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ORCIDLorena Anghel
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- affiliation: Universite Grenoble Alpes, Grenoble INP, France
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2020 – today
- 2024
[j22]Manon Dampfhoffer
, Thomas Mesquida, Alexandre Valentian, Lorena Anghel:
Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey. IEEE Trans. Neural Networks Learn. Syst. 35(9): 11906-11921 (2024)- [c99]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. DATE 2024: 1-6 - [c98]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. DATE 2024: 1-6 - [c97]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. ETS 2024: 1-6 - [i6]Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. CoRR abs/2401.04744 (2024) - [i5]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. CoRR abs/2401.06195 (2024) - [i4]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. CoRR abs/2401.12416 (2024) - 2023
- [j21]Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 150-164 (2023) - [j20]Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel:
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1885-1897 (2023) - [j19]Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda:
Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4246-4259 (2023) - [j18]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. ACM Trans. Embed. Comput. Syst. 22(5s): 131:1-131:25 (2023) - [j17]Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel:
Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study. IEEE Trans. Emerg. Top. Comput. Intell. 7(3): 731-741 (2023) - [c96]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. DATE 2023: 1-6 - [c95]Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT 2023: 1-7 - [c94]Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel:
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS 2023: 1-4 - [c93]Manon Dampfhoffer, Thomas Mesquida, Emmanuel Hardy, Alexandre Valentian, Lorena Anghel:
Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting. ICASSP 2023: 1-5 - [c92]Manon Dampfhoffer, Joel Minguet Lopez, Thomas Mesquida, Alexandre Valentian, Lorena Anghel:
Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses. IJCNN 2023: 1-8 - [c91]Yunus Emre Aslan, Florian Cacho, T. Kumar, D. K. Janardan, A. Kumar, F. Giner, M. Faurichon, Lorena Anghel:
Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging. IOLTS 2023: 1-6 - [c90]Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel:
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. ISVLSI 2023: 1-6 - [i3]Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy:
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR abs/2305.16187 (2023) - [i2]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. CoRR abs/2306.10185 (2023) - [i1]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. CoRR abs/2311.15816 (2023) - 2022
- [j16]Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu:
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3251-3259 (2022) - [j15]Lorena Anghel, Florian Cacho:
Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design. IEEE Trans. Emerg. Top. Comput. 10(2): 581-590 (2022) - [c89]Stéphane Burel, Adrian Evans, Lorena Anghel:
Improving DNN Fault Tolerance in Semantic Segmentation Applications. DFT 2022: 1-6 - [c88]Manon Dampfhoffer, Thomas Mesquida, Alexandre Valentian, Lorena Anghel:
Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks. ICANN (3) 2022: 359-370 - [c87]Kamal Danouchi, Guillaume Prenat, Lorena Anghel:
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. LATS 2022: 1-6 - [c86]Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. NANOARCH 2022: 11:1-11:6 - [c85]Nhat-Tan Phan, Lucile Soumah, Ahmed Sidi El Valli, Louis Hutin, Lorena Anghel, Ursula Ebels, Philippe Talatchian:
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing. NANOARCH 2022: 16:1-16:6 - 2021
- [c84]Stéphane Burel, Adrian Evans, Lorena Anghel:
Zero-Overhead Protection for CNN Weights. DFT 2021: 1-6 - [c83]Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu:
Fast Behavioral VerilogA Compact Model for Stochastic MTJ. ESSDERC 2021: 259-262 - [c82]Stéphane Burel, Adrian Evans, Lorena Anghel:
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators. IOLTS 2021: 1-6 - [c81]Florian Cacho, Lorena Anghel, Xavier Federspiel:
Monitoring Setup and Hold Timing Limits. IRPS 2021: 1-6 - 2020
- [j14]Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu:
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices. J. Electron. Test. 36(3): 313-326 (2020) - [c80]Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir:
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS 2020: 1-4 - [c79]Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan:
New Perspectives on Core In-field Path Delay Test. ITC 2020: 1-5
2010 – 2019
- 2019
- [c78]Giorgio Di Natale, Elena Ioana Vatajelu, Kalpana Senthamarai Kannan, Lorena Anghel:
Hidden-Delay-Fault Sensor for Test, Reliability and Security. DATE 2019: 316-319 - [c77]Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui:
Rebooting Computing: The Challenges for Test and Reliability. DFT 2019: 8138-8143 - [c76]Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, Mircea Stan:
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. FCCM 2019: 338 - [c75]Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu:
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. LATS 2019: 1-6 - [c74]Elena Ioana Vatajelu, Giorgio Di Natale, Lorena Anghel:
Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN). VTS 2019: 1-8 - 2018
- [j13]Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu:
Test and Reliability in Approximate Computing. J. Electron. Test. 34(4): 375-387 (2018) - [c73]Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel:
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI. DATE 2018: 997-998 - [c72]Elena Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat:
Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS 2018: 109-114 - [c71]Riddhi Jitendrakumar Shah, Florian Cacho, Vincent Huard, Souhir Mhira, D. Arora, Pankaj Agarwal, Shubham Kumar, S. Balaraman, Bijoy Kumar Singh, Lorena Anghel:
Investigation of speed sensors accuracy for process and aging compensation. IRPS 2018: 5 - [c70]Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu:
Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH 2018: 91-97 - [c69]Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena Ioana Vatajelu, Elisa Vianello:
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies. VLSI-SoC 2018: 176-179 - 2017
- [j12]Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori:
Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess. Microsystems 54: 14-25 (2017) - [c68]Ajith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel:
Workload dependent reliability timing analysis flow. DATE 2017: 736-737 - [c67]Elena Ioana Vatajelu, Lorena Anghel:
Reliability analysis of MTJ-based functional module for neuromorphic computing. IOLTS 2017: 126-131 - [c66]Florian Cacho, Ahmed Benhassain, Riddhi Jitendrakumar Shah, Souhir Mhira, Vincent Huard, Lorena Anghel:
Investigation of critical path selection for in-situ monitors insertion. IOLTS 2017: 247-252 - [c65]Elena Ioana Vatajelu, Lorena Anghel:
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability. NANOARCH 2017: 21-26 - 2016
- [c64]Ahmed Benhassain, Florian Cacho, Vincent Huard, Lorena Anghel:
Early failure prediction by using in-situ monitors: Implementation and application results. ERMAVSS@DATE 2016: 21-24 - [c63]Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel:
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis. ERMAVSS@DATE 2016: 38-40 - [c62]Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel:
Study of workload impact on BTI HCI induced aging of digital circuits. DATE 2016: 1020-1021 - [c61]Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori:
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. DSD 2016: 334-341 - [c60]Niels Thole, Lorena Anghel, Görschwin Fey:
A hybrid algorithm to conservatively check the robustness of circuits. ETS 2016: 1-2 - [c59]Florian Cacho, Ahmed Benhassain, Souhir Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, Vincent Knopik, Abhishek Jain, C. R. Parthasarathy, Lorena Anghel:
Activity profiling: Review of different solutions to develop reliable and performant design. IOLTS 2016: 47-50 - [c58]Ahmed Benhassain, Souhir Mhira, Florian Cacho, Vincent Huard, Lorena Anghel:
In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability. IVSW 2016: 1-5 - [c57]Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao:
Multi-context non-volatile content addressable memory using magnetic tunnel junctions. NANOARCH 2016: 103-108 - [c56]Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard:
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results. VTS 2016: 1 - 2015
- [j11]Marco Ottavi, Salvatore Pontarelli, Dimitris Gizopoulos, Cristiana Bolchini, Maria K. Michael, Lorena Anghel, Mehdi Baradaran Tahoori, Antonis M. Paschalis, Pedro Reviriego, Oliver Bringmann, Viacheslav Izosimov, Hans A. R. Manhaeve, Christos Strydis, Said Hamdioui:
Dependable Multicore Architectures at Nanoscale: The View From Europe. IEEE Des. Test 32(2): 17-28 (2015) - [c55]Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner:
Timing in-situ monitors: Implementation strategy and applications results. CICC 2015: 1-4 - [c54]M. Saliva, Florian Cacho, Vincent Huard, X. Federspiel, D. Angot, Ahmed Benhassain, Alain Bravaix, Lorena Anghel:
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI. DATE 2015: 441-446 - [c53]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Application-independent testing of multilevel interconnect in mesh-based FPGAs. DTIS 2015: 1-6 - [c52]M. Saliva, Florian Cacho, Cheikh Ndiaye, Vincent Huard, D. Angot, Alain Bravaix, Lorena Anghel:
Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology. IRPS 2015: 4 - 2014
- [j10]Lorena Anghel, Cristiana Bolchini, Salvatore Pontarelli:
Editorial. Microprocess. Microsystems 38(6): 565-566 (2014) - [j9]Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. Microprocess. Microsystems 38(6): 620-635 (2014) - [c51]Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot:
System on chip project: Integration of a Motion-JPEG video decoder. EWME 2014: 167-170 - [c50]Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel:
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD 2014: 61-67 - [c49]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Cost-efficient of a cluster in a mesh SRAM-based FPGA. IOLTS 2014: 75-80 - [c48]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - 2013
- [j8]Thomas Frank, Stéphane Moreau, Cédrick Chappaz, Patrick Leduc, Lucile Arnaud, Aurélie Thuaire, Emmanuel Chery, F. Lorut, Lorena Anghel, Gilles Poupon:
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric. Microelectron. Reliab. 53(1): 17-29 (2013) - [c47]Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. DFTS 2013: 296-301 - [c46]Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. IOLTS 2013: 7-12 - 2012
- [j7]Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi:
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems. J. Electron. Test. 28(1): 137-150 (2012) - [j6]Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi:
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. J. Electron. Test. 28(6): 817-829 (2012) - [c45]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c44]Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi:
Efficient link-level error resilience in 3D NoCs. DDECS 2012: 127-132 - [c43]Michael Nicolaidis, Vladimir Pasca, Lorena Anghel:
Through-silicon-via built-in self-repair for aggressive 3D integration. IOLTS 2012: 91-96 - 2011
- [j5]Claudia Rusu, Lorena Anghel, Dimiter Avresky:
Adaptive inter-layer message routing in 3D networks-on-chip. Microprocess. Microsystems 35(7): 613-631 (2011) - [c42]N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel:
Bottom-up digital system-level reliability modeling. CICC 2011: 1-4 - [c41]Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh:
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. ETS 2011: 93-98 - [c40]Michael Nicolaidis, Vladimir Pasca, Lorena Anghel:
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems. ETS 2011: 208 - [c39]Aymen Fradi, Michael Nicolaidis, Lorena Anghel:
Memory BIST with address programmability. IOLTS 2011: 79-85 - [c38]Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi:
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis. LATW 2011: 1-6 - 2010
- [c37]Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola:
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. DATE 2010: 275-278 - [c36]Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi:
Fault tolerant communication in 3D integrated systems. DSN Workshops 2010: 131-135 - [c35]Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi:
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. ETS 2010: 258 - [c34]Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi:
Configurable serial fault-tolerant link for communication in 3D integrated systems. IOLTS 2010: 115-120 - [c33]Claudia Rusu, Lorena Anghel, Dimiter Avresky:
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip. IOLTS 2010: 121-126 - [c32]Michael Nicolaidis, Vladimir Pasca, Lorena Anghel:
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems. IOLTS 2010: 218
2000 – 2009
- 2009
- [c31]Lorena Anghel:
HOT TOPIC - Concurrent SoC development and end-to-end planning. DATE 2009: 430 - [c30]Hai Yu, Michael Nicolaidis, Lorena Anghel:
An effective approach to detect logic soft errors in digital circuits based on GRAAL. ISQED 2009: 236-240 - 2008
- [c29]Claudia Rusu, Cristian Grecu, Lorena Anghel:
Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. DELTA 2008: 32-37 - [c28]Christophe Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel:
Digital Implementation of a BIST Method based on Binary Observations. DSD 2008: 709-713 - [c27]Claudia Rusu, Cristian Grecu, Lorena Anghel:
Communication Aware Recovery Configurations for Networks-on-Chip. IOLTS 2008: 201-206 - [c26]Claudia Rusu, Cristian Grecu, Lorena Anghel:
Improving the scalability of checkpoint recovery for networks-on-chip. ISCAS 2008: 2793-2796 - 2007
- [j4]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. J. Electron. Test. 23(6): 625-633 (2007) - [j3]Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sébastien Fregonese, Thomas Zimmer, Lorena Anghel, Trong-Trinh Dang, Régis Leveugle:
CNTFET Modeling and Reconfigurable Logic-Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2365-2379 (2007) - [c25]Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh:
Essential Fault-Tolerance Metrics for NoC Infrastructures. IOLTS 2007: 37-42 - [c24]Claudia Rusu, Antonin Bougerol, Lorena Anghel, Cécile Weulersse, Nadine Buard, S. Benhammadi, Nicolas Renaud, Guillaume Hubert, Frederic Wrobel, Thierry Carrière, Rémi Gaillard:
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. IOLTS 2007: 137-145 - [c23]Lorena Anghel, Michael Nicolaidis:
Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. IWANN 2007: 422-429 - [c22]Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis:
Efficient timing closure with a transistor level design flow. VLSI-SoC 2007: 312-315 - 2006
- [c21]Guillaume Hubert, Antonin Bougerol, Florent Miller, Nadine Buard, Lorena Anghel, Thierry Carrière, Frederic Wrobel, Rémi Gaillard:
Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells. IOLTS 2006: 63-74 - [c20]Lorena Anghel, Michael Nicolaidis, Nadine Buard:
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? IOLTS 2006: 85 - [c19]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. IOLTS 2006: 165-172 - [c18]Lorena Anghel, Cristiano Lazzari, Michael Nicolaidis:
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies. LATW 2006: 186-191 - 2005
- [j2]Michael Nicolaidis, Lorena Anghel, Nadir Achouri:
Memory Defect Tolerance Architectures for Nanotechnologies. J. Electron. Test. 21(4): 445-455 (2005) - [c17]Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis:
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. IOLTS 2005: 29-34 - [c16]Lorena Anghel, Michael Nicolaidis:
Simulation and Mitigation of Single Event Effects. IOLTS 2005: 81 - [c15]Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert:
Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS 2005: 309-312 - [c14]Cristiano Lazzari, Lorena Anghel, Ricardo Reis:
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. VLSI-SoC 2005: 331-344 - 2004
- [j1]Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis:
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. J. Electron. Test. 20(4): 413-421 (2004) - [c13]Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco:
Coupling Different Methodologies to Validate Obsolete Microprocessors. DFT 2004: 250-255 - [c12]Lorena Anghel, Nadir Achouri, Michael Nicolaidis:
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie. PRDC 2004: 315-320 - [c11]Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. VTS 2004: 313-318 - 2003
- [c10]Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities. DFT 2003: 459-466 - [c9]Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary:
Preliminary Validation of an Approach Dealing with Processor Obsolescence. DFT 2003: 493- - [c8]Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
Memory Built-In Self-Repair for Nanotechnologies. IOLTS 2003: 94- - [c7]Raoul Velazco, Lorena Anghel, S. Saleh:
A Methodology for Test Replacement Solutions of Obsolete Processors. IOLTS 2003: 209-213 - 2002
- [c6]Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis:
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. DFT 2002: 99-107 - [c5]Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis:
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. LATW 2002: 126-129 - 2001
- [b1]Lorena Anghel:
Les limites technologiques du silicium et tolérance aux fautes. (Fault tolerance versus technological limitations of silicon). Grenoble Institute of Technology, France, 2001 - 2000
- [c4]Lorena Anghel, Michael Nicolaidis:
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. DATE 2000: 591-598 - [c3]Lorena Anghel, Dan Alexandrescu, Michael Nicolaidis:
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy. SBCCI 2000: 237-242 - [c2]Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal:
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. VTS 2000: 55-66
1990 – 1999
- 1999
- [c1]Th. Calin, Lorena Anghel, Michael Nicolaidis:
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. VTS 1999: 135-142
Coauthor Index
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