This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique for inter-die interconnects (Thru-Silicon Vias TSVs).

Abstract—Three-dimensional integration is a key technology for systems whose performance / power requirements cannot be achieved by traditional silicon ...

Jan 20, 2017 · Testing is one of the major challenges of 3D integration. This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique ...

Mar 27, 2011 · Testing is one of the major challenges of 3D integration. This paper proposes a configurable Interconnect Built-In Self-Test (BIST) technique ...

We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must ...

These techniques include Built-In-Self-Test / Diagnosis / Repair. (BIST/D/R), Reduced Pad-Count Testing (RPCT), Test. Data Compression (TDC), etc. If a ...

A built-in-self-test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack using through-silicon-via (TSV) technology to overcome the memory ...

Wide I/O [4] also supports interconnect testing using ... , “Configurable Thru-Silicon-Via interconnect Built-In. Self-Test and diagnosis,” in 12th LATW, 2011, pp ...

A self-test methodology and test structures for testing Through Silicon Vias ... Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis.

Local digital test sequences are also needed to test circuits designed considering DfT. A straightforward built-in self-test approach [12] detects faults ...