default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID14th IOLTS 2008: Rhodes, Greece
- 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece. IEEE Computer Society 2008, ISBN 978-0-7695-3264-6
On-Line Error Detection and Correction
- Jaume Abella
, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
On-Line Failure Detection and Confinement in Caches. 3-9 - Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
An Enhanced Logic BIST Architecture for Online Testing. 10-15 - Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. 16-21
Self-Checking Circuits and Error Detecting Codes
- Marc Hunger, Sybille Hellebrand:
Verification and Analysis of Self-Checking Properties through ATPG. 25-30 - Richard Ruzicka, Lukás Sekanina, Roman Prokop:
Physical Demonstration of Polymorphic Self-Checking Circuits. 31-36 - Michael Richter, Klaus Oberländer, Michael Gössel:
New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability. 37-42
Radiation Hardening Techniques
- Norbert Seifert:
Special Session 1: Radiation Hardening Techniques. 43-44 - Subhasish Mitra:
Soft Error Protection Techniques. 45 - Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche:
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. 46-48 - Norbert Seifert:
Soft Error Rates of Hardened Sequentials utilizing Local Redundancy. 49-50
Soft Error Detection and Correction Methodologies
- M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji:
False Error Study of On-line Soft Error Detection Mechanisms. 53-58 - Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin:
Integrating Scan Design and Soft Error Correction in Low-Power Applications. 59-64 - Alodeep Sanyal, Syed M. Alam, Sandip Kundu:
A Built-In Self-Test Scheme for Soft Error Rate Characterization. 65-70
Control-Flow Checking and Fault-Tolerance in Special Applications
- Ramtilak Vemu, Jacob A. Abraham:
Budget-Dependent Control-Flow Error Detection. 73-78 - Paolo Maistri, Cyril Excoffon, Régis Leveugle:
Software Self-Testing of a Symmetric Cipher with Error Detection Capability. 79-84 - Ricardo de Oliveira Duarte, Luiz de Siqueira Martins-Filho, Guilherme F. T. Knop, Ricardo S. Prado:
A Fault-Tolerant Attitude Determination System Based on COTS Devices. 85-90
Fault Injection
- Ashish Darbari, Bashir M. Al-Hashimi, Peter Harrod, Daryl Bradley:
A New Approach for Transient Fault Injection Using Symbolic Simulation. 93-98 - Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi:
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation. 99-104
Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?
- Michael Nicolaidis:
Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force? 105-106
Invited Talk
- Shi-Jie Wen, Dan Alexandrescu, Renaud Perez:
A Systematical Method of Quantifying SEU FIT. 109-114
Mitigation Techniques for Transient Errors
- Taiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, Shigeo Satoh:
Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs. 117-122 - Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris:
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. 123-128 - Sreenivas Gangadhar, Michael N. Skoufis, Spyros Tragoudas:
Propagation of Transients Along Sensitizable Paths. 129-134 - Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante:
On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. 135-140
Memory Self-Test and Self-Repair
- Wilson J. Pérez H., Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs. 143-148 - Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos:
A BISR Architecture for Embedded Memories. 149-154 - Costas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan:
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. 155-160
Panel
- Tino Heijmen:
Special Session 3 - Panel: SER in Automotive: what is the impact of the AEC Q100-G spec? 161-162
Posters
- Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Yield Improvement, Fault-Tolerance to the Rescue?. 165-166 - Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena:
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. 167-168 - Yuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou:
SRAM Cell Design Protected from SEU Upsets. 169-170 - Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand:
A Modular Memory BIST for Optimized Memory Repair. 171-172 - Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi:
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. 173-174 - Zhengfeng Huang, Huaguo Liang:
A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies. 175-176 - Tobias Koal, Heinrich Theodor Vierhaus:
Basic Architecture for Logic Self Repair. 177-178 - Piotr Gawkowski, Janusz Sosnowski:
Developing Fault Injection Environment for Complex Experiments. 179-181 - Michel Pignol, Thierry Parrain, Vincent Claverie, Christian Boléat, Guy Estaves:
Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448. 182-184 - Nikolaos G. Bartzoudis, Vasileios Tantsios, Klaus D. McDonald-Maier:
Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded Microprocessors. 185-187 - Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan:
Fault Tolerant Reversible Finite Field Arithmetic Circuits. 188-189 - Nachiketa Das, Pranab Roy, Hafizur Rahaman:
On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element. 190-191 - Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
Totally Fault Tolerant RNS Based FIR Filters. 192-194
Reliability and Circuit Simulation
- Rob Aitken:
Special Session 4: Reliability and Circuit Simulation. 195-196 - Yu (Kevin) Kao:
Modeling and Simulation of Circuit Aging in Scaled CMOS Design. 197
Fault-Tolerance and On-Line Testing for Networks-on-Chip, Labs-on-Chip and Multiport Chips
- Claudia Rusu, Cristian Grecu, Lorena Anghel:
Communication Aware Recovery Configurations for Networks-on-Chip. 201-206 - Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi:
Reliability in Application Specific Mesh-Based NoC Architectures. 207-212 - Yang Zhao, Krishnendu Chakrabarty:
On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors. 213-218 - Piotr Zajac, Jacques Henri Collet, Andrzej Napieralski:
Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips. 219-224
Parametric Testing Techniques
- Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. 227-232 - Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell:
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. 233-238 - Muhammad Mudassar Nisar, Abhijit Chatterjee:
Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters. 239-244
Radiation-Induced SER
- Tino Heijmen:
Soft-Error Vulnerability of Sub-100-nm Flip-Flops. 247-252 - Damien Leroy, Rémi Gaillard, Erwin Schäfer, Cyrille Beltrando, Shi-Jie Wen, Richard Wong:
Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node. 253-257
Self-Test Generation Techniques
- Samara Sudireddy, Jayawant Kakade, Dimitri Kagaris:
Deterministic Built-in TPG with Segmented FSMs. 261-266 - Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick:
A Low-Cost Accumulator-Based Test Pattern Generation Architecture. 267-272 - Andreas Merentitis, George Theodorou, Mihalis Giorgaras, Nektarios Kranitis:
Directed Random SBST Generation for On-Line Testing of Pipelined Processors. 273-279
Laser-Based Fault Injection in Memories
- Antonin Bougerol, Florent Miller, Nadine Buard:
SDRAM Architecture & Single Event Effects Revealed with Laser. 283-288 - Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle:
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. 289-294 - Vincent Pouget, Alexandre Douin, Gilles Foucard, Paul Peronnard, Dean Lewis, Pascal Fouillat, Raoul Velazco:
Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection. 295-301
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-06 01:45 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
