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ORCIDDATE 2018: Dresden, Germany
- Jan Madsen, Ayse K. Coskun:
2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. IEEE 2018, ISBN 978-3-9819263-0-9 - Sung Kim
, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe:
MATIC: Learning around errors for efficient low-voltage neural network accelerators. 1-6 - Junki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim:
Maximizing system performance by balancing computation loads in LSTM accelerators. 7-12 - Xiaoming Chen, Danny Z. Chen, Xiaobo Sharon Hu:
moDNN: Memory optimal DNN training on GPUs. 13-18 - Dimitrios Stamoulis, Ermao Cai, Da-Cheng Juan, Diana Marculescu:
HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks. 19-24 - Hsuan Hsiao, Jason Helge Anderson:
Sensei: An area-reduction advisor for FPGA high-level synthesis. 25-30 - Shantanu Dutt, Ouwen Shi:
A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. 31-36 - Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson:
High-level synthesis of software-customizable floating-point cores. 37-42 - Eugene Goldberg, Matthias Güdemann, Daniel Kroening, Rajdeep Mukherjee:
Efficient verification of multi-property designs (The benefit of wrong assumptions). 43-48 - Tobias Seufert, Christoph Scholl:
Combining PDR and reverse PDR for hardware model checking. 49-54 - Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz:
Symbolic quick error detection using symbolic initial state for pre-silicon verification. 55-60 - Lihao Liang, Paul E. McKenney, Daniel Kroening, Tom Melham:
Verification of tree-based hierarchical read-copy update in the Linux kernel. 61-66 - Jingweijia Tan, Kaige Yan:
HVSM: Hardware-variability aware streaming processors' management policy in GPUs. 67-72 - Srinivasa Reddy Punyala, Theodoros Marinakis, Arash Komaee, Iraklis Anagnostopoulos:
Throughput optimization and resource allocation on GPUs under multi-application execution. 73-78 - Zhaoying Li, Lei Ju, Hongjun Dai, Xin Li, Mengying Zhao, Zhiping Jia:
Set variation-aware shared LLC management for CPU-GPU heterogeneous architecture. 79-84 - Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. 85-90 - Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. 91-96 - Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Advancing hardware security using polymorphic and stochastic spin-hall effect devices. 97-102 - Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres:
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. 103-108 - Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen:
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. 109-112 - Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Spintronic normally-off heterogeneous system-on-chip design. 113-118 - Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao:
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers. 119-124 - Seyedhamidreza Motaman, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
Novel application of spintronics in computing, sensing, storage and cybersecurity. 125-130 - Qi An, Sébastien Le Beux, Ian O'Connor, Jacques-Olivier Klein:
Large scale, high density integration of all spin logic. 131-136 - Mathias Soeken, Thomas Häner, Martin Roetteler:
Programming quantum computers using design automation. 137-146 - Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza:
Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not? 147-152 - Ye Tian, Qian Zhang, Ting Wang, Qiang Xu:
Lookup table allocation for approximate computing with memory under quality constraints. 153-158 - Yun Long, Xueyuan She, Saibal Mukhopadhyay:
Accelerating biophysical neural network simulation with region of interest based approximation. 159-164 - Jinghan Zhang, Hamed Tabkhi, Gunar Schirner:
DS-DSE: Domain-specific design space exploration for streaming applications. 165-170 - Junlong Zhou, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu, Yue Ma, Gongxuan Zhang, Jianming Yan:
Variation-aware task allocation and scheduling for improving reliability of real-time MPSoCs. 171-176 - Jianmin Qian, Jian Li, Ruhui Ma:
Topology-aware virtual resource management for heterogeneous multicore systems. 177-182 - Heechun Park, Taewhan Kim:
Structure optimizations of neuromorphic computing architectures for deep neural network. 183-188 - Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li:
CCR: A concise convolution rule for sparse neural network accelerators. 189-194 - Thomas Haine, Johan Segers, Denis Flandre, David Bol:
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. 195-200 - Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Degradation analysis of high performance 14nm FinFET SRAM. 201-206 - Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi:
Investigating power outage effects on reliability of solid-state drives. 207-212 - Jiankang Ren, Ran Bi, Xiaoyan Su, Qian Liu, Guowei Wu, Guozhen Tan:
Workload-aware harmonic partitioned scheduling for probabilistic real-time systems. 213-218 - Leandro Soares Indrusiak, Alan Burns, Borislav Nikolic:
Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs. 219-224 - Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, Rakesh B. Bobba:
A design-space exploration for allocating security tasks in multicore real-time systems. 225-230 - Thanh-Dat Nguyen, Yassine Ouhammou, Emmanuel Grolleau, Julien Forget, Claire Pagetti, Pascal Richard:
Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications. 231-236 - Houxiang Ji, Linghao Song, Li Jiang, Hai Helen Li, Yiran Chen:
ReCom: An efficient resistive accelerator for compressed deep neural networks. 237-240 - Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity. 241-244 - Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan:
ACCLIB: Accelerators as libraries. 245-248 - Isaar Ahmad, Sanjog Patil, Smruti R. Sarangi:
HPXA: A highly parallel XML parser. 249-252 - Seyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi, Sherief Reda:
QoR-aware power capping for approximate big data processing. 253-256 - Kai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt:
Exact multi-objective design space exploration using ASPmT. 257-260 - Diego G. Tomé, Paulo C. Santos, Luigi Carro, Eduardo C. de Almeida, Marco A. Z. Alves:
HIPE: HMC instruction predication extension applied on database processing. 261-264 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Parametric failure modeling and yield analysis for STT-MRAM. 265-268 - Martin Schoeberl:
One-way shared memory. 269-272 - Rui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang, Teng Tian:
An efficient resource-optimized learning prefetcher for solid state drives. 273-276 - George Ungureanu, José Edil G. de Medeiros, Ingo Sander:
Bridging discrete and continuous time models with atoms. 277-280 - Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann:
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. 281-284 - Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay:
A highly efficient full-system virtual prototype based on virtualization-assisted approach. 285-288 - Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars:
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling. 289-292 - Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung:
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. 293-296 - Marcello Dalpasso, Davide Bertozzi, Michele Favalli:
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices. 297-300 - Rohini Gulve, Virendra Singh:
ATPG power guards: On limiting the test power below threshold. 301-304 - Alexander S. Kulikov:
Improving circuit size upper bounds using SAT-solvers. 305-308 - Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. 309-314 - Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson:
SAT-based redundancy removal. 315-318 - Soheil Hashemi, Hokchhay Tann, Francesco Buttafuoco, Sherief Reda:
Approximate computing for biometrie security systems: A case study on iris scanning. 319-324 - Tai-Chou Wu, Yu-ping Ma, Li-Pin Chang:
Flash read disturb management using adaptive cell bit-density with in-place reprogramming. 325-330 - Ahmad Albaqsami, Maryam S. Hosseini, Nader Bagherzadeh:
HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors. 331-336 - Reena Panda, Xinnian Zheng, Andreas Gerstlauer, Lizy Kurian John:
CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications. 337-342 - Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li:
SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. 343-348 - Tim Schmidt, Zhongqi Cheng, Rainer Dömer:
Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. 349-354 - Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty:
Trident: A comprehensive timing error resilient technique against choke points at NTC. 355-360 - Byung-Su Kim, Joon-Sung Yang:
Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring. 361-366 - Venakata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay:
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations. 367-372 - Sudipta Mondal, Krishnendu Chakrabarty:
Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies. 373-378 - Felipe A. Kuentzer, Leonardo Rezende Juracy, Alexandre M. Amory:
On the reuse of timing resilient architecture for testing path delay faults in critical paths. 379-384 - Jan Burchard, Dominik Erb, Bernd Becker:
Characterization of possibly detected faults by accurately computing their detection probability. 385-390 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy:
Ultra-low energy circuit building blocks for security technologies. 391-394 - Itamar Levi, Yehuda Rudin, Alexander Fish, Osnat Keren:
Embedded randomness and data dependencies design paradigm: Advantages and challenges. 395-400 - Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting on-chip power management for side-channel security. 401-406 - Jilan Lin, Lixue Xia, Zhenhua Zhu, Hanbo Sun, Yi Cai, Hui Gao, Ming Cheng, Xiaoming Chen, Yu Wang, Huazhong Yang:
Rescuing memristor-based computing with non-linear resistance levels. 407-412 - Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique:
PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture. 413-418 - Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez:
Multi-precision convolutional neural networks on heterogeneous hardware. 419-424 - Onur Tunali, Mustafa Altun:
Logic synthesis and defect tolerance for memristive crossbar arrays. 425-430 - Alma Pröbstl, Sangyoung Park, Swaminathan Narayanaswamy, Sebastian Steinhorst, Samarjit Chakraborty:
SOH-aware active cell balancing strategy for high power battery packs. 431-436 - Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii, Massimo Poncino:
GIS-based optimal photovoltaic panel floorplanning for residential installations. 437-442 - Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. 443-448 - Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik:
WALL: A writeback-aware LLC management for PCM-based main memory systems. 449-454 - Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Design and integration of hierarchical-placement multi-level caches for real-time systems. 455-460 - Kyle Kuan, Tosiron Adegbija:
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. 461-466 - Mohd Syafiq Mispan, Haibo Su, Mark Zwolinski, Basel Halak:
Cost-efficient design for modeling attacks resistant PUFs. 467-472 - Orlando Arias, Fahim Rahman, Mark M. Tehranipoor, Yier Jin:
Device attestation: Past, present, and future. 473-478 - Omid Aramoon, Xi Chen, Gang Qu:
A reconfigurable scan network based IC identification for embedded devices. 479-484 - Lai Leng Woo, Mark Zwolinski, Basel Halak:
Early detection of system-level anomalous behaviour using hardware performance counters. 485-490 - Leilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng:
Compact modeling of carbon nanotube thin film transistors for flexible circuit design. 491-496 - Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak:
A high-speed design methodology for inductive coupling links in 3D-ICs. 497-502 - Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler:
An exact method for design exploration of quantum-dot cellular automata. 503-508 - Soheil Nazar Shahsavani, Bo Zhang, Massoud Pedram:
Accurate margin calculation for single flux quantum logic cells. 509-514 - Yue Ma, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu:
Improving reliability for real-time systems through dynamic recovery. 515-520 - Johannes Bund, Christoph Lenzen, Moti Medina:
Optimal metastability-containing sorting networks. 521-526 - Kai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li:
MAUI: Making aging useful, intentionally. 527-532 - Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee:
EXPERT: Effective and flexible error protection by redundant multithreading. 533-538 - Björn Forsberg, Luca Benini, Andrea Marongiu:
HePREM: Enabling predictable GPU execution on heterogeneous SoC. 539-544 - Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
Circuit carving: A methodology for the design of approximate hardware. 545-550 - Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan:
ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation. 551-556 - Anuj Pathania, Jörg Henkel:
Task scheduling for many-cores with S-NUCA caches. 557-562 - Sung-Ming Wu, Kai-Hsiang Lin, Li-Pin Chang:
KVSSD: Close integration of LSM trees and flash translation layer for write-efficient KV store. 563-568 - Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, Li Jiang:
In-growth test for monolithic 3D integrated SRAM. 569-572 - Jeroen P. G. van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano:
A co-design methodology for scalable quantum processors and their classical electronic interface. 573-576 - Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk:
Approximate quaternary addition with the fast carry chains of FPGAs. 577-580 - Seongmin Hong, Inho Lee, Yongjun Park:
NN compactor: Minimizing memory and logic resources for small neural networks. 581-584 - Alexander Lamprecht, Swaminathan Narayanaswamy, Sebastian Steinhorst:
Improving fast charging efficiency of reconfigurable battery packs. 585-588 - Arun Adiththan, S. Ramesh, Soheil Samii:
Cloud-assisted control of ground vehicles using adaptive computation offloading techniques. 589-592 - Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
FusionCache: Using LLC tags for DRAM cache. 593-596 - Philipp Niemann, Robert Wille, Rolf Drechsler:
Improved synthesis of Clifford+T quantum functionality. 597-600 - Yuyang Wang, M. Ashkan Seyedi, Rui Wu, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng:
Energy-efficient channel alignment of DWDM silicon photonic transceivers. 601-604 - Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar:
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. 605-608 - Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann:
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. 609-612 - Rafael Billig Tonetto, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
Precise evaluation of the fault sensitivity of OoO superscalar processors. 613-616 - Hyukjoong Kim, Kyuhwa Han, Dongkun Shin:
StreamFTL: Stream-level address translation scheme for memory constrained flash storage. 617-620 - Basireddy Karunakar Reddy, Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh:
Online concurrent workload classification for multi-core energy management. 621-624 - Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuangang Wang, Yuan Xie:
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory. 625-628 - Yuanqi Shen, Amin Rezaei, Hai Zhou:
SAT-based bit-flipping attack on logic encryptions. 629-632 - Fabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich, Stefan Heinen:
AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cells. 633-636 - Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Towards high-performance polarity-controllable FETs with 2D materials. 637-641 - Saru Vig, Guiyuan Jiang, Siew-Kei Lam:
Dynamic skewed tree for fast memory integrity verification. 642-647 - Cezar Reinbrecht, Bruno Forlin, Andreas Zankl, Johanna Sepúlveda:
Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCs. 648-653 - Jakob Stangl, Thomas Lorünser, Sai Manoj Pudukotai Dinakarrao:
A fast and resource efficient FPGA implementation of secret sharing for storage applications. 654-659 - Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta:
Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel. 660-665 - Gabriele Miorandi, Francesco Stefanni, Federico Fraccaroli, Davide Quaglia:
A SystemC-based Simulator for design space exploration of smart wireless systems. 666-671 - Ming Ding, Guibin Chen, Pieter Harpe, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips, Arthur H. M. van Roermund:
A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT. 672-675 - Michele Lora, Stefano Centomo, Davide Quaglia, Franco Fummi:
Automatic integration of cycle-accurate descriptions with continuous-time models for cyber-physical virtual platforms. 676-681 - Rouhollah Mahfouzi, Amir Aminifar, Soheil Samii, Ahmed Rezine, Petru Eles, Zebo Peng:
Stability-aware integrated routing and scheduling for control applications in Ethernet networks. 682-687 - Liying Li, Peijin Cong, Kun Cao, Junlong Zhou, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu:
Feedback control of real-time EtherCAT networks for reliability enhancement in CPS. 688-693 - Wanli Chang, Debayan Roy, Xiaobo Sharon Hu, Samarjit Chakraborty:
Cache-aware task scheduling for maximizing control performance. 694-699 - Kent Gauen, Ryan Dailey, Yung-Hsiang Lu, Eunbyung Park, Wei Liu, Alexander C. Berg, Yiran Chen:
Three years of low-power image recognition challenge: Introduction to special session. 700-703 - Jincheng Yu, Kaiyuan Guo, Yiming Hu, Xuefei Ning, Jiantao Qiu, Huizi Mao, Song Yao, Tianqi Tang, Boxun Li, Yu Wang, Huazhong Yang:
Real-time object detection towards high power efficiency. 704-708 - Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li:
A retrospective evaluation of energy-efficient object detection solutions on embedded devices. 709-714 - Duseok Kang, Donghyun Kang, Jintaek Kang, Sungjoo Yoo, Soonhoi Ha:
Joint optimization of speed, accuracy, and energy for embedded image recognition systems. 715-720 - Yehuda Naveh, Elham Kashefi, James R. Wootton, Koen Bertels:
Theoretical and practical aspects of verification of quantum computers. 721-730 - Trinayan Baruah, Yifan Sun, Shi Dong, David R. Kaeli, Norm Rubin:
Airavat: Improving energy efficiency of heterogeneous applications. 731-736 - Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino:
All-digital embedded meters for on-line power estimation. 737-742 - Davide Zoni, Luca Cremona, William Fornaciari:
PowerProbe: Run-time power modeling through automatic RTL instrumentation. 743-748 - Sangyoung Park, Samarjit Chakraborty:
Design optimization of photovoltaic arrays on curved surfaces. 749-754 - Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. 755-760 - Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Logic optimization with considering boolean relations. 761-766 - Shubham Rai, Michael Raitza, Akash Kumar:
Technology mapping flow for emerging reconfigurable silicon nanowire transistors. 767-772 - Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. 773-778 - Yang Song, Olivier Alavoine, Bill Lin:
Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems. 779-784 - Mohammad Taghi Teimoori, Muhammad Abdullah Hanif, Alireza Ejlali, Muhammad Shafique:
AdAM: Adaptive approximation management for the non-volatile memory hierarchies. 785-790 - Nour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
A cross-layer adaptive approach for performance and power optimization in STT-MRAM. 791-796 - Zhijian Pan, Miao Li, Jian Yao, Hong Lu, Zuochang Ye, Yanfeng Li, Yan Wang:
Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques. 797-802 - Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse:
Mitigation of NBTI induced performance degradation in on-chip digital LDOs. 803-808 - Fritz G. Previlon, Charu Kalra, David R. Kaeli, Paolo Rech:
Evaluating the impact of execution parameters on program vulnerability in GPU applications. 809-814 - Bing Li, Linghao Song, Fan Chen, Xuehai Qian, Yiran Chen, Hai Helen Li:
ReRAM-based accelerator for deep learning. 815-820 - Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Viji Srinivasan, Swagath Venkataramani:
Exploiting approximate computing for deep learning acceleration. 821-826 - Muhammad Shafique, Theocharis Theocharides, Christos-Savvas Bouganis, Muhammad Abdullah Hanif, Faiq Khalid, Rehan Hafiz, Semeen Rehman:
An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era. 827-832 - Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of quantized neural networks on heterogeneous all-programmable devices. 833-838 - Pierluigi Nuzzo, Michele Lora, Yishai A. Feldman, Alberto L. Sangiovanni-Vincentelli:
CHASE: Contract-based requirement engineering for cyber-physical system design. 839-844 - Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Resilience evaluation via symbolic fault injection on intermediate code. 845-850 - Normann Decker, Boris Dreyer, Philip Gottschling, Christian Hochberger, Alexander Lange, Martin Leucker, Torben Scheffel, Simon Wegener, Alexander Weiss:
Online analysis of debug trace data for embedded systems. 851-856 - Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler:
Testbench qualification for SystemC-AMS timed data flow models. 857-860 - José Edil G. de Medeiros, George Ungureanu, Ingo Sander:
An algebra for modeling continuous time systems. 861-864 - Romain Jacob, Licong Zhang, Marco Zimmerling, Jan Beutel, Samarjit Chakraborty, Lothar Thiele:
TTW: A Time-Triggered Wireless design for CPS. 865-868 - Charalambos Konstantinou, Eduardo Chielle, Michail Maniatakos:
PHYLAX: Snapshot-based profiling of real-time embedded devices via JTAG interface. 869-872 - Kuan-Ting Ho, Chung-Ta King, Bhaskar Das, Yung-Ju Chang:
Characterizing display QoS based on frame dropping for power management of interactive applications on smartphones. 873-876 - Hanchen Yang, Feiyang Kang, Caiwen Ding, Ji Li, Jaemin Kim, Donkyu Baek, Shahin Nazarian, Xue Lin, Paul Bogdan, Naehyuck Chang:
Prediction-based fast thermoelectric generator reconfiguration for energy harvesting from vehicle radiators. 877-880 - Chaochao Feng, Daheng Yue, Zhenyu Zhao, Zhuofan Liao:
A parameterized timing-aware flip-flop merging algorithm for clock power reduction. 881-884 - Seungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang:
Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study. 885-888 - Saman Fröhlich, Daniel Große, Rolf Drechsler:
Approximate hardware generation using symbolic computer algebra employing grobner basis. 889-892 - José Luis Imaña:
Reconfigurable implementation of GF(2m) bit-parallel multipliers. 893-896 - Paulo C. Santos, Geraldo F. Oliveira, João Paulo C. de Lima, Marco A. Z. Alves, Luigi Carro, Antonio C. S. Beck:
Processing in 3D memories to speed up operations on complex data structures. 897-900 - Kun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin:
An efficient NBTI-aware wake-up strategy for power-gated designs. 901-904 - Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. 905-908 - Martin Schoeberl:
Design of a time-predictable multicore processor: The T-CREST project. 909-912 - Muhammad Abdullah Hanif, Rehan Hafiz, Muhammad Shafique:
Error resilience analysis for systematically employing approximate computing in convolutional neural networks. 913-916 - Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar, Muhammad Shafique:
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. 917-920 - Bryan Donyanavard, Amir M. Rahmani, Tiago Mück, Kasra Moazemmi, Nikil D. Dutt:
Gain scheduled control for nonlinear power management in CMPs. 921-924 - Thomas Lefeuvre, Imen Fassi, Christoph Cullmann, Gernot Gebhard, Emin-Koray Kasnakli, Isabelle Puaut, Steven Derrien:
Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction. 925-930 - Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat:
Using multifunctional standardized stack as universal spintronic technology for IoT. 931-936 - Benjamin Uhlig, Jie Liang, Jaehyun Lee, Raphael Ramos, Abitha Dhavamani, Nicole Nagy, Jean Dijon, Hanako Okuno, Dipankar Kalita, Vihar P. Georgiev, Asen Asenov, Salvatore M. Amoroso, Liping Wang, Campbell Millar, F. Konemann, Bernd Gotsmann, Goncalo Goncalves, Bingan Chen, Reeturaj Pandey, R. Chen, Aida Todri-Sanial:
Progress on carbon nanotube BEOL interconnects. 937-942 - Simon Reder, Leonard Masing, Harald Bucher, Timon D. ter Braak, Timo Stripf, Jürgen Becker:
A WCET-aware parallel programming model for predictability enhanced multi-core architectures. 943-948 - Arman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza:
Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation. 949-954 - Farzad Samie, Sebastian Paul, Lars Bauer, Jörg Henkel:
Highly efficient and accurate seizure prediction on constrained IoT devices. 955-960 - Syed Muhammad Abubakar, Wala Saadeh, Muhammad Awais Bin Altaf:
A wearable long-term single-lead ECG processor for early detection of cardiac arrhythmia. 961-966 - Christos Kyrkou, George Plastiras, Theocharis Theocharides, Stylianos I. Venieris, Christos-Savvas Bouganis:
DroNet: Efficient convolutional neural network detector for real-time UAV applications. 967-972 - Tianhao Huang, Guohao Dai, Yu Wang, Huazhong Yang:
HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing. 973-978 - Christoph Schorn, Andre Guntoro, Gerd Ascheid:
Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators. 979-984 - Mohamed Ayoub Neggaz, Hasan Erdem Yantir, Smaïl Niar, Ahmed M. Eltawil, Fadi J. Kurdahi:
Rapid in-memory matrix multiplication using associative processor. 985-990 - Vijeta Rathore, Vivek Chaturvedi, Amit Kumar Singh, Thambipillai Srikanthan, R. Rohith, Siew-Kei Lam, Muhammad Shafique:
HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems. 991-996 - Ajith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel:
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI. 997-998 - Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars:
An industrial case study of low cost adaptive voltage scaling using delay test patterns. 999-1000 - Tao Wang, Zhangchun Shi, Junlin Huang, Huaxing Tang, Wu Yang, Junna Zhong:
A case study for using dynamic partitioning based solution in volume diagnosis. 1001-1002 - Jan Schat:
On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter. 1003-1004 - Chih-Hong Cheng, Frederik Diehl, Gereon Hinz, Yassine Hamza, Georg Nührenberg, Markus Rickert, Harald Ruess, Michael Truong-Le:
Neural networks for safety-critical applications - Challenges, experiments and perspectives. 1005-1006 - Thomas Maurin, Laurent-Frederic Ducreux, George Caraiman, Philippe Sissoko:
IoT security assessment through the interfaces P-SCAN test bench platform. 1007-1008 - Simon Rokicki, Erven Rohou, Steven Derrien:
Supporting runtime reconfigurable VLIWs cores through dynamic binary translation. 1009-1014 - Zelalem Birhanu Aweke, Todd M. Austin:
uSFI: Ultra-lightweight software fault isolation for IoT-class devices. 1015-1020 - Sara Royuela, Luís Miguel Pinho, Eduardo Quiñones:
Converging safety and high-performance domains: Integrating OpenMP into Ada. 1021-1026 - Jorge Castro-Godínez, Sven Esser, Muhammad Shafique, Santiago Pagani, Jörg Henkel:
Compiler-driven error analysis for designing approximate accelerators. 1027-1032 - Liliana Andrade, Adrien Prost-Boucle, Frédéric Pétrot:
Overview of the state of the art in embedded machine learning. 1033-1038 - Alexandre Carbon, Jean-Marc Philippe, Olivier Bichler, Renaud Schmit, Benoît Tain, David Briand, Nicolas Ventroux, Michel Paindavoine, Olivier Brousse:
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks. 1039-1044 - Sheng Lin, Ning Liu, Mahdi Nazemi, Hongjia Li, Caiwen Ding, Yanzhi Wang, Massoud Pedram:
FFT-based deep learning deployment in embedded systems. 1045-1050 - Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini:
A transprecision floating-point platform for ultra-low power computing. 1051-1056 - Keni Qiu, Weiwen Chen, Yuanchao Xu, Lixue Xia, Yu Wang, Zili Shao:
A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN. 1057-1062 - Jan Lucas, Sohan Lal, Ben H. H. Juurlink:
Optimal DC/AC data bus inversion coding. 1063-1068 - Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul:
LASER: A hardware/software approach to accelerate complicated loops on CGRAs. 1069-1074 - Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
A time-multiplexed FPGA overlay with linear interconnect. 1075-1080 - Shail Dave, Mahesh Balasubramanian, Aviral Shrivastava:
URECA: Unified register file for CGRAs. 1081-1086 - Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao:
Optimizing the data placement and transformation for multi-bank CGRA computing system. 1087-1092 - Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio López-Buedo, Martí Torrents, Ferad Zyulkyarov, Michael Enrico, Óscar González de Dios:
dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter. 1093-1098 - Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das:
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. 1099-1104 - A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew P. J. Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn:
The transprecision computing paradigm: Concept, design, and applications. 1105-1110 - Falk Schellenberg, Dennis R. E. Gnad, Amir Moradi, Mehdi Baradaran Tahoori:
An inside job: Remote power analysis attacks on FPGAs. 1111-1116 - Florian Bache, Christina Plump, Tim Güneysu:
Confident leakage assessment - A side-channel evaluation framework based on confidence intervals. 1117-1122 - Zelalem Birhanu Aweke, Todd M. Austin:
Øzone: Efficient execution with zero timing leakage for modern microarchitectures. 1123-1128 - Jakub Breier, Dirmanto Jap, Shivam Bhasin:
SCADPA: Side-channel assisted differential-plaintext attack on bit permutation based ciphers. 1129-1134 - Alwin Zulehner, Alexandru Paler, Robert Wille:
Efficient mapping of quantum circuits to the IBM QX architectures. 1135-1138 - Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin:
Parallel code generation of synchronous programs for a many-core architecture. 1139-1142 - Davide Gadioli, Ricardo Nobre, Pedro Pinto, Emanuele Vitali, Amir H. Ashouri, Gianluca Palermo, João M. P. Cardoso, Cristina Silvano:
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications. 1143-1146 - Kamal Lamichhane, Carlos Moreno, Sebastian Fischmeister:
Non-intrusive program tracing of non-preemptive multitasking systems using power consumption. 1147-1150 - Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. 1151-1154 - Mohsen Imani, Saransh Gupta, Tajana Rosing:
GenPIM: Generalized processing in-memory to accelerate data intensive applications. 1155-1158 - Manish Kumar Jaiswal, Hayden Kwok-Hay So:
Universal number posit arithmetic generator on FPGA. 1159-1162 - Gang Li, Fanrong Li, Tianli Zhao, Jian Cheng:
Block convolution: Towards memory-efficient inference of large-scale CNNs on FPGA. 1163-1166 - Lu Zhang, Wei Hu, Armaiti Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu, Ryan Kastner:
Examining the consequences of high-level synthesis optimizations on power side-channel. 1167-1170 - Mustafa Khairallah, Rajat Sadhukhan, Radhamanjari Samanta, Jakub Breier, Shivam Bhasin, Rajat Subhra Chakraborty, Anupam Chattopadhyay, Debdeep Mukhopadhyay:
DFARPA: Differential fault attack resistant physical design automation. 1171-1174 - Yidong Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han:
An energy-efficient stochastic computational deep belief network. 1175-1178 - Alwin Zulehner, Robert Wille:
Pushing the number of qubits below the "minimum": Realizing compact boolean components for quantum logic. 1179-1182 - Yuanhui Ni, Weiwen Chen, Wenjuan Cui, Yuanchun Zhou, Keni Qiu:
Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN. 1183-1186 - Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah:
ORIENT: Organized interleaved ECCs for new STT-MRAM caches. 1187-1190 - Xavier Carpent, Gene Tsudik, Norrathep Rattanavipanon:
ERASMUS: Efficient remote attestation via self-measurement for unattended settings. 1191-1194 - Junchul Choi, Donghyun Kang, Soonhoi Ha:
End-to-end latency analysis of cause-effect chains in an engine management system. 1195-1198 - Jai-Ming Lin, Chien-Yu Huang:
General floorplanning methodology for 3D ICs with an arbitrary bonding style. 1199-1202 - Matthias Traub, Hans-Jörg Vögel, Eric Sax, Thilo Streichert, Jérôme Härri:
Digitalization in automotive and industrial systems. 1203-1204 - Xiaoming Chen, Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu:
Design and optimization of FeFET-based crossbars for binary convolution neural networks. 1205-1210 - Benjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak:
Low-power 3D integration using inductive coupling links for neurotechnology applications. 1211-1216 - Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Francky Catthoor, Siebren Schaafsma:
Mapping of local and global synapses on spiking neuromorphic hardware. 1217-1222 - Xun Jiao, Vahideh Akhlaghi, Yu Jiang, Rajesh K. Gupta:
Energy-efficient neural networks using approximate computation reuse. 1223-1228 - Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Multi-bit non-volatile spintronic flip-flop. 1229-1234 - Shivam Swami, Kartik Mohanram:
ADAM: Architecture for write disturbance mitigation in scaled phase change memory. 1235-1240 - Xin Shi, Fei Wu, Shunzhuo Wang, Changsheng Xie, Zhonghai Lu:
Program error rate-based wear leveling for NAND flash memory. 1241-1246 - Jinhua Cui, Youtao Zhang, Jianhang Huang, Weiguo Wu, Jun Yang:
ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs. 1247-1252 - Aydin Aysu, Michael Orshansky, Mohit Tiwari:
Binary Ring-LWE hardware with power side-channel countermeasures. 1253-1258 - Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini:
High speed ASIC implementations of leakage-resilient cryptography. 1259-1264 - Elie Noumon Allini, Oto Petura, Viktor Fischer, Florent Bernard:
Optimization of the PLL configuration in a PLL-based TRNG design. 1265-1270 - Roberto Medina, Etienne Borde, Laurent Pautet:
Availability enhancement and analysis for mixed-criticality systems on multi-core. 1271-1276 - Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Mixed-criticality scheduling with memory bandwidth regulation. 1277-1282 - Saurav Kumar Ghosh, Soumyajit Dey, Dip Goswami, Daniel Mueller-Gritschneder, Samarjit Chakraborty:
Design and validation of fault-tolerant embedded controllers. 1283-1288 - Ahmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian M. Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni, Michael T. Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, Xunzhao Yin:
Computing with ferroelectric FETs: Devices, models, systems, and applications. 1289-1298 - Saibal Mukhopadhyay, Marilyn Wolf, Mohammed Faisal Amir, Evan Gebhardt, Jong Hwan Ko, Jaeha Kung, Burhan Ahmad Musassar:
The CAMEL approach to stacked sensor smart cameras. 1299-1303 - Jiahao Wu, Timothy Blattner, Walid Keyrouz, Shuvra S. Bhattacharyya:
A design tool for high performance image processing on multicore platforms. 1304-1309 - Bart Goossens, Hiep Luong, Jan Aelterman, Wilfried Philips:
Quasar, a high-level programming language and development environment for designing smart vision systems on embedded platforms. 1310-1315 - Marco Trevisi, H. C. Bandala, Jorge Fernández-Berni, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez:
Concurrent focal-plane generation of compressed samples from time-encoded pixel values. 1316-1320 - Axel Weissenfeld, Bernhard Strobl, Franz Daubner:
Contactless finger and face capturing on a secure handheld embedded device. 1321-1326 - Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
A faithful binary circuit model with adversarial noise. 1327-1332 - Charalampos Antoniadis, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
EVT-based worst case delay estimation under process variation. 1333-1338 - Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang:
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. 1339-1344 - Chun-Xun Lin, Martin D. F. Wong:
Accelerate analytical placement with GPU: A generic approach. 1345-1350 - Biresh Kumar Joardar, Karthi Duraisamy, Partha Pratim Pande:
High performance collective communication-aware 3D Network-on-Chip architectures. 1351-1356 - Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco:
A soft-error resilient route computation unit for 3D Networks-on-Chips. 1357-1362 - Jayasimha Sai Koduri, Iraklis Anagnostopoulos:
SPA: Simple pool architecture for application resource allocation in many-core systems. 1364-1368 - Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong, Jiang Xu:
RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems. 1369-1374 - Zhuohui Duan, Haikun Liu, Xiaofei Liao, Hai Jin:
HME: A lightweight emulator for hybrid memory. 1375-1380 - Marco Elver, Christopher J. Banks, Paul B. Jackson, Vijay Nagarajan:
VerC3: A library for explicit state synthesis of concurrent systems. 1381-1386 - Yao Xiao, Shahin Nazarian, Paul Bogdan:
Prometheus: Processing-in-memory heterogeneous architecture design from a multi-layer network theoretic strategy. 1387-1392 - Joscha Benz, Christoph Gerum, Oliver Bringmann:
Advancing source-level timing simulation using loop acceleration. 1393-1398 - Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya:
Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. 1399-1404 - Guan-Ru Lai, Chun-Yu Lin, Tsung-Yi Ho:
Pump-aware flow routing algorithm for programmable microfluidic devices. 1405-1410 - Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. 1411-1416 - Vincent T. Lee, Armin Alaghi, Luis Ceze:
Correlation manipulating circuits for stochastic computing. 1417-1422 - Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu:
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. 1423-1428 - Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos:
A novel fault tolerant cache architecture based on orthogonal latin squares theory. 1429-1434 - Debjyoti Bhattacharjee, Luca G. Amarù, Anupam Chattopadhyay:
Technology-aware logic synthesis for ReRAM based in-memory computing. 1435-1440 - Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang:
Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. 1441-1446 - Hiromitsu Awano, Takashi Sato:
Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs. 1447-1452 - Ye Wang, Michael Orshansky:
Efficient helper data reduction in SRAM PUFs via lossy compression. 1453-1458 - Zijun Long, Xiaohang Wang, Yingtao Jiang, Guofeng Cui, Li Zhang, Terrence S. T. Mak:
Improving the efficiency of thermal covert channels in multi-/many-core systems. 1459-1464 - Soheil Nazar Shahsavani, Alireza Shafaei, Massoud Pedram:
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement. 1465-1468 - Nikolaos Sketopoulos, Christos P. Sotiriou, Stavros Simoglou:
Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies. 1469-1472 - Ying-Chi Wei, Radhamanjari Samanta, Yih-Lang Li:
LESAR: A dynamic line-end spacing aware detailed router. 1473-1476 - Edoardo Fusella, Alessandro Cilardo:
Understanding turn models for adaptive routing: The modular approach. 1477-1480 - Souradip Sarkar, Manil Dev Gomony:
Quater-imaginary base for complex number arithmetic circuits. 1481-1483 - Yasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann:
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis. 1484-1487 - D. Celia, Vinita Vasudevan, Nitin Chandrachoodan:
Optimizing power-accuracy trade-off in approximate adders. 1488-1491 - Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung:
Improving the error behavior of DRAM by exploiting its Z-channel property. 1492-1495 - Arne Heittmann, Tobias G. Noll:
Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells. 1496-1499 - Jihoon Park, Seokjun Lee, Hojung Cha:
Accurate prediction of smartphones' skin temperature by considering exothermic components. 1500-1503 - Urbi Chatterjee, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Trustworthy proofs for sensor data using FPGA based physically unclonable functions. 1504-1507 - Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards fully automated TLM-to-RTL property refinement. 1508-1511 - Alvaro Velasquez, Sumit Kumar Jha:
In-memory computing using paths-based logic and heterogeneous components. 1512-1515 - Leonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet:
Non-intrusive testing technique for detection of Trojans in asynchronous circuits. 1516-1519 - Milos Grujic, Bohan Yang, Vladimir Rozic, Ingrid Verbauwhede:
Towards inter-vendor compatibility of true random number generators for FPGAs. 1520-1523 - Xianzhang Chen, Edwin Hsing-Mean Sha, Yuansong Zeng, Chaoshu Yang, Weiwen Jiang, Qingfeng Zhuge:
Efficient wear leveling for inodes of file systems on persistent memories. 1524-1527 - Sneha N. Ved, Manu Awasthi:
Exploring non-volatile main memory architectures for handheld devices. 1528-1531 - Armin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mück, Ahmed Nassar, Amir M. Rahmani, Thomas Wild, Nikil D. Dutt, Rolf Ernst, Andreas Herkersdorf, Fadi J. Kurdahi:
Design methodologies for enabling self-awareness in autonomous systems. 1532-1537 - Alif Ahmed, Farimah Farahmandi, Prabhat Mishra:
Directed test generation using concolic testing on RTL models. 1538-1543 - Neil Veira, Zissis Poulos, Andreas G. Veneris:
Suspect set prediction in RTL bug hunting. 1544-1549 - Alessandro Danese, Valeria Bertacco, Graziano Pravadelli:
Symbolic assertion mining for security validation. 1550-1555 - Daniela Ritirc, Armin Biere, Manuel Kauers:
Improving and extending the algebraic approach for verifying gate-level multipliers. 1556-1561 - Danil Sokolov, Alessandro de Gennaro, Andrey Mokhov:
Reconfigurable asynchronous pipelines: From formal models to silicon. 1562-1567 - Alexander Fedotov, Julien Schmaltz:
Automatic generation of hardware checkers from formal micro-architectural specifications. 1568-1573 - Antonio Iannopollo, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli:
Specification decomposition for synthesis from libraries of LTL Assume/Guarantee contracts. 1574-1579 - Liwei Zhou, Yiorgos Makris:
Hardware-assisted rootkit detection via on-line statistical fingerprinting of process execution. 1580-1585 - Robert Schilling, Mario Werner, Stefan Mangard:
Securing conditional branches in the presence of fault attacks. 1586-1591 - Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran:
Towards provably-secure performance locking. 1592-1597 - Jonathan Cruz, Yuanwen Huang, Prabhat Mishra, Swarup Bhunia:
An automated configurable Trojan insertion framework for dynamic trust benchmarks. 1598-1603 - Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li:
Extending the lifetime of NVMs with compression. 1604-1609 - Taehyun Kwon, Muhammad Imran, Jung Min You, Joon-Sung Yang:
Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement. 1610-1615 - Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li, Zheng Li:
An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines. 1616-1621 - Yuncheng Guo, Yu Hua, Pengfei Zuo:
DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory. 1622-1627 - Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. 1628-1633 - Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel:
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces. 1634-1639 - Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan:
Computing-in-memory with spintronics. 1640-1645 - Jintao Yu, Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui:
Memristive devices for computation-in-memory. 1646-1651 - Augusto Vega, Alper Buyuktosunoglu, Pradip Bose:
Energy-secure swarm power management. 1652-1657 - Seyedeh Golsana Ghaemi, Iman Ahmadpour, Mehdi Ardebili, Hamed Farbeh:
SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality. 1658-1663
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