KR970054502A - Vertical thin film transistor and its manufacturing method, and pixel array for ultra thin liquid crystal display device using same - Google Patents

Abstract

A novel vertical thin film transistor, a method of manufacturing the same, and a pixel array for an ultra-thin liquid crystal display device using the same are disclosed. The pixel electrode is formed on the transparent substrate. On the pixel electrode, source and drain electrodes are formed in a vertical structure by a tapered etching method with an ohmic semiconductor layer and an insulating layer interposed therebetween. The active semiconductor layer and the gate insulating layer are sequentially formed on the source and drain electrodes. On the gate insulating layer, a gate electrode is formed by self-aligning the source and drain electrodes.

Since an overlap width is not formed between the source electrode and the gate electrode, parasitic capacitance may be reduced.

Description

Vertical thin film transistor and its manufacturing method, and pixel array for ultra thin liquid crystal display device using same

Since this is an open matter, no full text was included.

3 is a cross-sectional view of a vertical thin film transistor according to the present invention.

Claims (5)

Transparent substrates; A pixel electrode formed on the substrate; Source and drain electrodes disposed on the pixel electrode and formed in a vertical structure by a tapered etching method with an ohmic semiconductor layer and an insulating layer interposed therebetween; An active semiconductor layer and a gate insulating layer sequentially formed on the source and drain electrodes; And a gate electrode disposed on the gate insulating layer and self-aligned to the source and drain electrodes. The thin film transistor of claim 1, wherein the active semiconductor layer is inclined due to the source and drain electrodes formed by the tapered etching. The thin film transistor of claim 1, wherein the ohmic semiconductor layer is formed of amorphous silicon doped with impurities. Forming a pixel electrode on the transparent substrate; Sequentially depositing a first metal layer, a first ohmic semiconductor layer, a first insulating layer, a second ohmic semiconductor layer, and a second metal layer on the resultant product; Tapering etching the stacked layers by a photolithography process to form a drain electrode formed of a first metal layer and a source electrode made of a second metal layer; Forming an active semiconductor layer on the resultant; Sequentially forming a gate insulating layer and a second insulating layer on the resultant product; Forming a photoresist pattern on the resultant by performing white exposure using the source and drain electrodes; Etching the second insulating layer using the photoresist pattern as a mask; Removing the photoresist pattern; And forming a gate electrode on the resultant product. A pixel electrode formed on the transparent substrate, a source and drain electrode positioned on the pixel electrode and having a vertical structure by a tapered etching method with an ohmic semiconductor layer and an insulating layer interposed therebetween, and an active layer formed on the source and drain electrodes in this order A thin film transistor having a semiconductor layer and a gate insulating layer and a gate electrode formed on the gate insulating layer and self-aligned to the source and drain electrodes; A gate bus line connected to the gate electrode; A data busline connected to the source and drain electrodes; And a storage capacitor formed on the thin film transistor. ※ Note: The disclosure is based on the initial application.