JPH05249485A - Active matrix liquid crystal display having thin-film transistor for switching - Google Patents

Active matrix liquid crystal display having thin-film transistor for switching

Info

Publication number
JPH05249485A
JPH05249485A JP23524091A JP23524091A JPH05249485A JP H05249485 A JPH05249485 A JP H05249485A JP 23524091 A JP23524091 A JP 23524091A JP 23524091 A JP23524091 A JP 23524091A JP H05249485 A JPH05249485 A JP H05249485A
Authority
JP
Japan
Prior art keywords
liquid crystal
crystal display
film transistor
glass substrate
active matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP23524091A
Other languages
Japanese (ja)
Inventor
Hiroaki Kakinuma
弘明 柿沼
Mikio Mori
幹雄 毛利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP23524091A priority Critical patent/JPH05249485A/en
Publication of JPH05249485A publication Critical patent/JPH05249485A/en
Withdrawn legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To improve an opening rate by disposing pixel electrodes consisting of transparent electrode films formed on a glass substrate and disposing thin-film transistors (TFTs) within the wiring regions of these pixel electrodes. CONSTITUTION:The pixel electrodes 11 consisting of the transparent electrode films are provided on a glass substrate 10. These pixel electrodes 11 are connected to n<+> layers (sources) 16 doped with phosphorus in order to obtain the ohmic contact of the TFTs via source lines 18. Gate lines 12 are wired in an (x) direction on the glass substrate 10. Gate insulating layer 15 are formed on the gate lines 12 and semiconductor layers 14 consisting of amorphous silicon, etc., are provided thereon. The n<+> layers (sources) 16 doped with the phosphorus in order to obtain the ohmic contact and the n<+> layers (drains 17) doped with the phosphorus in order to obtain the ohmic contact are provided on these semiconductor layers 14. Drain lines 13 are provided thereon; in a (y) direction in this embodiment. As a result, such thing that the picture element part are partly occupied by TFTs is eliminated and the opening rate is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶ディスプレイ、液
晶シャッター等の画素のスイッチングに用いる薄膜トラ
ンジスタを具備するアクティブマトリックス液晶ディス
プレイに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display having a thin film transistor used for switching pixels such as a liquid crystal display and a liquid crystal shutter.

【0002】[0002]

【従来の技術】図3は従来の画素スイッチング用薄膜ト
ランジスタを具備する液晶ディスプレイの平面図であ
る。この図に示すように、21は透明電極膜からなる画
素電極であり、薄膜トランジスタのソースに接続されて
いる。22はゲート線、23は画像信号が印加されるド
レイン線である。24は画素電極をオンオフするための
薄膜トランジスタ(以下、TFTという)であり、ゲー
ト、ソース、ドレインの各電極、非晶質シリコン等の半
導体層25、ゲート線とドレイン線の絶縁層も兼ねたゲ
ート絶縁層26から成っている。ここで、通常、TFT
はゲート線とドレイン線の交点付近の画素領域内に配置
されている。
2. Description of the Related Art FIG. 3 is a plan view of a liquid crystal display having a conventional pixel switching thin film transistor. As shown in this figure, 21 is a pixel electrode made of a transparent electrode film, which is connected to the source of the thin film transistor. Reference numeral 22 is a gate line, and 23 is a drain line to which an image signal is applied. Reference numeral 24 is a thin film transistor (hereinafter referred to as TFT) for turning on / off the pixel electrode, each electrode of the gate, source and drain, a semiconductor layer 25 such as amorphous silicon, and a gate which also serves as an insulating layer of a gate line and a drain line. It is composed of an insulating layer 26. Here, usually TFT
Are arranged in the pixel region near the intersection of the gate line and the drain line.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うなTFTの配置では、TFTが画素面積の一部を占め
てしまうので、開口率が低下するという問題が生じ、こ
れはカラー化や冗長度を増すための複数TFT化に伴っ
て大きな問題となっていた。本発明は、以上述べた開口
率の低下を除去するため、TFTをゲート線とドレイン
線の領域内に配し、開口率の大きいスイッチング用薄膜
トランジスタを備えたアクティブマトリックス液晶ディ
スプレイを提供することを目的とする。
However, in such a TFT arrangement, since the TFT occupies a part of the pixel area, there arises a problem that the aperture ratio is lowered, which causes colorization and redundancy. Along with the increase in the number of TFTs, there has been a big problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide an active matrix liquid crystal display having a switching thin film transistor having a large aperture ratio by arranging TFTs in the regions of the gate line and the drain line in order to eliminate the above-mentioned decrease in aperture ratio. And

【0004】[0004]

【課題を解決するための手段】本発明は、上記目的を達
成するために、ガラス基板上の各画素にスイッチング用
薄膜トランジスタを備えたアクティブマトリックス液晶
ディスプレイにおいて、ガラス基板上に形成された透明
電極膜による画素電極と、該画素電極の配線領域内に薄
膜トランジスタを配置するようにしたものである。
In order to achieve the above object, the present invention provides an active matrix liquid crystal display in which each pixel on a glass substrate has a switching thin film transistor, and a transparent electrode film formed on the glass substrate. The pixel electrode and the thin film transistor are arranged in the wiring region of the pixel electrode.

【0005】[0005]

【作用】本発明によれば、ガラス基板上に形成された透
明電極膜による画素電極と、該画素電極の配線領域内に
薄膜トランジスタを配置し、ゲート電極を画素中に引き
出すことなく、そのまま利用し、主にゲート線とドレイ
ン線の交差領域上にチャンネルを形成する。従って、従
来のように画素部の一部をTFTが占めることがなくな
り、開口率を向上させることができる。
According to the present invention, the pixel electrode made of the transparent electrode film formed on the glass substrate and the thin film transistor are arranged in the wiring region of the pixel electrode, and the gate electrode is used as it is without being drawn out into the pixel. , Forming a channel mainly on the intersection area of the gate line and the drain line. Therefore, unlike the conventional case, the TFT does not occupy a part of the pixel portion, and the aperture ratio can be improved.

【0006】[0006]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例を示す液
晶ディスプレイの平面図、図2はその液晶ディスプレイ
のA−A線断面図である。図中、11はガラス基板10
上に形成された透明電極膜による画素電極、12はゲー
ト線、13はドレイン線である。また、14は非晶質シ
リコン等の半導体層、15はゲート絶縁層、16はオー
ミックコンタクトを得るためのリンをドープしたn+
(ソース)、17はオーミックコンタクトを得るための
リンをドープしたn+ 層(ドレイン)、18は画素電極
11が接続されるソース線である。
Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a plan view of a liquid crystal display showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA of the liquid crystal display. In the figure, 11 is a glass substrate 10.
Pixel electrodes made of a transparent electrode film formed above, 12 are gate lines, and 13 are drain lines. Further, 14 is a semiconductor layer such as amorphous silicon, 15 is a gate insulating layer, 16 is an n + layer (source) doped with phosphorus for obtaining ohmic contact, and 17 is doped with phosphorus for obtaining ohmic contact. The n + layer (drain), 18 is a source line to which the pixel electrode 11 is connected.

【0007】なお、作製プロセスは従来例と同じで良
い。ここでは、TFTのチャンネルがドレイン線の内部
に存在する。図1および図2において、ガラス基板10
上には透明電極膜による画素電極11が設けられ、その
画素電極11はソース線18を介して、TFTのオーミ
ックコンタクトを得るためのリンをドープしたn+
(ソース)16に接続される。また、ガラス基板10上
にはゲート線12がここではx方向に配線される。その
ゲート線12上にはゲート絶縁層15が形成され、その
上に非晶質シリコン等の半導体層14が設けられる。そ
の半導体層14上にはオーミックコンタクトを得るため
のリンをドープしたn+ 層(ソース)16、オーミック
コンタクトを得るためのリンをドープしたn+ 層(ドレ
イン)17が設けられ、その上にここではy方向にドレ
イン線13が形成される。
The manufacturing process may be the same as the conventional example. Here, the channel of the TFT exists inside the drain line. 1 and 2, the glass substrate 10
A pixel electrode 11 made of a transparent electrode film is provided on the upper side, and the pixel electrode 11 is connected via a source line 18 to a phosphorus-doped n + layer (source) 16 for obtaining ohmic contact of the TFT. Further, the gate line 12 is wired on the glass substrate 10 in the x direction here. A gate insulating layer 15 is formed on the gate line 12, and a semiconductor layer 14 such as amorphous silicon is provided on the gate insulating layer 15. On the semiconductor layer 14, a phosphorus-doped n + layer (source) 16 for obtaining an ohmic contact and a phosphorus-doped n + layer (drain) 17 for obtaining an ohmic contact are provided. Then, the drain line 13 is formed in the y direction.

【0008】図4は本発明の他の実施例を示す液晶ディ
スプレイの平面図である。図中、31はガラス基板上に
形成された透明電極膜による画素電極、32はゲート
線、33はドレイン線である。また、34は非晶質シリ
コン等の半導体層、35はゲート絶縁層、36は画素電
極31が接続されるソース線である。このように、チャ
ンネル幅を大きくしたい場合には、図4に示すように、
ゲート線32からゲートを分岐するようにすれば良い。
FIG. 4 is a plan view of a liquid crystal display showing another embodiment of the present invention. In the figure, 31 is a pixel electrode made of a transparent electrode film formed on a glass substrate, 32 is a gate line, and 33 is a drain line. Further, 34 is a semiconductor layer such as amorphous silicon, 35 is a gate insulating layer, and 36 is a source line to which the pixel electrode 31 is connected. In this way, when it is desired to increase the channel width, as shown in FIG.
The gate may be branched from the gate line 32.

【0009】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。
The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

【0010】[0010]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、TFTのチャンネルをドレイン線あるいはゲー
ト線と同一領域に配置するようにしたので、従来のよう
に画素部の一部をTFTが占めることがなくなり、開口
率を向上させることができる。
As described above in detail, according to the present invention, the channel of the TFT is arranged in the same region as the drain line or the gate line. The TFT is not occupied and the aperture ratio can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す液晶ディスプレイの平面
図である。
FIG. 1 is a plan view of a liquid crystal display showing an embodiment of the present invention.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.

【図3】従来の画素スイッチング用薄膜トランジスタを
具備する液晶ディスプレイの平面図である。
FIG. 3 is a plan view of a liquid crystal display including a conventional pixel switching thin film transistor.

【図4】本発明の他の実施例を示す液晶ディスプレイの
平面図である。
FIG. 4 is a plan view of a liquid crystal display showing another embodiment of the present invention.

【符号の説明】 10 ガラス基板 11,31 画素電極 12,32 ゲート線 13,33 ドレイン線 14,34 半導体層 15,35 ゲート絶縁層 16 n+ 層(ソース) 17 n+ 層(ドレイン) 18,36 ソース線[Explanation of reference signs] 10 glass substrate 11,31 pixel electrode 12,32 gate line 13,33 drain line 14,34 semiconductor layer 15,35 gate insulating layer 16 n + layer (source) 17 n + layer (drain) 18, 36 source line

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ガラス基板上の各画素にスイッチング用
薄膜トランジスタを備えたアクティブマトリックス液晶
ディスプレイにおいて、(a)ガラス基板上に形成され
た透明電極膜による画素電極と、(b)該画素電極の配
線領域内に薄膜トランジスタを配置することを特徴とす
るスイッチング用薄膜トランジスタを備えたアクティブ
マトリックス液晶ディスプレイ。
1. An active matrix liquid crystal display having a switching thin film transistor in each pixel on a glass substrate, wherein (a) a pixel electrode made of a transparent electrode film formed on the glass substrate and (b) wiring of the pixel electrode. An active matrix liquid crystal display having a switching thin film transistor, characterized in that a thin film transistor is arranged in a region.
【請求項2】 前記配線領域はゲート線とドレイン線の
交差領域である請求項1記載のスイッチング用薄膜トラ
ンジスタを備えたアクティブマトリックス液晶ディスプ
レイ。
2. The active matrix liquid crystal display having a switching thin film transistor according to claim 1, wherein the wiring region is a region where a gate line and a drain line intersect with each other.
JP23524091A 1991-09-17 1991-09-17 Active matrix liquid crystal display having thin-film transistor for switching Withdrawn JPH05249485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23524091A JPH05249485A (en) 1991-09-17 1991-09-17 Active matrix liquid crystal display having thin-film transistor for switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23524091A JPH05249485A (en) 1991-09-17 1991-09-17 Active matrix liquid crystal display having thin-film transistor for switching

Publications (1)

Publication Number Publication Date
JPH05249485A true JPH05249485A (en) 1993-09-28

Family

ID=16983158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23524091A Withdrawn JPH05249485A (en) 1991-09-17 1991-09-17 Active matrix liquid crystal display having thin-film transistor for switching

Country Status (1)

Country Link
JP (1) JPH05249485A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039622A (en) * 1996-11-28 1998-08-17 김영환 Liquid crystal display
KR100500682B1 (en) * 1996-11-28 2005-10-14 비오이 하이디스 테크놀로지 주식회사 LCD and its manufacturing method
KR100569712B1 (en) * 1998-04-24 2006-09-20 삼성전자주식회사 Thin film transistor substrate
WO2010107027A1 (en) * 2009-03-17 2010-09-23 凸版印刷株式会社 Thin film transistor array and image display device using thin film transistor array

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039622A (en) * 1996-11-28 1998-08-17 김영환 Liquid crystal display
KR100500682B1 (en) * 1996-11-28 2005-10-14 비오이 하이디스 테크놀로지 주식회사 LCD and its manufacturing method
KR100569712B1 (en) * 1998-04-24 2006-09-20 삼성전자주식회사 Thin film transistor substrate
WO2010107027A1 (en) * 2009-03-17 2010-09-23 凸版印刷株式会社 Thin film transistor array and image display device using thin film transistor array
JP4743348B2 (en) * 2009-03-17 2011-08-10 凸版印刷株式会社 THIN FILM TRANSISTOR ARRAY AND IMAGE DISPLAY DEVICE USING THIN FILM TRANSISTOR ARRAY
JPWO2010107027A1 (en) * 2009-03-17 2012-09-20 凸版印刷株式会社 THIN FILM TRANSISTOR ARRAY AND IMAGE DISPLAY DEVICE USING THIN FILM TRANSISTOR ARRAY
US8742423B2 (en) 2009-03-17 2014-06-03 Toppan Printing Co., Ltd. Thin-film transistor array and image display device in which thin-film transistor array is used

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981203