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Low Power Digital CMOS DesignJune 1995
Abstract
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Cited By
Dwivedi S, Khare K and Dadoria A Low-Power High Speed 1-bit Full Adder Circuit Design Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies, (1-5)- Chen K (2019). A Low-Memory-Access Length-Adaptive Architecture for 2$$^n$$n-Point FFT, Circuits, Systems, and Signal Processing, 34:2, (459-482), Online publication date: 1-Feb-2015.
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