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Automating RT-level operand isolation to minimize power consumption in datapaths

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N. WehnAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 624 - 633

https://doi.org/10.1145/343647.343873

Published: 01 January 2000 Publication History

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SEMBA SSAITO HTATSUOKA MFUJIMURA K(2020)Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL ModelsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2020VLP0004E103.A:12(1417-1426)Online publication date: 1-Dec-2020
https://doi.org/10.1587/transfun.2020VLP0004
Simevski ASchrape OBenito C(2018)Comparative Analyses of Low-Power IC Design Techniques based on Chip Measurements2018 16th Biennial Baltic Electronics Conference (BEC)10.1109/BEC.2018.8600987(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/BEC.2018.8600987
Udupi SUrdahl JStoffel DKunz W(2017)Dynamic Power Optimization Based on Formal Property Checking of Operations2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.56(227-232)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.56
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Automating RT-level operand isolation to minimize power consumption in datapaths
1. Hardware

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

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Ivo Bolsens
IMEC, Leuven, Belgium

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SEMBA SSAITO HTATSUOKA MFUJIMURA K(2020)Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL ModelsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2020VLP0004E103.A:12(1417-1426)Online publication date: 1-Dec-2020
https://doi.org/10.1587/transfun.2020VLP0004
Simevski ASchrape OBenito C(2018)Comparative Analyses of Low-Power IC Design Techniques based on Chip Measurements2018 16th Biennial Baltic Electronics Conference (BEC)10.1109/BEC.2018.8600987(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/BEC.2018.8600987
Udupi SUrdahl JStoffel DKunz W(2017)Dynamic Power Optimization Based on Formal Property Checking of Operations2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.56(227-232)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.56
Lai SLee YLei S(2013)Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT) Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT) in a Digital Radio Mondiale (DRM) and DRM+ ReceiverJournal of Low Power Electronics and Applications10.3390/jlpea30200993:2(99-113)Online publication date: 24-May-2013
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ITO KNUMATA T(2013)Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose ProcessorsIEICE Transactions on Electronics10.1587/transele.E96.C.463E96.C:4(463-472)Online publication date: 2013
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Sahm HSauppe MMarkert EHorn THeinkel UOtto K(2013)Optimized ASIC/FPGA design flow for energy efficient network nodesBell Labs Technical Journal10.1002/bltj.2163418:3(195-209)Online publication date: Dec-2013
https://doi.org/10.1002/bltj.21634
Weng SKuo YChang S(2012)Timing Optimization in Sequential Circuit by Exploiting Clock-Gating LogicACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954817:2(1-15)Online publication date: 1-Apr-2012
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Li LChoi K(2011)Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applicationsIET Communications10.1049/iet-com.2010.09335:17(2501-2508)Online publication date: 25-Nov-2011
https://doi.org/10.1049/iet-com.2010.0933
Cong JLiu BMajumdar RZhang Z(2010)Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011316:1(1-29)Online publication date: 1-Nov-2010
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Bsoul AWilton S(2010)An FPGA architecture supporting dynamically controlled power gating2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681533(1-8)Online publication date: Dec-2010
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Novel low-overhead operand isolation techniques for low-power datapath synthesis

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

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Level-Testability of Multi-operand Adders

Novel low-overhead operand isolation techniques for low-power datapath synthesis

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

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