article

Low-Energy Digit-Serial/Parallel Finite Field Multipliers

Authors:

Keshab K. ParhiAuthors Info & Claims

Journal of VLSI Signal Processing Systems, Volume 19, Issue 2

Pages 149 - 166

Published: 01 July 1998 Publication History

Abstract

Digit-serial architectures are best suited for systems requiring moderate sample rate and where area and power consumption are critical. This paper presents a new approach for designing digit-serial/parallel finite field multipliers. This approach combines both array-type and parallel multiplication algorithms, where the digit-level array-type algorithm minimizes the latency for one multiplication operation and the parallel architecture inside of each digit cell reduces both the cycle-time as well as the switching activities, hence power consumption. By appropriately constraining the feasible primitive polynomials, the mod p(x) operation involved in finite field multiplication can be performed in a more efficient way. As a result, the computation delay and energy consumption of one finite field multiplication using the proposed digit-serial/parallel architectures are significantly less than of those obtained by folding the parallel semi-systolic multipliers. Furthermore, their energy-delay products are reduced by a even larger percentage. Therefore, the proposed digit-serial/parallel architectures are attractive for both low-energy and high-performance applications.

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Cited By

Meher BMeher P(2019)Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension FieldsCircuits, Systems, and Signal Processing10.1007/s00034-018-0884-738:2(774-790)Online publication date: 1-Feb-2019
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Gebali FIbrahim A(2016)Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomialMicroprocessors & Microsystems10.1016/j.micpro.2015.11.01640:C(45-52)Online publication date: 1-Feb-2016
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Low-Energy Digit-Serial/Parallel Finite Field Multipliers

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Published In

cover image Journal of VLSI Signal Processing Systems

Journal of VLSI Signal Processing Systems Volume 19, Issue 2

Special issue on application specific systems, architectures and processors

July 1998

123 pages

ISSN:0922-5773

Editors:
S. Y. Kung
Princeton Univ., Princeton, NJ
,
Keshab K. Parhi
Univ. of Minnesota, Minneapolis
,
Valerie Taylor
Northwestern Univ., Evanston, IL

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Copyright © Copyright © 1998 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 July 1998

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Cited By

Meher BMeher P(2019)Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension FieldsCircuits, Systems, and Signal Processing10.1007/s00034-018-0884-738:2(774-790)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s00034-018-0884-7
Gebali FIbrahim A(2016)Low space-complexity and low power semi-systolic multiplier architectures over GF(2m) based on irreducible trinomialMicroprocessors & Microsystems10.1016/j.micpro.2015.11.01640:C(45-52)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1016/j.micpro.2015.11.016
Szu-Chi Chung Jing-Yu Wu Hsing-Ping Fu Jen-Wei Lee Hsie-Chia Chang Chen-Yi Lee (2015)Efficient Hardware Architecture of $\eta_{T}$ Pairing Accelerator Over Characteristic ThreeIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230348923:1(88-97)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2303489
Fan HHasan M(2015)A survey of some recent bit-parallel GF ( 2 n ) multipliersFinite Fields and Their Applications10.1016/j.ffa.2014.10.00832:C(5-43)Online publication date: 1-Mar-2015
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Uslu BErdem S(2015)Versatile digit serial multipliers for binary extension fieldsComputers and Electrical Engineering10.1016/j.compeleceng.2015.07.00646:C(29-45)Online publication date: 1-Aug-2015
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Nikooghadam MZakerolhosseini A(2013)Utilization of Pipeline Technique in AOP Based Multipliers with Parallel InputsJournal of Signal Processing Systems10.1007/s11265-012-0702-672:1(57-62)Online publication date: 1-Jul-2013
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Meher BMeher P(2013)An Efficient Look-up Table-based Approach for Multiplication over GF(2m) Generated by TrinomialsCircuits, Systems, and Signal Processing10.1007/s00034-013-9553-z32:6(2623-2638)Online publication date: 1-Dec-2013
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Lee CChiou C(2012)Scalable Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector RepresentationJournal of Signal Processing Systems10.1007/s11265-011-0654-269:2(197-211)Online publication date: 1-Nov-2012
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Zhou GLi LMichalik H(2012)Complexity analysis of finite field digit serial multipliers on FPGAsProceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications10.1007/978-3-642-28365-9_11(126-137)Online publication date: 19-Mar-2012
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