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Low-power design methodology and applications utilizing dual supply voltages

Authors:

Kimiyoshi Usami,

Mutsunori IgarashiAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 123 - 128

https://doi.org/10.1145/368434.368590

Published: 28 January 2000 Publication History

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Joshi SLi DOgrenci-Memik SDeptuch GHoff JJindariani SLiu TOlsen JTran N(2018)Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization AnalysisJournal of Low Power Electronics and Applications10.3390/jlpea80300258:3(25)Online publication date: 30-Jul-2018
https://doi.org/10.3390/jlpea8030025
Chen YWang YXie YTakach A(2012)Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizingJournal of Electrical and Computer Engineering10.1155/2012/1052502012(3-3)Online publication date: 1-Jan-2012
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Chen XWang YCao YMa YYang H(2012)Variation-aware supply voltage assignment for simultaneous power and aging optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216843320:11(2143-2147)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2168433
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Low-power design methodology and applications utilizing dual supply voltages
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ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2000

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Joshi SLi DOgrenci-Memik SDeptuch GHoff JJindariani SLiu TOlsen JTran N(2018)Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization AnalysisJournal of Low Power Electronics and Applications10.3390/jlpea80300258:3(25)Online publication date: 30-Jul-2018
https://doi.org/10.3390/jlpea8030025
Chen YWang YXie YTakach A(2012)Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizingJournal of Electrical and Computer Engineering10.1155/2012/1052502012(3-3)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/105250
Chen XWang YCao YMa YYang H(2012)Variation-aware supply voltage assignment for simultaneous power and aging optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216843320:11(2143-2147)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2168433
Chen YXie YWang YTakach ALin Y(2010)Parametric yield driven resource binding in behavioral synthesis with multi-V/V libraryProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899901(781-786)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899901
Soudris DPiguet C(2009)Circuits Techniques for Dynamic Power ReductionLow-Power CMOS Circuits10.1201/9781420036503.ch10(1-21)Online publication date: 9-Nov-2009
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Mukherjee RLiu SMemik SMondal S(2008)A high-level clustering algorithm targeting dual Vdd FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139196513:4(1-20)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391965
Billore ARajput CMishra D(2007)Low power design of variable centre frequency CMOS VCOInternational Journal of Electronics10.1080/0020721070179109394:12(1109-1119)Online publication date: Dec-2007
https://doi.org/10.1080/00207210701791093
Kulkarni SSrivastava ASylvester DBlaauw DChinnery DKeutzer K(2007)Power Optimization using Multiple Supply VoltagesClosing the Power Gap Between ASIC & Custom10.1007/978-0-387-68953-1_8(189-217)Online publication date: 2007
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Chinnery DKeutzer KChinnery DKeutzer K(2007)Overview of the Factors Affecting the Power ConsumptionClosing the Power Gap Between ASIC & Custom10.1007/978-0-387-68953-1_2(11-53)Online publication date: 2007
https://doi.org/10.1007/978-0-387-68953-1_2
Pangrle BJadcherla SChinnery DKeutzer K(2007)Verification For Multiple Supply Voltage DesignsClosing the Power Gap Between ASIC & Custom10.1007/978-0-387-68953-1_11(281-298)Online publication date: 2007
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Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages

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Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages

Low-power technology mapping for FPGA architectures with dual supply voltages

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