Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems
Authors: 
Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro MinamiAuthors Info & Claims
Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, Yoshiki Tsukiboshi, Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro MinamiAuthors Info & ClaimsPages 533 - 540
Abstract
This paper discusses design methodology for a module-wise dynamic voltage and frequency scaling(DVFS) technique which adjusts the supply voltage for a module appropriately to reduce the power dissipation. A circuit is able to work even when the supply voltage is in transition, by using our dynamic de-skewing system(DDS). We propose a novel clock design methodology to minimize the inter-module clock skew for solving one of the major design issues in the module-wise DVFS. We also describe a method of determining the minimum supply voltage value for a module. We lead the issue to a problem of solving simultaneous polynomial inequalities. Our experimental results show that the module-wise DVFS can reduce 53% power compared with the chip-wise DVFS, and 17% more reduction was achieved by applying the minimum supply voltage proposed.
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Index Terms
- Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems
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- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
- IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology
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Published: 24 January 2006
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