TWI473222B - Chip structure having imitation gold bumps - Google Patents

Chip structure having imitation gold bumps Download PDF

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Publication number
TWI473222B
TWI473222B TW98134686A TW98134686A TWI473222B TW I473222 B TWI473222 B TW I473222B TW 98134686 A TW98134686 A TW 98134686A TW 98134686 A TW98134686 A TW 98134686A TW I473222 B TWI473222 B TW I473222B
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layer
gold
bump
bumps
wafer structure
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TW98134686A
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TW201113995A (en
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Chih Wen Ho
Sun Hua Ko
Ming Kuo Wei
Po Chien Lee
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Chipbond Technology Corp
Gold Jet Technology Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

具有仿金凸塊之晶片結構Wafer structure with imitation gold bumps

本發明係有關於半導體裝置,特別係有關於一種具有仿金凸塊之晶片結構The present invention relates to a semiconductor device, and more particularly to a wafer structure having a gold-like bump

覆晶接合技術(flip-chip bonding technology)與內引腳接合技術(Inner Lead Bonding,ILB)是將晶片之主動面的銲墊上設置複數個導電凸塊(或稱為突出狀電極),藉由晶片翻轉或壓合內引腳方式以使凸塊能與一基板接合以完成電性連接。相較於使用打線連接(wire bond)之電性連接方式,提供了晶片至基板之較短電性連接路徑與適用於高密度輸出/入接點數量之產品製造,具有良好的高頻訊號的傳輸品質。Flip-chip bonding technology and Inner Lead Bonding (ILB) are used to place a plurality of conductive bumps (or protruding electrodes) on the pads of the active surface of the wafer. The wafer flips or presses the inner leads to allow the bumps to engage a substrate to complete the electrical connection. Compared with the electrical connection method using wire bond, it provides a short electrical connection path from the wafer to the substrate and a product suitable for high-density output/input point, with good high-frequency signal. Transmission quality.

目前較為常見的覆晶接合或內引腳接合技術是使用金凸塊(Au bump)的接合技術,金凸塊以熱壓合或是異方性導電膠電性連接至基板。雖然其可靠性較佳且不會有回焊成球狀的橋接短路問題,但由於材料成本過高,仍亟需發展同等級品質的替代凸塊。At present, the more common flip chip bonding or internal pin bonding technology is the bonding technique using Au bump, which is electrically connected to the substrate by thermocompression or anisotropic conductive paste. Although its reliability is better and there is no bridging short circuit problem of reflowing into a spherical shape, due to the high material cost, it is still necessary to develop a replacement bump of the same quality.

近來,有人提出一種低成本的銅凸塊來取代金塊,然而銅凸塊因其質地較硬相對使得延展性較差,故施加於銅凸塊的應力會直接傳遞到銅凸塊與晶片金屬墊的接合界面,導致銅凸塊的底部斷裂或是造成晶片受損。特別在多個凸塊無法控制相當準確的等高或是基板與晶片之間的覆晶間隙為非一致(例如基板翹曲變形時)的狀況時,銅凸塊的底部斷裂問題會變得更嚴重。此外,銅凸塊容易產生氧化問題,在製程中必須保持在還原氣氛,並在凸塊製成之後須另作防氧化的保護,製程限制頗多而無法有效降低凸塊的製造成本。Recently, a low-cost copper bump has been proposed to replace the gold bump. However, the copper bump has poor ductility due to its relatively hard texture, so the stress applied to the copper bump is directly transmitted to the copper bump and the wafer metal pad. Bonding the interface causes the bottom of the copper bump to break or damage the wafer. Especially when a plurality of bumps cannot control a fairly accurate contour or a situation in which the flip-chip gap between the substrate and the wafer is non-uniform (for example, when the substrate is warped), the problem of bottom cracking of the copper bump becomes more complicated. serious. In addition, the copper bumps are prone to oxidation problems, must be maintained in a reducing atmosphere during the process, and must be additionally protected against oxidation after the bumps are formed. There are many process limitations that cannot effectively reduce the manufacturing cost of the bumps.

為了解決上述之問題,本發明之主要目的係在於提供一種具有仿金凸塊之晶片結構,可避免在探測時因為抗潛變層被刺穿,導致凸塊外露引起的氧化問題,亦能避免壓合內引腳時直接壓觸而造成凸塊損壞。In order to solve the above problems, the main object of the present invention is to provide a wafer structure having a gold-like bump, which can avoid the oxidation problem caused by the exposure of the bump due to the piercing of the anti-submersible layer during detection, and can also avoid The bump is directly pressed when the inner pin is pressed and the bump is damaged.

本發明之次一目的係在於提供一種具有仿金凸塊之晶片結構,形成可取代金凸塊的仿金凸塊,更優於習知的銅凸塊,不會有銅凸塊的底部斷裂問題,能符合無鉛化、高可靠度與低成本之凸塊要求。A second object of the present invention is to provide a wafer structure having imitation gold bumps, forming a gold bump which can replace the gold bumps, which is superior to the conventional copper bumps, and has no bottom fracture problem of the copper bumps. It can meet the requirements of lead-free, high reliability and low cost bumps.

本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種具有仿金凸塊之晶片結構,主要包括一晶片、一凸塊下金屬層、複數個複合式金屬凸塊以及一抗潛變層。該晶片係具有複數個銲墊與一保護層,該保護層係覆蓋於該晶片之一表面上並形成有複數個開孔,以顯露該些銲墊。該凸塊下金屬層係設置於該些銲墊上,並覆蓋該保護層之該些開孔之周邊。該些複合式金屬凸塊每一複合式金屬凸塊係由一本體與一接合部相疊所構成而呈柱狀,該本體係對準該些銲墊並設置於該凸塊下金屬層上,該接合部係設置於該本體上,其中該本體係包含不小於99wt%的銀(Ag)含量,該接合部之材質係選自於金(Au),並且該接合部之厚度係小於該本體之厚度。該抗潛變層係形成於該接合部之一上表面與一第一外側邊以及該本體之一第二外側邊,以完全覆蓋該些複合式金屬凸塊。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a wafer structure with imitation gold bumps, which mainly comprises a wafer, a under bump metal layer, a plurality of composite metal bumps and an anti-dense layer. The wafer has a plurality of pads and a protective layer covering a surface of the wafer and forming a plurality of openings to expose the pads. The under bump metal layer is disposed on the pads and covers the periphery of the openings of the protective layer. Each of the composite metal bumps is formed by a stack of a body and a joint portion, and the system is aligned with the pads and disposed on the underlying metal layer of the bumps. The joint is disposed on the body, wherein the system comprises a silver (Ag) content of not less than 99% by weight, the material of the joint is selected from gold (Au), and the thickness of the joint is less than the The thickness of the body. The anti-situ layer is formed on an upper surface of the joint and a first outer side and a second outer side of the body to completely cover the composite metal bumps.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

在前述之具有仿金凸塊之晶片結構中,該接合部之該第一外側邊與該本體之該第二外側邊係可相互切齊,以構成一柱側壁。In the foregoing wafer structure having a gold-like bump, the first outer side of the joint and the second outer side of the body may be mutually aligned to form a pillar sidewall.

在前述之具有仿金凸塊之晶片結構中,該凸塊下金屬層係可具有不被該本體覆蓋之側緣,並且上述側緣係相對凹入於該第二外側邊。In the foregoing wafer structure having gold-like bumps, the under bump metal layer may have side edges not covered by the body, and the side edges are relatively recessed to the second outer side.

在前述之具有仿金凸塊之晶片結構中,該本體與該接合部之間係可形成有一接合面,該接合面係為非平坦。In the foregoing wafer structure having a gold-like bump, a joint surface may be formed between the body and the joint portion, and the joint surface is non-flat.

在前述之具有仿金凸塊之晶片結構中,該凸塊下金屬層係可具有一黏著層與一導電層,該黏著層係貼附於該銲墊,該導電層係貼附於該黏著層上。In the above wafer structure having a gold-like bump, the under-metal layer of the bump may have an adhesive layer and a conductive layer attached to the pad, and the conductive layer is attached to the adhesive layer. On the floor.

在前述之具有仿金凸塊之晶片結構中,該抗潛變層係可覆蓋至該導電層之側緣而顯露該黏著層之側緣。In the foregoing wafer structure having gold-like bumps, the anti-potential layer may cover the side edges of the conductive layer to expose the side edges of the adhesive layer.

在前述之具有仿金凸塊之晶片結構中,該抗潛變層之材質係可選自於金(Au)、鈀(Pd)、銅(Cu)與鎳(Ni)之其中一種。In the foregoing wafer structure having a gold-like bump, the material of the anti-dip layer may be selected from one of gold (Au), palladium (Pd), copper (Cu) and nickel (Ni).

在前述之具有仿金凸塊之晶片結構中,該抗潛變層係可選自於置換金與還原金之其中之一,使其具有抗氧化與高導電之特性。In the foregoing wafer structure having imitation gold bumps, the anti-potential layer may be selected from one of replacement gold and reduced gold to have oxidation resistance and high conductivity.

在前述之具有仿金凸塊之晶片結構中,該接合部之該上表面與該第一外側邊之間係可為有角度彎曲。In the foregoing wafer structure having a gold-like bump, the upper surface of the joint portion and the first outer side edge may be angularly curved.

在前述之具有仿金凸塊之晶片結構中,該本體之厚度係可介於6μm到20μm,該接合部之厚度係介於2μm到6μm,該抗潛變層之厚度係不超過1μm。In the foregoing wafer structure having gold-like bumps, the thickness of the body may be between 6 μm and 20 μm, the thickness of the joint portion is between 2 μm and 6 μm, and the thickness of the anti-steep layer is not more than 1 μm.

在前述之具有仿金凸塊之晶片結構中,該接合部之厚度係可大於該抗潛變層之厚度。In the foregoing wafer structure having a gold-like bump, the thickness of the joint portion may be greater than the thickness of the anti-stiction layer.

在前述之具有仿金凸塊之晶片結構中,該些複合式金屬凸塊之外形係可選自圓柱體、立方體以及長方體之其中之一。In the foregoing wafer structure having imitation gold bumps, the composite metal bump outer shape may be selected from one of a cylinder, a cube, and a rectangular parallelepiped.

由以上技術方案可以看出,本發明之具有仿金凸塊之晶片結構,有以下優點與功效:It can be seen from the above technical solutions that the wafer structure with the imitation gold bump of the present invention has the following advantages and effects:

一、可藉由本體、接合部與抗潛變層之特定組合關係作為其中一技術手段,由於每一複合式金屬凸塊係由本體與接合部相疊所構成,接合部係設置於本體上且接合部之厚度遠大於抗潛變層之厚度,可避免在探測時因為抗潛變層過薄而被探針刺穿,導致複合式金屬凸塊外露引起的氧化問題,亦能避免在內引腳壓合時直接壓觸至本體而造成複合式金屬凸塊損壞之情況。1. A specific combination of the body, the joint and the anti-situ layer can be used as one of the technical means. Since each composite metal bump is formed by stacking the body and the joint, the joint is disposed on the body. Moreover, the thickness of the joint portion is much larger than the thickness of the anti-potential layer, so that the probe can be prevented from being pierced by the probe because the anti-potential layer is too thin during the detection, and the oxidation problem caused by the exposure of the composite metal bump can also be avoided. When the pin is pressed, it directly touches the body and causes the composite metal bump to be damaged.

二、可藉由複合式金屬凸塊與抗潛變層之特定組合關係作為其中一技術手段,由於複合式金屬凸塊之本體包含不小於99wt%的銀含量,複合式金屬凸塊之接合部之材質係選自於金,形成可取代金凸塊的仿金凸塊,更優於習知的銅凸塊,不會有銅凸塊的底部斷裂問題,能符合無鉛化、高可靠度與低成本之凸塊要求。此外,利用包覆在複合式金屬凸塊表面的抗潛變層,亦能避免複合式金屬凸塊在應力作用下產生潛變的緩慢變形現象。Second, the specific combination relationship between the composite metal bump and the anti-dense layer can be used as one of the technical means. Since the body of the composite metal bump contains a silver content of not less than 99% by weight, the joint portion of the composite metal bump The material is selected from gold, forming a gold-like bump that can replace gold bumps. It is better than the conventional copper bumps. It does not have the problem of bottom cracking of copper bumps, and can meet lead-free, high reliability and low. The bump requirement for cost. In addition, the use of the anti-situ layer coated on the surface of the composite metal bump can also avoid the slow deformation phenomenon of the composite metal bump under the action of stress.

三、可藉由複合式金屬凸塊與抗潛變層之特定組合關係作為其中一技術手段,由於抗潛變層係為置換金(或還原金)並完全覆蓋複合式金屬凸塊,故抗潛變的處理時間短、形成厚度可控制在1μm以內,能避免複合式金屬凸塊之潛變發生,不會使複合式金屬凸塊的尺寸橫向變大,故在高溫下不會產生覆晶間隙變化,具有成本更低、厚度更薄之功效。Third, the specific combination relationship between the composite metal bump and the anti-situ layer can be used as one of the technical means. Since the anti-situ layer is a replacement gold (or reduced gold) and completely covers the composite metal bump, it is resistant. The processing time of the latent change is short, and the thickness can be controlled within 1 μm, which can avoid the occurrence of the latent change of the composite metal bump, and will not make the size of the composite metal bump laterally larger, so that no crystal chip will be generated at high temperature. The gap changes, with lower cost and thinner thickness.

四、可藉由複合式金屬凸塊內本體與接合部之間的非平坦接合面以及抗潛變層的完全覆蓋,以避免複合式金屬凸塊內接合部的分離或變形。Fourth, the non-flat joint surface between the inner metal body of the composite metal bump and the joint portion and the complete anti-latency layer can be completely covered to avoid separation or deformation of the joint portion in the composite metal bump.

以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

依據本發明之第一具體實施例,一種具有仿金凸塊之晶片結構100舉例說明於第1圖之局部截面示意圖與第2A至2G圖之製程中元件截面示意圖。本發明的具有仿金凸塊之晶片結構100係主要包括一晶片110、一凸塊下金屬層120、複數個複合式金屬凸塊130以及一抗潛變層140。該晶片110係具有複數個銲墊111與一保護層112,該保護層112係覆蓋於該晶片110之一表面113上並形成有複數個開孔114,以顯露該些銲墊111。該晶片110係為半導體材質,例如矽或是III-V族半導體,而前述的該表面113係可為該晶片110之主動面,可形成有積體電路元件,例如選自於微控制器、微處理器、記憶體、邏輯電路、特殊應用積體電路(例如顯示器驅動電路)等或上述的任意組合。該些銲墊111係由金屬製成,例如鋁、銅以及其合金等,可作為該晶片110訊號輸出入之端子。該保護層112係為電絕緣性的表面層,或稱其為鈍化層(passivation layer),材質可為聚亞醯胺、苯環丁烯(BCB)、磷矽玻璃(phosphosilicate glass)、氧化矽(silicon oxide)、氮化矽(silicon nitride)或氮化物(nitride),可藉由化學氣相沉積(CVD)技術所形成,能提供保護該表面113上之積體電路元件並使該表面113更為平坦。在本實施例中,該保護層112之該些開孔114係可局部覆蓋該些銲墊111之周緣,即該些開孔114之尺寸略小於該些銲墊111之尺寸。According to a first embodiment of the present invention, a wafer structure 100 having a gold-like bump is exemplified in a partial cross-sectional view of FIG. 1 and a cross-sectional view of an element in a process of FIGS. 2A to 2G. The wafer structure 100 with gold-like bumps of the present invention mainly comprises a wafer 110, an under bump metal layer 120, a plurality of composite metal bumps 130, and an anti-dense layer 140. The wafer 110 has a plurality of pads 111 and a protective layer 112. The protective layer 112 covers a surface 113 of the wafer 110 and is formed with a plurality of openings 114 to expose the pads 111. The wafer 110 is made of a semiconductor material, such as a germanium or a III-V semiconductor, and the surface 113 may be an active surface of the wafer 110. The integrated circuit component may be formed, for example, selected from a microcontroller. A microprocessor, a memory, a logic circuit, a special application integrated circuit (for example, a display driving circuit), or the like, or any combination thereof. The pads 111 are made of metal, such as aluminum, copper, and alloys thereof, and can be used as terminals for the signal input and output of the wafer 110. The protective layer 112 is an electrically insulating surface layer, or a passivation layer, and the material may be polyamidoamine, benzocyclobutene (BCB), phosphosilicate glass, or cerium oxide. Silicon oxide, silicon nitride or nitride, formed by chemical vapor deposition (CVD) techniques, can provide protection of the integrated circuit components on the surface 113 and cause the surface 113 More flat. In the present embodiment, the openings 114 of the protective layer 112 partially cover the periphery of the pads 111, that is, the openings 114 are slightly smaller in size than the pads 111.

請參閱第1圖所示,該凸塊下金屬層120係設置於該些銲墊111上,並覆蓋該保護層112之該些開孔114之周邊。該凸塊下金屬層120係為墊片狀,以供設置該些複合式金屬凸塊130,而該些銲墊111係與位置對應的該凸塊下金屬層120電性連接。具體而言,該凸塊下金屬層120係可具有一黏著層121與一導電層122,用以增進該些複合式金屬凸塊130與該些銲墊111之間的連結。更進一步地,該黏著層121係貼附於該銲墊111,可以提供該些銲墊111與該保護層112良好的黏著性並具有阻障作用,以防止金屬擴散。該黏著層121之材質可為鈦(Ti)或鎢化鈦(TiW)。該導電層122係貼附於該黏著層121上,該導電層122的導電性應高於該黏著層121並厚度可更薄,可作為形成該些複合式金屬凸塊130之電鍍種子層(容後詳述),並且該導電層122可提供對該些複合式金屬凸塊130之良好的沾附性,該導電層122之材質可為金(Au)。在本實施例中,該黏著層121與該導電層122係可以電鍍、濺鍍或化學氣相沉積方式形成。通常該凸塊下金屬層120係可略大於該保護層112之該些開孔114,以延伸至該保護層112之對應之開孔114的周緣。Referring to FIG. 1 , the under bump metal layer 120 is disposed on the pads 111 and covers the periphery of the openings 114 of the protective layer 112 . The under bump metal layer 120 is in the form of a spacer for providing the composite metal bumps 130, and the solder pads 111 are electrically connected to the under bump metal layer 120 corresponding to the position. In particular, the under bump metal layer 120 can have an adhesive layer 121 and a conductive layer 122 for enhancing the connection between the composite metal bumps 130 and the pads 111. Further, the adhesive layer 121 is attached to the solder pad 111, and the solder pads 111 can be provided with good adhesion to the protective layer 112 and have a barrier function to prevent metal diffusion. The material of the adhesive layer 121 may be titanium (Ti) or titanium tungsten (TiW). The conductive layer 122 is attached to the adhesive layer 121. The conductive layer 122 has a higher conductivity than the adhesive layer 121 and can be thinner, and can be used as a plating seed layer for forming the composite metal bumps 130 ( The conductive layer 122 can provide good adhesion to the composite metal bumps 130. The conductive layer 122 can be made of gold (Au). In this embodiment, the adhesive layer 121 and the conductive layer 122 can be formed by electroplating, sputtering or chemical vapor deposition. Generally, the under bump metal layer 120 may be slightly larger than the openings 114 of the protective layer 112 to extend to the periphery of the corresponding opening 114 of the protective layer 112.

請再參閱第1圖所示,每一複合式金屬凸塊130係由一本體131與一接合部132相疊所構成而呈柱狀,該本體131係對準該些銲墊111並設置於該凸塊下金屬層120上,該接合部132係設置於該本體131上,其中該本體131係包含不小於99wt%的銀(Ag)含量,該接合部132之材質係選自於金(Au),並且該接合部132之厚度係小於該本體131之厚度。在本實施例中,該接合部132之一第一外側邊134與該本體131之一第二外側邊135係可相互切齊,以構成一柱壁外側面,並且該接合部132之一上表面133與該第一外側邊134之間係可為有角度彎曲,例如約90度,用以界定該上表面133之面積進而有效控制凸塊接合區域,有利於非迴焊之導電接合。關於該些複合式金屬凸塊130的柱狀型態,該些複合式金屬凸塊130的高度可大於該些複合式金屬凸塊130的底部面積之一直徑或一寬度。其中,每一複合式金屬凸塊130之該本體131之厚度係可介於6μm到20μm,該接合部132之厚度係介於2μm到6μm。此外,由於該些複合式金屬凸塊130之本體131係包含不小於99wt%的銀含量,故具有極高的純度,適合以電鍍方式大量形成,並具有在電鍍製程中達到均質化之功效,不會有因成份散布不均的缺陷導致凸塊硬度的差異變化,又接合部132係具有金(Au)的特性與接合作用。因此,該些複合式金屬凸塊130係可猶如習知的金凸塊一般,具有與習知金凸塊相同但低於銅凸塊的硬度,並且導電性與金屬延伸性良好。並且,該些複合式金屬凸塊130之成本卻較低於習知的金凸塊之成本,並符合無鉛化之要求,能在不會影響凸塊的性能與品質下形成仿金凸塊,以取代習知的金凸塊,更優於習知的銅凸塊,不會有習知銅凸塊的底部斷裂問題。Referring to FIG. 1 again, each of the composite metal bumps 130 is formed by a stack of a body 131 and a joint portion 132. The body 131 is aligned with the pads 111 and disposed on the pillars 111. The joint portion 132 is disposed on the body 131, wherein the body 131 includes a silver (Ag) content of not less than 99% by weight, and the material of the joint portion 132 is selected from gold ( Au), and the thickness of the joint portion 132 is smaller than the thickness of the body 131. In this embodiment, one of the first outer side 134 of the joint portion 132 and the second outer side 135 of the body 131 are mutually aligned to form a cylindrical outer side surface, and the joint portion 132 An upper surface 133 and the first outer side 134 may be angled, for example, about 90 degrees, to define the area of the upper surface 133 to effectively control the bump joint area, which is beneficial for non-reflow conductive Engage. Regarding the columnar patterns of the composite metal bumps 130, the height of the composite metal bumps 130 may be greater than the diameter or a width of one of the bottom areas of the composite metal bumps 130. The thickness of the body 131 of each of the composite metal bumps 130 may be between 6 μm and 20 μm, and the thickness of the joint portion 132 is between 2 μm and 6 μm. In addition, since the body 131 of the composite metal bumps 130 contains a silver content of not less than 99% by weight, it has extremely high purity, is suitable for being formed in a large amount by electroplating, and has the effect of achieving homogenization in the electroplating process. There is no difference in the hardness of the bump due to the defect of uneven dispersion of the components, and the joint portion 132 has the characteristics of gold (Au) and the bonding effect. Therefore, the composite metal bumps 130 can be the same as the conventional gold bumps, have the same hardness as the conventional gold bumps but lower than the copper bumps, and have good electrical conductivity and metal elongation. Moreover, the cost of the composite metal bumps 130 is lower than the cost of the conventional gold bumps, and meets the requirements of lead-free, and can form imitation gold bumps without affecting the performance and quality of the bumps. In order to replace the conventional gold bumps, it is better than the conventional copper bumps, and there is no problem of the bottom crack of the conventional copper bumps.

請參閱第1圖所示,該抗潛變層140係形成於該接合部132之該上表面133與該第一外側邊134以及該本體131之該第二外側邊135,以完全覆蓋該些複合式金屬凸塊130。該抗潛變層140之主要作用在於避免該些複合式金屬凸塊130之本體131由該第二外側邊135產生銀的潛變現象。該抗潛變層140之厚度係不超過1μm,可約為0.03至0.3μm。如第4圖所示,由於該接合部132之厚度係可遠大於該抗潛變層140之厚度,故可以避免在探測(probing)時因為該抗潛變層140過薄而被探針30刺穿,導致該些複合式金屬凸塊130的銀成份外露所引起的氧化問題。在本實施例中,該抗潛變層140之材質係可選自於金(Au)、鈀(Pd)、銅(Cu)與鎳(Ni)之其中一種,可為純金屬或是合金,較佳地,該抗潛變層140係可選自於置換金(displacement Au)與還原金(reduced Au)之其中之一,使其具有抗氧化與高導電之特性,故抗潛變的處理時間短、形成厚度可控制在1μm(微米)以內(約數十到數百埃),便能避免該些複合式金屬凸塊130之潛變發生,並且不會使該些複合式金屬凸塊130的尺寸橫向變大,故在高溫下不會產生覆晶間隙變化,具有成本更低、厚度更薄之功效。特別是,該抗潛變層140之硬度係可不高於或接近該些複合式金屬凸塊130之硬度,而不需要有凸塊結構補強之作用,故該抗潛變層140的厚度增加與減少皆不會影響與改變整體凸塊的結構強度。因此,如第5圖所示,在內引腳接合製程中,壓合一內引腳40至該些複合式金屬凸塊130上時,由於該接合部132係具有一定厚度,在承受該內引腳40擠壓之後,該接合部132會稍微向左右兩側外擴,但不致使該內引腳40直接碰觸至該本體131,除了能免除該些複合式金屬凸塊130外露所引起的氧化問題,甚至發生該內引腳40過度擠壓而使得該抗潛變層140產生破損處時,由於該接合部132之材質係可選自於金,與該抗潛變層140具有相近之材質,亦可主動彌補該抗潛變層140之破損處,而不會影響整體的電性連接品質。Referring to FIG. 1 , the anti-situ layer 140 is formed on the upper surface 133 of the joint portion 132 and the first outer side 134 and the second outer side 135 of the body 131 to completely cover The composite metal bumps 130. The main function of the anti-situ layer 140 is to prevent the body 131 of the composite metal bumps 130 from generating a latent phenomenon of silver from the second outer side 135. The anti-steep layer 140 has a thickness of no more than 1 μm and may be about 0.03 to 0.3 μm. As shown in FIG. 4, since the thickness of the joint portion 132 can be much larger than the thickness of the anti-dive layer 140, it can be avoided that the probe 30 is too thin during probing because the anti-dive layer 140 is too thin. The piercing causes oxidation problems caused by the exposure of the silver component of the composite metal bumps 130. In this embodiment, the material of the anti-situ layer 140 may be selected from one of gold (Au), palladium (Pd), copper (Cu) and nickel (Ni), and may be a pure metal or an alloy. Preferably, the anti-situ layer 140 is selected from one of displacement Au and reduced Au, so that it has anti-oxidation and high-conductivity characteristics, so the anti-potential treatment The short time and the formation thickness can be controlled within 1 μm (micrometers) (about tens to hundreds of angstroms), the occurrence of the latent deformation of the composite metal bumps 130 can be avoided, and the composite metal bumps are not caused. The size of the 130 is increased laterally, so that no change in the flip-chip gap occurs at high temperatures, and the effect is lower and the thickness is thinner. In particular, the hardness of the anti-situ layer 140 may not be higher than or close to the hardness of the composite metal bumps 130, and does not require the reinforcement of the bump structure, so the thickness of the anti-dive layer 140 is increased. The reduction does not affect and change the structural strength of the overall bump. Therefore, as shown in FIG. 5, when the inner lead 40 is pressed onto the composite metal bumps 130 in the inner lead bonding process, since the joint portion 132 has a certain thickness, it is received therein. After the pin 40 is pressed, the joint portion 132 is slightly expanded to the left and right sides, but the inner lead 40 is not directly touched to the body 131, except that the composite metal bump 130 is exposed. Oxidation problem, even when the inner lead 40 is over-extruded to cause damage to the anti-situ layer 140, since the material of the joint portion 132 can be selected from gold, it is similar to the anti-dip layer 140. The material can also actively compensate for the damage of the anti-situ layer 140 without affecting the overall electrical connection quality.

一般而言,金屬材料在常溫下,受到彈性限度以下之應力長時間作用時,並不容易發生變化。但在高溫環境下,受到較低於彈性限度之應力作用時,金屬材料會隨著時間漸漸地產生變形,此一現象稱之為潛變(creep)。由於複合式金屬凸塊130的潛變現象會高於金凸塊與銅凸塊,故本發明必須利用在該些複合式金屬凸塊130表面之該抗潛變層140的薄膜包覆效果,特別是包覆該些複合式金屬凸塊130之本體131,避免該些複合式金屬凸塊130在長期應力作用下發生潛變而產生緩慢變形之現象,防止該些複合式金屬凸塊130往側向變胖的變形,以維持覆晶間隙並達到有效接合。In general, a metal material does not easily change when it is subjected to a stress below the elastic limit at a normal temperature for a long period of time. However, in a high temperature environment, when subjected to stress lower than the elastic limit, the metal material gradually deforms with time, and this phenomenon is called creep. Since the latent phenomenon of the composite metal bump 130 is higher than that of the gold bump and the copper bump, the present invention must utilize the film coating effect of the anti-situ layer 140 on the surface of the composite metal bump 130. In particular, the body 131 of the composite metal bumps 130 is covered to avoid the phenomenon that the composite metal bumps 130 undergo a latent deformation under long-term stress to cause slow deformation, and the composite metal bumps 130 are prevented from being deformed. The laterally fattening deformation maintains the flip-chip gap and achieves effective engagement.

請參閱第2A至2G圖所示,本發明進一步說明該具有仿金凸塊之晶片結構100之製造方法,以彰顯本案的功效。Referring to Figures 2A through 2G, the present invention further illustrates the method of fabricating the wafer structure 100 having gold-like bumps to demonstrate the efficacy of the present invention.

首先,如第2A圖所示,提供一晶片110,多個晶片110在該步驟中可構成於一晶圓,該晶片110係具有複數個銲墊111與一保護層112,該保護層112係覆蓋於該晶片110之一表面113上並具有複數個開孔114,以顯露該些銲墊111。First, as shown in FIG. 2A, a wafer 110 is provided. The plurality of wafers 110 can be formed in a wafer. The wafer 110 has a plurality of pads 111 and a protective layer 112. The protective layer 112 is provided. Covering one surface 113 of the wafer 110 and having a plurality of openings 114 to expose the pads 111.

接著,如第2B圖所示,包含上述之凸塊下金屬層120的金屬層係整面覆蓋於該晶片110之該保護層112上與該些銲墊111。該凸塊下金屬層120係可包含上述之黏著層121與導電層122,且可藉由已知半導體製程之沉積技術形成,例如濺鍍(sputtering)方式。在此步驟中,尚未界定面積尺寸之該凸塊下金屬層120係覆蓋整面的保護層112以及暴露出的銲墊111。Next, as shown in FIG. 2B, the metal layer including the under bump metal layer 120 covers the protective layer 112 of the wafer 110 and the pads 111. The under bump metal layer 120 may include the adhesion layer 121 and the conductive layer 122 described above, and may be formed by a deposition technique known in the semiconductor process, such as sputtering. In this step, the under bump metal layer 120, which has not yet defined the area size, covers the entire protective layer 112 and the exposed pads 111.

之後,如第2C圖所示,形成一圖案化遮罩,例如一光阻層10形成於該金屬層之外表面。一般而言,該光阻層10可選自液態光阻或乾膜光阻,接著進行一曝光顯影製程,形成複數個開孔11,以相對應地曝露出各銲墊111上方預定形成該凸塊下金屬層120之位置。該些開孔11係提供作為複合式金屬凸塊130與凸塊下金屬層120之形成區域。在本實施例中,該些開孔11係大於對應位置之該些銲墊111。或者,不受限地,該些開孔11亦可形成於該些銲墊111之外,並配合RDL(重配置線路層)製程中因接點配置設計上的需要而需變更接點的位置。Thereafter, as shown in FIG. 2C, a patterned mask is formed, for example, a photoresist layer 10 is formed on the outer surface of the metal layer. In general, the photoresist layer 10 can be selected from a liquid photoresist or a dry film photoresist, and then an exposure and development process is performed to form a plurality of openings 11 to correspondingly expose the pads 111 to form the protrusions. The position of the underlying metal layer 120. The openings 11 are provided as regions for forming the composite metal bumps 130 and the under bump metal layers 120. In the embodiment, the openings 11 are larger than the pads 111 of the corresponding positions. Alternatively, without limitation, the openings 11 may be formed outside the pads 111, and the position of the contacts needs to be changed in accordance with the design of the contact arrangement in the RDL (reconfiguration line layer) process. .

接著,如第2D圖所示,在該些開孔114內以電鍍(electroplating)方式形成上述之複數個本體131,該些本體131係接合於該凸塊下金屬層120上。接著,如第2E圖所示,可沿用同一光阻層10再形成複數個接合部132於該些本體131上,以構成複數個複合式金屬凸塊130,不會額外增加圖案化遮罩的設置成本。Next, as shown in FIG. 2D, the plurality of bodies 131 are formed by electroplating in the openings 114, and the bodies 131 are bonded to the under bump metal layer 120. Then, as shown in FIG. 2E, a plurality of bonding portions 132 may be formed on the body 131 along the same photoresist layer 10 to form a plurality of composite metal bumps 130 without additionally adding a patterned mask. Set the cost.

接著,如第2F圖所示,移除該光阻層10,以使得該金屬層中不包含該凸塊下金屬層120的部位為外露。接著,如第2G圖所示,可以蝕刻方式移除部分之該黏著層121與該導電層122,以形成該凸塊下金屬層120,其尺寸係可由該些複合式金屬凸塊130的底部覆蓋面積所界定。其中,每一複合式金屬凸塊130係形成該接合部132之一第一外側邊134與該本體131之一第二外側邊135,並且該第一外側邊134與該第二外側邊135係相互切齊。Next, as shown in FIG. 2F, the photoresist layer 10 is removed such that the portion of the metal layer that does not include the under bump metal layer 120 is exposed. Then, as shown in FIG. 2G, a portion of the adhesive layer 121 and the conductive layer 122 may be removed by etching to form the under bump metal layer 120, which may be sized by the bottom of the composite metal bumps 130. Coverage area is defined. Each of the composite metal bumps 130 forms a first outer side 134 of the joint portion 132 and a second outer side 135 of the body 131, and the first outer side 134 and the second outer side The side edges 135 are aligned with each other.

最後,再如第1圖所示,形成一抗潛變層140於該接合部132之一上表面133與該第一外側邊134以及該本體131之第二外側邊135。該抗潛變層140可藉由置換金、電鍍或化學鍍方法形成。利用該抗潛變層140包覆該些複合式金屬凸塊130,能避免該些複合式金屬凸塊130之本體131產生潛變現象。Finally, as shown in FIG. 1 , an anti-substance layer 140 is formed on one of the upper surface 133 of the joint portion 132 and the first outer side 134 and the second outer side 135 of the body 131 . The anti-situ layer 140 can be formed by replacement gold, electroplating or electroless plating. By coating the composite metal bumps 130 with the anti-situ layer 140, the body 131 of the composite metal bumps 130 can be prevented from generating a creep phenomenon.

具體而言,該些複合式金屬凸塊之外形係可選自圓柱體、立方體以及長方體之其中之一,但不受限制地,亦可為各種形狀之多角柱體。在本實施例中,如第3A圖所示,該些複合式金屬凸塊130之外形係為立方體,以使該上表面133為正方形,而每一複合式金屬凸塊130有四個柱體外側面,每一柱體外側面包含該接合部132之第一外側邊134與對應切齊之該本體131之第二外側邊135,並亦為正方形,可應用於矩陣排列或微間距排列之覆晶接合。在另一形狀變化例中,如第3B圖所示,複合式金屬凸塊130’之外形係為圓柱體,以使該上表面133’為圓形,而每一複合式金屬凸塊130’有一個圓弧狀柱體外側面,其係包含該接合部132’之外側邊與對應切齊之該本體131’之外側邊,可應用於矩陣排列或微間距排列之覆晶接合,並有助於底部填充膠之填充以防止填膠空隙的形成。在另一形狀變化例中,如第3C圖所示,該些複合式金屬凸塊130”之外形係為長方體,以使該上表面133”為矩形,而每一複合式金屬凸塊130”有四個柱體外側面,每一柱體外側面包含該接合部132”之外側邊與對應切齊之該本體131”之外側邊,並為兩兩對應的矩形或正方形,可應用於內引腳接合。Specifically, the composite metal bump outer shape may be selected from one of a cylinder, a cube, and a rectangular parallelepiped, but is not limited thereto, and may be a polygonal cylinder of various shapes. In this embodiment, as shown in FIG. 3A, the composite metal bumps 130 are formed in a cubic shape so that the upper surface 133 is square, and each composite metal bump 130 has four columns outside the body. The side surface of each column includes a first outer side 134 of the joint portion 132 and a second outer side 135 of the body 131 correspondingly aligned, and is also square, and can be applied to a matrix arrangement or a fine pitch arrangement. Flip chip bonding. In another shape variation, as shown in FIG. 3B, the composite metal bump 130' is shaped like a cylinder so that the upper surface 133' is circular, and each composite metal bump 130' The outer surface of the outer surface of the arc-shaped column includes the outer side of the joint portion 132' and the outer side of the body 131' which is correspondingly aligned, and can be applied to the flip chip bonding of the matrix arrangement or the fine pitch arrangement, and It helps to fill the underfill to prevent the formation of voids. In another shape change example, as shown in FIG. 3C, the composite metal bumps 130" are formed in a rectangular parallelepiped shape such that the upper surface 133" is rectangular, and each composite metal bump 130" There are four outer side faces of the column, and the outer side of each column includes the outer side of the engaging portion 132" and the side of the body 131" which is correspondingly aligned, and is a rectangular or square corresponding to each other, and can be applied inside. Pin bonding.

依據本發明之第二具體實施例,另一種仿金凸塊之晶片結構200舉例說明於第6圖之截面示意圖。該仿金凸塊之晶片結構200主要包括一晶片110、一凸塊下金屬層120、複數個複合式金屬凸塊130以及一抗潛變層140。其中與第一實施例相同的主要元件將以相同符號標示,並不再詳予贅述。In accordance with a second embodiment of the present invention, another wafer structure 200 of gold-like bumps is illustrated in cross-section in FIG. The imitation gold bump wafer structure 200 mainly includes a wafer 110, a bump under metal layer 120, a plurality of composite metal bumps 130, and an anti-dense layer 140. The same elements as those in the first embodiment will be designated by the same reference numerals and will not be described in detail.

在本實施例中,該凸塊下金屬層120係可具有不被該本體131覆蓋之側緣123,並且上述側緣123係相對凹入於該第二外側邊135,而該抗潛變層140係局部覆蓋至該凸塊下金屬層120。詳細而言,該抗潛變層140係可覆蓋至該導電層122之側緣,但顯露該黏著層121之側緣。因此,不會使得該抗潛變層140接觸至該晶片110之該保護層112,以達成凸塊高密度排列,並能增加晶片與基板間的結合力,進而提升高頻訊號的傳輸品質。更進一步地,由於該抗潛變層140未接觸至該晶片110之該保護層112,故能產生一緩衝空間,以控制該抗潛變層140完整覆蓋該複合式金屬凸塊130之表面卻不會延伸到該保護層112,以減少凸塊間短路的問題,並可以預防該複合式金屬凸塊130因變形擠壓至該晶片110而從該複合式金屬凸塊130底部斷開,影響了整體電性連接效果。此外,再如第6圖所示,由於每一複合式金屬凸塊130是以電鍍(electroplating)方式形成,該本體131與該接合部132之間係形成有一接合面250,該接合面250係為非平坦。因此,可藉由該非平坦接合面251以及該抗潛變層140的完全覆蓋,以避免該些複合式金屬凸塊130內接合部132的分離或變形。詳細而言,該本體131隨著該凸塊下金屬層120之凹陷處而形成非平坦之該接合面250,並且該接合面250之凹陷深度係略為該凸塊下金屬層120之凹陷深度的二分之一。In this embodiment, the under bump metal layer 120 may have a side edge 123 not covered by the body 131, and the side edge 123 is relatively recessed to the second outer side 135, and the anti-potential Layer 140 is partially covered to the under bump metal layer 120. In detail, the anti-situ layer 140 may cover the side edges of the conductive layer 122 but expose the side edges of the adhesive layer 121. Therefore, the anti-dip layer 140 is not brought into contact with the protective layer 112 of the wafer 110 to achieve high-density arrangement of the bumps, and the bonding force between the wafer and the substrate can be increased, thereby improving the transmission quality of the high-frequency signal. Further, since the anti-dive layer 140 does not contact the protective layer 112 of the wafer 110, a buffer space can be generated to control the anti-dive layer 140 to completely cover the surface of the composite metal bump 130. The protective layer 112 is not extended to reduce the problem of short circuit between the bumps, and the composite metal bump 130 can be prevented from being broken from the bottom of the composite metal bump 130 by deformation to the wafer 110, affecting The overall electrical connection effect. In addition, as shown in FIG. 6 , since each composite metal bump 130 is formed by electroplating, a joint surface 250 is formed between the body 131 and the joint portion 132 , and the joint surface 250 is formed. It is not flat. Therefore, the separation or deformation of the joint portion 132 in the composite metal bumps 130 can be avoided by the non-flat joint surface 251 and the complete coverage of the anti-dive layer 140. In detail, the body 131 forms a non-flat interface surface 250 along with the recess of the under bump metal layer 120, and the recess depth of the joint surface 250 is slightly the recess depth of the under bump metal layer 120. Half.

總而言之,本發明之具有仿金凸塊之晶片結構利用抗潛變層包覆複合式金屬凸塊,能避免複合式金屬凸塊之潛變發生,故在高溫下不會產生覆晶間隙變化的問題,可符合無鉛化、高可靠度與低成本之凸塊要求。因此,複合式金屬凸塊可具體應用於半導體晶片上的柱狀凸塊。更由於抗潛變層不會接觸至保護層,可達成凸塊高密度排列,以增加晶片與基板間的結合力,進而提升高頻訊號的傳輸品質。In summary, the wafer structure with the imitation gold bump of the present invention utilizes the anti-dip layer to coat the composite metal bump, which can avoid the occurrence of the latent change of the composite metal bump, so that no change in the flip-chip gap occurs at high temperature. The problem can meet the requirements of lead-free, high reliability and low cost bumps. Therefore, the composite metal bumps can be specifically applied to the columnar bumps on the semiconductor wafer. Moreover, since the anti-dense layer does not contact the protective layer, a high-density arrangement of the bumps can be achieved to increase the bonding force between the wafer and the substrate, thereby improving the transmission quality of the high-frequency signal.

以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

10...光阻層10. . . Photoresist layer

11...開孔11. . . Opening

20...基板20. . . Substrate

21...表面twenty one. . . surface

22...連接墊twenty two. . . Connection pad

30...探針30. . . Probe

40...內引腳40. . . Inner pin

100...具有仿金凸塊之晶片結構100. . . Wafer structure with imitation gold bumps

110...晶片110. . . Wafer

111...銲墊111. . . Solder pad

112...保護層112. . . The protective layer

113...表面113. . . surface

114...開孔114. . . Opening

120...凸塊下金屬層120. . . Under bump metal layer

121...黏著層121. . . Adhesive layer

122...導電層122. . . Conductive layer

123...側緣123. . . Side edge

130...複合式金屬凸塊130. . . Composite metal bump

131...本體131. . . Ontology

132...接合部132. . . Joint

133...上表面133. . . Upper surface

134...第一外側邊134. . . First outer side

135...第二外側邊135. . . Second outer side

130’...複合式金屬凸塊130’. . . Composite metal bump

131’...本體131’. . . Ontology

132’...接合部132’. . . Joint

133’...上表面133’. . . Upper surface

130”...複合式金屬凸塊130"...composite metal bumps

131”...本體131"... body

132”...接合部132"...joining

133”...上表面133"... upper surface

140...抗潛變層140. . . Anti-substitute layer

200...具有仿金凸塊之晶片結構200. . . Wafer structure with imitation gold bumps

250...接合面250. . . Joint surface

第1圖:依據本發明之第一具體實施例的一種具有仿金凸塊之晶片結構之局部截面示意圖。Figure 1 is a partial cross-sectional view showing a wafer structure having gold-like bumps in accordance with a first embodiment of the present invention.

第2A至2G圖:依據本發明之第一具體實施例的具有仿金凸塊之晶片結構在製程中元件的截面示意圖。2A to 2G are views showing a cross-sectional view of an element in a process of a wafer structure having a gold-like bump according to a first embodiment of the present invention.

第3A至3C圖:依據本發明之第一具體實施例的具有仿金凸塊之晶片結構中不同形狀複合式金屬凸塊的變化例之立體示意圖。3A to 3C are perspective views showing variations of different shapes of composite metal bumps in a wafer structure having gold-like bumps according to the first embodiment of the present invention.

第4圖:依據本發明之第一具體實施例的具有仿金凸塊之晶片結構繪示其在探測時被探針刺穿之截面示意圖。Fig. 4 is a cross-sectional view showing a wafer structure having a gold-like bump according to a first embodiment of the present invention, which is pierced by a probe at the time of detection.

第5圖:依據本發明之第一具體實施例的具有仿金凸塊之晶片結構繪示其在接合引腳時之截面示意圖。Fig. 5 is a cross-sectional view showing a wafer structure having a gold-like bump according to a first embodiment of the present invention when it is bonded to a lead.

第6圖:依據本發明之第二具體實施例的另一種具有仿金凸塊之晶片結構之局部截面示意圖。Figure 6 is a partial cross-sectional view showing another wafer structure having gold-like bumps in accordance with a second embodiment of the present invention.

100...具有仿金凸塊之晶片結構100. . . Wafer structure with imitation gold bumps

110...晶片110. . . Wafer

111...銲墊111. . . Solder pad

112...保護層112. . . The protective layer

113...表面113. . . surface

114...開孔114. . . Opening

120...凸塊下金屬層120. . . Under bump metal layer

121...黏著層121. . . Adhesive layer

122...導電層122. . . Conductive layer

123...側緣123. . . Side edge

130...複合式金屬凸塊130. . . Composite metal bump

151...本體151. . . Ontology

132...接合部132. . . Joint

133...上表面133. . . Upper surface

134...第一外側邊134. . . First outer side

135...第二外側邊135. . . Second outer side

140...抗潛變層140. . . Anti-substitute layer

Claims (12)

一種具有仿金凸塊之晶片結構,包括:一晶片,係具有複數個銲墊與一保護層,該保護層係覆蓋於該晶片之一表面上並形成有複數個開孔,以顯露該些銲墊;一凸塊下金屬層,係設置於該些銲墊上,並覆蓋該保護層之該些開孔之周邊;複數個複合式金屬凸塊,每一複合式金屬凸塊係由一本體與一接合部相疊所構成而呈柱狀,該本體係對準該些銲墊並設置於該凸塊下金屬層上,該接合部係設置於該本體上,其中該本體係包含不小於99wt%的銀(Ag)含量,該接合部之材質係選自於金(Au),並且該接合部之厚度係小於該本體之厚度;以及一抗潛變層,係形成於該接合部之一上表面與一第一外側邊以及該本體之一第二外側邊,以完全覆蓋該些複合式金屬凸塊,其中該些複合式金屬凸塊的本體之潛變(creep)高於該抗潛變層的潛變。 A wafer structure having a gold-like bump comprises: a wafer having a plurality of pads and a protective layer covering the surface of one of the wafers and forming a plurality of openings to expose the plurality of openings a solder pad; a bump under metal layer disposed on the pads and covering the periphery of the openings of the protective layer; a plurality of composite metal bumps, each composite metal bump being composed of a body Formed in a columnar shape with a joint portion, the system is aligned with the solder pads and disposed on the underlying metal layer of the bump, the joint portion is disposed on the body, wherein the system comprises not less than 99 wt% of silver (Ag) content, the material of the joint is selected from gold (Au), and the thickness of the joint is less than the thickness of the body; and an anti-dense layer is formed at the joint An upper surface and a first outer side and a second outer side of the body to completely cover the composite metal bumps, wherein the bulk of the composite metal bumps has a higher creep The latent change of the anti-potential layer. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該接合部之該第一外側邊與該本體之該第二外側邊係相互切齊,以構成一柱側壁。 A wafer structure having a gold-like bump according to claim 1, wherein the first outer side of the joint and the second outer side of the body are flush with each other to form a pillar side wall. 根據申請專利範圍第2項之具有仿金凸塊之晶片結構,其中該凸塊下金屬層係具有不被該本體覆蓋之側緣,並且上述側緣係相對凹入於該第二外側邊。 A wafer structure having a gold-like bump according to claim 2, wherein the under bump metal layer has a side edge not covered by the body, and the side edge is relatively recessed to the second outer side . 根據申請專利範圍第3項之具有仿金凸塊之晶片結構,其中該本體與該接合部之間係形成有一接合面,該接合面係為非平坦。 A wafer structure having a gold-like bump according to claim 3, wherein a joint surface is formed between the body and the joint portion, and the joint surface is non-flat. 根據申請專利範圍第3項之具有仿金凸塊之晶片結構,其中該凸塊下金屬層係具有一黏著層與一導電層,該黏著層係貼附於該銲墊,該導電層係貼附於該黏著層上。 The wafer structure having a gold-like bump according to claim 3, wherein the under bump metal layer has an adhesive layer and a conductive layer, the adhesive layer is attached to the solder pad, and the conductive layer is attached Attached to the adhesive layer. 根據申請專利範圍第5項之具有仿金凸塊之晶片結構,其中該抗潛變層係覆蓋至該導電層之側緣而顯露該黏著層之側緣。 A wafer structure having a gold-like bump according to claim 5, wherein the anti-potential layer covers a side edge of the conductive layer to expose a side edge of the adhesive layer. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該抗潛變層之材質係選自於金(Au)、鈀(Pd)、銅(Cu)與鎳(Ni)之其中一種。 A wafer structure having a gold-like bump according to the first aspect of the patent application, wherein the material of the anti-situ layer is selected from the group consisting of gold (Au), palladium (Pd), copper (Cu) and nickel (Ni). One. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該抗潛變層係選自於置換金與還原金之其中之一,使其具有抗氧化與高導電之特性。 A wafer structure having a gold-like bump according to the first aspect of the patent application, wherein the anti-potential layer is selected from one of a replacement gold and a reduced gold to have oxidation resistance and high conductivity. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該接合部之該上表面與該第一外側邊之間係為有角度彎曲。 A wafer structure having a gold-like bump according to claim 1, wherein the upper surface of the joint portion and the first outer side edge are angularly curved. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該本體之厚度係介於6μm到20μm,該接合部之厚度係介於2μm到6μm,該抗潛變層之厚度係不超過1μm。 The wafer structure having a gold-like bump according to the first aspect of the patent application, wherein the thickness of the body is between 6 μm and 20 μm, and the thickness of the joint portion is between 2 μm and 6 μm, and the thickness of the anti-situ layer is not More than 1μm. 根據申請專利範圍第1項之具有仿金凸塊之晶片結 構,其中該接合部之厚度係大於該抗潛變層之厚度。 Wafer junction with gold bumps according to item 1 of the patent application scope The thickness of the joint is greater than the thickness of the anti-situ layer. 根據申請專利範圍第1項之具有仿金凸塊之晶片結構,其中該些複合式金屬凸塊之外形係選自圓柱體、立方體以及長方體之其中之一。The wafer structure having imitation gold bumps according to claim 1, wherein the composite metal bumps are selected from one of a cylinder, a cube, and a rectangular parallelepiped.
TW98134686A 2009-10-13 2009-10-13 Chip structure having imitation gold bumps TWI473222B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW468246B (en) * 2000-11-21 2001-12-11 Wha Yu Ind Co Ltd Metal bump structure on I/O contact of substrate or chip and its fabrication method
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
TWM352128U (en) * 2008-10-08 2009-03-01 Int Semiconductor Tech Ltd Semiconductor structure having silver bump

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW468246B (en) * 2000-11-21 2001-12-11 Wha Yu Ind Co Ltd Metal bump structure on I/O contact of substrate or chip and its fabrication method
US20040166661A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation Method for forming copper bump antioxidation surface
TWM352128U (en) * 2008-10-08 2009-03-01 Int Semiconductor Tech Ltd Semiconductor structure having silver bump

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