KR100618705B1 - Method for forming gate of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a gate of a semiconductor device capable of improving the refresh characteristics of the device. Disclosed is a semiconductor device having a device isolation film; Forming a hard mask film for forming a channel region on a substrate product including the device isolation film; Recessing the hard mask layer and the substrate to expose the channel region of the substrate; Forming an oxide film on the substrate resultant; Forming spacers on both side walls of the substrate by etching the oxide film and the substrate in the remaining portions except for the side walls of the substrate to a predetermined depth; Performing wet etching on the spacers and the hard mask layer to form a stepped substrate; Forming a gate oxide layer on the substrate resultant; Sequentially forming a doped polysilicon film, a tungsten silicide film, and a gate hard mask film on the gate oxide film; And etching the gate hard mask layer, the tungsten silicide layer, and the doped polysilicon layer.

Description

METHOOD FOR FORMING GATE OF SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating processes for forming a gate of a semiconductor device having a recess channel according to the related art.

2A through 2D are cross-sectional views illustrating processes for forming a gate of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 semiconductor substrate 12 device isolation film

13: hard mask film 14: oxide film

15 gate oxide film 16 polysilicon film

17 tungsten silicide film 18 gate hard mask film

The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of improving the refresh characteristics of the device.                         

Recently, as the size of the DRAM device is reduced, the channel length of the cell transistor is also greatly reduced. In addition, as the channel length is reduced, the short channel effect is increased, thereby increasing the ion implantation concentration of the channel. Therefore, when the ion implantation concentration of the channel increases, the concentration of the junction portion corresponding to the source or drain region of the transistor is increased, thereby increasing the intensity of the electric field applied to the junction region. As the electric field strength increases, the leakage current of the junction making contact with the capacitor increases, and the leakage current causes loss of electric charge stored in the capacitor, thereby degrading the refresh characteristics of the device. Therefore, in order to solve this problem, the idea of the implementation of the device having a recess channel (recess channel) that can ensure the effective channel length (effective channel length) and the actual process development research is being actively conducted.

1A to 1E are cross-sectional views illustrating processes for forming a gate of a semiconductor device having a recess channel according to the related art.

As shown in FIG. 1A, a first hard mask layer 3 is formed on the semiconductor substrate 1 on which the device isolation layer 2 is formed, and then a photoresist pattern (not shown) is formed on the first hard mask layer. Form.

As shown in FIG. 1B, using the photoresist pattern as an etching mask, the active region of the substrate 1 adjacent to the first hard mask layer 3 and the isolation layer 2 is recessed to form an active region having a step difference. Form.

As shown in FIG. 1C, after removing the first hard mask layer 3 remaining on the substrate, impurity ion implantation is performed in the substrate to form a well region (not shown), and then the threshold voltage of the transistor is adjusted. To do this, impurity ion implantation is performed. A gate oxide film 4 is then formed on the substrate product.

As shown in FIG. 1D, a doped polysilicon film 5, a tungsten silicide film 6, and a second hard mask film 7 are sequentially formed on the substrate product including the gate oxide film 4.

As shown in FIG. 1E, the second hard mask layer 7, the tungsten silicide layer 6, and the doped polysilicon layer 5 are sequentially etched to form a gate 8 in the stepped active region. .

However, as described above, in the case of a device having a recess channel, an effective effect of increasing the effective channel length is relatively small, so that the channel ion implantation concentration for adjusting the threshold voltage of the device should be relatively high. Therefore, the effect of reducing the electric field at the junction portion of the source / drain regions is also relatively small, and there is a problem that the improvement of the refresh characteristics of the device is limited.

Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of improving the refresh characteristics of the device, which has been devised to solve the conventional problems as described above.

In order to achieve the above object, the present invention provides a semiconductor substrate having a device isolation film; Forming a hard mask film for forming a channel region on a substrate product including the device isolation film; Recessing the hard mask layer and the substrate to expose the channel region of the substrate; Forming an oxide film on the substrate resultant; Forming spacers on both side walls of the substrate by etching the oxide film and the substrate in the remaining portions except for the side walls of the substrate to a predetermined depth; Performing wet etching on the spacers and the hard mask layer to form a stepped substrate; Forming a gate oxide layer on the substrate resultant; Sequentially forming a doped polysilicon film, a tungsten silicide film, and a gate hard mask film on the gate oxide film; And etching the gate hard mask layer, the tungsten silicide layer, and the doped polysilicon layer.

Here, the step of recessing the hard mask film and the substrate recesses the substrate to a depth of 400 GPa or less.

The step of forming the oxide film is formed by the CVD method.

The oxide film is formed to a thickness of 500 kPa or less.

The etching of the oxide film and the substrate of the remaining portions except for the sidewalls of the substrate to a predetermined depth to form spacers on both sidewalls of the substrate recesses the substrate to a depth of 400 mm or less.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

2A through 2D are cross-sectional views illustrating processes of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a semiconductor substrate 11 having an isolation layer 12 is provided. Subsequently, the hard mask layer 13 and the substrate are recessed to expose the channel region of the substrate after the hard mask layer 13 for forming the channel region is formed on the substrate resultant including the device isolation layer 12. . At this time, the hard mask film 13 and the substrate 11 are recessed to a depth of 400 kPa or less.

As shown in FIG. 2B, an oxide layer 14 is formed on the hard mask layer 13, the isolation layer 12, and the exposed substrate 11. In this case, the oxide film 14 is formed to a thickness of 500 kPa or less by the CVD method.

As shown in FIG. 2C, spacers 14a are formed on both sidewalls of the substrate by etching the oxide layer 14 and the substrate in the remaining portions except the sidewalls of the substrate to a predetermined depth. At this time, the substrate is recessed to a depth of 400 kPa or less. Thereafter, wet etching is performed on the spacer 14a and the hard mask layer 13 to form a stepped substrate.

As shown in FIG. 2D, a gate oxide film 15 is formed on the substrate resultant. Next, the doped polysilicon layer 16, the tungsten silicide layer 17, and the gate hard mask layer 18 are sequentially formed on the substrate including the gate oxide layer.

Next, the gate hard mask layer 18, the tungsten silicide layer 17, and the doped polysilicon layer 16 are etched to form a gate 19.                     

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

As described above, the present invention can increase the effective channel length relatively, unlike the existing process by forming a gate having a stepped recess channel. As a result, the short channel effect can be prevented, thereby reducing the impurity ion implantation concentration for adjusting the threshold voltage of the channel. Therefore, the electric field can be relaxed at the junction portion of the source / drain region, thereby improving the refresh characteristics of the device.

Claims (5)

Providing a semiconductor substrate having a device isolation film; Forming a hard mask film for forming a channel region on a substrate product including the device isolation film; Recessing the hard mask layer and the substrate to expose the channel region of the substrate; Forming an oxide film on the substrate resultant; Forming spacers on both side walls of the substrate by etching the oxide film and the substrate in the remaining portions except for the side walls of the substrate to a predetermined depth; Performing wet etching on the spacers and the hard mask layer to form a stepped substrate; Forming a gate oxide layer on the substrate resultant; Sequentially forming a doped polysilicon film, a tungsten silicide film, and a gate hard mask film on the gate oxide film; And And etching the gate hard mask layer, the tungsten silicide layer, and the doped polysilicon layer. The method of claim 1, wherein the recessing of the hard mask layer and the substrate is performed by recessing the substrate to a depth of 400 μm or less. The method of claim 1, wherein the forming of the oxide film is performed by a CVD method. The method of claim 1, wherein the oxide film is formed to a thickness of 500 kPa or less. The method of claim 1, wherein the forming of the spacers on both sidewalls of the substrate by etching the oxide film and the substrate in the remaining portions except for the sidewalls of the substrate to a predetermined depth comprises recessing the substrate to a depth of 400 μm or less. Method of forming a gate of a semiconductor device.

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