JPH05343416A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a separation region and a collector lead out region by separating a separation diffusion region and the collector lead out region with an oxide film. CONSTITUTION:An about 5000Angstrom thick SiO2 film 8 is laminated on an epitaxial silicon layer 3 which includes trenches 7a and 7b based on a CVD process. The SiO2 film 8 (oxide film) deposited on the bottoms of the trenches 7a and 7b are etched and removed by anisotropic etching so that only the SiO2 film 8, which covers the internal sides of the trenches 7a and 7b, may remain. The heat treatment of the film crystallizes only amorphous silicon 10, which comes into contact with a silicon board 1, in the form of a single crystal and at the same time diffuses the impurities implanted into the bottoms of the trenches 7a and 7b which serve as a separation diffusion region 6 and a collector lead out region 5. This construction makes it possible to form a device separation region whose area is extremely small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an active region of an integrated circuit such as a bipolar LSI is separated and a collector lead region is formed.

[0002]

2. Description of the Related Art A case of forming an NPN transistor in a conventional bipolar integrated circuit will be described with reference to FIG. First, after forming the N ⁺ buried layer 22 on the P-type silicon substrate 21,
Epitaxial growth is performed on the entire surface of the silicon substrate 21, and N
The type silicon layer 23 is laminated (FIG. 3A).

Next, an oxide film 24 is formed on the silicon substrate 21.
Then, the oxide film 24 is patterned into a desired shape, P ⁺ impurities are ion-implanted using the oxide film 24 as a mask, and a high temperature heat treatment is performed to form a P ⁺ region 26 reaching the silicon substrate 21. (FIG. 3 (b)).
Further, after the oxide film 24 is formed again on the silicon substrate 21, the oxide film 24 is patterned into a desired shape, N ⁺ impurities are ion-implanted using the oxide film 24 as a mask, and a high temperature heat treatment is performed. An N ⁺ region 25 extending to the N ⁺ buried layer 22 formed on the silicon substrate 21 is formed (FIG. 3C).

Then, a P ⁺ impurity is ion-implanted by a method similar to the method of forming the N ⁺ buried layer 22 in the P type silicon substrate 21 to form a base region 28. further,
In the same manner, N ⁺ impurity ions are implanted to form the emitter region 29. Then, after forming the oxide film 27 on the silicon substrate 21, contact holes are formed on the emitter, collector, and base regions of the oxide film 27, and the electrodes 30, 31, and 32 are formed (FIG. 3D). ).

In this way, each element formed on the silicon substrate 21 is separated by utilizing the P ⁺ region 26 formed in the silicon layer 23 laminated on the silicon substrate 21, and at the same time the silicon layer 23 is formed. N ⁺ region 25 formed
Is used as the collector drawing area. In the method of manufacturing a semiconductor device described above, since the P ⁺ isolation region 26 and the N ⁺ collector lead-out region 25 formed in the silicon layer 23 must be deep diffusion regions, they are diffused laterally during the formation process. Therefore, the occupied area becomes large. In addition, including the expansion of the depletion layer at the time of voltage application, it is difficult to reduce the cell size of this transistor.

Further, in order to diffuse the P ⁺ isolation region 26 and the N ⁺ collector extraction region 25, a heat treatment is performed at a high temperature for a long time. In this process, the N ⁺ buried region 22 is upwardly diffused into the silicon layer 23. However, there is a problem in that the thickness of the effective epitaxial silicon layer 23 is reduced and the thickness of the effective epitaxial silicon layer 23 is reduced. On the other hand, as shown in FIG. 4, by forming a trench in the isolation region 44 of the P-type silicon substrate 41 in which the N-type epitaxial layer 42 is formed and burying SiO ₂ 43 in the trench, Although a method of separating the bipolar LSI has been proposed, there is a problem that this method can be applied only to the separation region 44.

Further, there is a problem that the substrate potential cannot be obtained from the surface of the silicon substrate 41 and the manufacturing process is complicated, so that the stability in the process is insufficient. The present invention has been made in view of such a problem, and provides a method for manufacturing a semiconductor device, which can reduce the separation region and the collector extraction region and suppress the reduction in the thickness of the effective epitaxial silicon layer. It is an object.

[0008]

In order to solve the above-mentioned problems, according to the present invention, (i) on a second conductivity type silicon substrate in which a high concentration first conductivity type region is formed as a buried diffusion region. A low-concentration first-conductivity-type silicon layer is laminated on the entire surface, an oxide film is formed on the entire surface of the silicon layer, and then, on the silicon layer in a region where a collector extraction region is formed,
At the same time as forming the trench reaching the buried diffusion region,
Forming a trench reaching the silicon substrate in the silicon layer in the region where the isolation diffusion region is to be formed; (ii) covering only the side surface in the trench with an oxide film; (iii) a trench serving as the isolation diffusion region Injecting a second conductivity type impurity into the bottom and injecting the first conductivity type impurity into the bottom of the trench to be the collector extraction region, (iv) depositing amorphous silicon on the entire surface of the silicon layer including the trench, and performing heat treatment And a step of (v) selectively removing the amorphous silicon on the silicon layer.

In the present invention, the high-concentration first conductivity type region formed on the second conductivity type silicon substrate is formed as a buried diffusion layer. For example, a single crystal P-type silicon substrate is used. In such a case, a well-known photolithography method or the like is used to add N-type impurities such as P or As at a high concentration, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁷ ions / cm ^2.
It is formed at a certain concentration. And low concentration, eg 1 ×
An N-type silicon layer having a concentration of about 10 ¹² to 1 × 10 ¹³ ions / cm ² is epitaxially grown. In this case, the epitaxial growth is performed by, for example, the CVD method, the MBE method, the A method.
It can be formed by the LE method or the like. The thickness of the epitaxial silicon layer at that time is not particularly limited, but is preferably about 1 to 10 μm. Then, a SiO ₂ film is formed on the epitaxial silicon layer by 1000 to _200.
After forming about 0Å, a trench is formed in a region where a collector extraction region and an isolation region are formed. The trench at this time can be formed by a known etching method, the depth is not particularly limited,
The trench for forming the collector lead-out region has a depth to reach the high-concentration N-type region formed as the buried diffusion layer, and the trench for forming the isolation diffusion region is formed on the P-type silicon substrate. It is preferable that the depth is as deep as possible. In addition, it is preferable to form the trench at the same time from the viewpoint of simplifying the process.

On the epitaxial silicon layer including the trench, a Si film having a film thickness of about 1000 to 5000 Å is formed.
An O ₂ film is deposited, and an S ₂ film is formed on the epitaxial silicon layer and on the bottom of the trench by a known etching method.
The iO ₂ film is removed by etching, leaving the SiO ₂ film covers only the side surface of the trench. Then, for example, by a photolithography process, 1 × 10 ¹⁶ to 1 × 1 of a P-type impurity such as boron is added to the bottom of the trench to be the isolation diffusion region.
Implantation is carried out at a concentration of about 0 ¹⁷ ions / cm ² , and N-type impurities such as P or As are added at 1 × 10 ¹⁶ to 1 × 10 ^{17 at the} bottom of the trench serving as the collector extraction region in the same manner as above.
It is injected at a concentration of about ions / cm ² .

Amorphous silicon is laminated on the entire surface of the epitaxial silicon layer including the trench by a known method such as the CVD method. At this time, a SiO ₂ protective film of about 1000 to 5000 Å is formed on the epitaxial silicon layer. The film thickness of amorphous silicon is not particularly limited,
It is preferable that the trenches are stacked with a film thickness that is equal to or larger than the thickness that allows the trenches to be completely buried. Then, heat treatment is performed. The heat treatment at this time is, for example, 30 to 60 at a normal pressure and a temperature range of about 1000 to 1100 ° C. in an N ₂ or Ar atmosphere.
It is preferable to perform the treatment for about a minute. By this heat treatment,
Amorphous silicon that is in contact with the single crystal silicon at the bottom of the trench gradually becomes single crystal from the portion that is in contact with the single crystal silicon. At the same time as this single crystallization, the heat treatment diffuses the impurity ions injected into the trench bottoms, which are the isolation region and the collector extraction region, into the amorphous or single crystallized silicon buried in the trench. Become.

In the present invention, since the amorphous silicon is single-crystallized sequentially from the lower side in contact with the single-crystal silicon, the amorphous silicon buried in the trench may be completely single-crystallized. .. Then, the amorphous silicon laminated on the silicon layer is selectively removed. At this time, for amorphous silicon, for example, a method of detecting the change in the Si concentration in the waste liquid by spin etching using KOH or HF / HNO ₃ type etchant, and stopping the supply of the etchant when the SiO ₂ on the surface is exposed, etc. Thus, it can be selectively removed by etching.

After that, each element can be formed by a usual method. Although the case of forming an NPN transistor has been described above, this is merely for convenience of description, and a PNP transistor is essentially the same, and the present invention naturally extends to them.

[0014]

According to the above-described method, (i) a low-concentration first-conductivity-type silicon layer is laminated on the entire surface of a second-conductivity-type silicon substrate in which a high-concentration first-conductivity-type region is formed as a buried diffusion region. After forming an oxide film on the entire surface of the silicon layer, a trench reaching a buried diffusion region is formed in the silicon layer in a region where a collector extraction region is formed, and at the same time, a trench is formed in a region in which an isolation diffusion region is formed. , A step of forming a trench reaching the silicon substrate, (i
i) a step of covering only the side surface in the trench with an oxide film, and (iii) a second step at the bottom of the trench to be the isolation diffusion region.
Implanting a conductivity type impurity, and implanting a first conductivity type impurity into the bottom of the trench to be the collector extraction region,
(Iv) a step of laminating amorphous silicon on the entire surface of the silicon layer including the trench and performing heat treatment, (v)
Since the step of selectively removing the amorphous silicon on the silicon layer is included, the isolation diffusion region and the collector extraction region formed in the silicon layer are separated by the oxide film, and the isolation in the formation process is performed. Lateral diffusion of the diffusion region and the collector extraction region is suppressed.

Further, since amorphous silicon is laminated on the entire surface of the silicon layer including the trench and heat-treated, the isolation diffusion region and the collector extraction region become the isolation diffusion region at the same time as the amorphous silicon is single-crystallized. The second-conductivity-type impurities implanted into the bottom of the trench and the first-conductivity-type impurities implanted into the bottom of the trench, which will be the collector extraction region, are diffused upward into the single crystal silicon, so that the heat treatment process can be suppressed. This suppresses an effective reduction in the thickness of the low-concentration first-conductivity-type silicon layer.

[0016]

EXAMPLE An example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. First, a SiO ₂ film (not shown) is formed on the surface of the P-type silicon substrate 1 by thermal oxidation, and then S is formed by a photolithography process.
The iO ₂ film is patterned. Then, using the SiO ₂ film as a mask, P or As ions of about 1 × 10 ¹⁷ ions / cm ² are ion-implanted to form the N ⁺ buried diffusion region 2, and then a film thickness of about 5 μm and 5Ω ·
cm of N-type epitaxial silicon layer 3 is laminated. Then, the SiO ₂ film 4 having a thickness of about 2000 Å is formed by thermal oxidation.
Then, the SiO ₂ film 4 is patterned into a desired shape, and trenches 7b and 7a having a depth of about 5 μm are formed in the isolation diffusion region 6 and the collector extraction region 5 as much as possible (FIG. 1A). ..

Then, a SiO ₂ film (not shown) having a film thickness of about 100 to 500 Å is formed on the inner walls of the trenches 7b and 7a by thermal oxidation, and then the epitaxial silicon layer 3 including the trenches 7b and 7a is formed by the CVD method. 5,000
Stacking an SiO ₂ film 8 of about Å, by anisotropic etching, trenches 7b, the SiO ₂ film 8 laminated on 7a bottom is removed by etching, the SiO ₂ film which covers only the side surface of the trench 7b, 7a Leave 8 (FIG. 1 (b)).

Then, by patterning the resist, P type impurity ions such as boron of about 1 × 10 ¹⁷ ions / cm ² are implanted into the bottom of the trench 7b formed in the region as much as the isolation diffusion region 6 (see FIG. 1
(C)). Further, by patterning the resist 9, 1 × 10 ¹⁷ ions / cm is formed at the bottom of the trench 7a formed in the region as close as possible to the collector extraction region 5.
^{About 2} N-type impurity ions such as P are implanted (Fig. 1
(D)).

Next, an epitaxy including the trenches 7a and 7b is performed.
On the axial silicon layer 3, a film with a film thickness of about 5000Å
Deposition of rufus silicon 10 (Fig. 1 (e)), for example
For example, N ₂Atmospheric pressure, 1000 to 1100 ° C
Heat treatment is performed for 30 to 60 minutes in the temperature range (Fig. 2
(F)). By this heat treatment, contact with the silicon substrate 1
Amorphous silicon 1 in the trenches 7a, 7b
At the same time that only 0 is crystallized, the separation diffusion region 6 and
Bottoms of the trenches 7a and 7b which will be the collector extraction regions 5
The impurities injected into the portion are diffused upward.

Then, only the amorphous silicon 10 laminated on the epitaxial silicon layer 3 is spin-etched with a KOH-based etchant, for example.
The change in the Si concentration in the waste liquid is detected, and the SiO ₂ on the surface is detected.
Etching is selectively removed by a method of stopping the supply of the etchant when exposed (FIG. 2G). Then, the SiO ₂ film 4 on the epitaxial silicon layer 3 is selectively removed (FIG. 2 (h)), and then, by the same method as the method of forming the N ⁺ buried diffusion region 2 in the P-type silicon substrate 1. P ⁺ impurities are ion-implanted to form the base region 12
Are implanted with N ⁺ impurity ions to form the emitter region 13. Then, after the oxide film 4 is formed on the silicon substrate 1, contact holes are formed on the emitter, collector and base regions of the oxide film 4, and the electrodes 14, 15 and 1 are formed.
6 is formed (FIG. 2 (i)).

In the semiconductor device thus formed,
Is formed on the silicon layer 3. ⁺Separation and diffusion area 6
And N⁺Of the collector extraction region 5 of₂By membrane 8
Because of the separation, lateral diffusion during the formation process
Can be suppressed. Also, amorphous silicon
When 10 is single crystallized, the collector extraction region 5 and
Impurity diffusion from below the separation diffusion region 6 is performed.
Therefore, it is necessary to reduce the thickness of the effective epitaxial silicon layer 3.
Can be suppressed.

[0022]

According to the method of manufacturing a semiconductor device according to the present invention, (i) a low-concentration second substrate is formed on the entire surface of a second-conductivity-type silicon substrate in which a high-concentration first-conductivity type region is formed as a buried diffusion region. After laminating a 1-conductivity type silicon layer and forming an oxide film on the entire surface of the silicon layer, a trench reaching a buried diffusion region is formed in the silicon layer in a region where a collector extraction region is formed, and at the same time, an isolation diffusion region is formed. A step of forming a trench reaching the silicon substrate in the silicon layer in a region to be formed; (ii) a step of covering only a side surface of the trench with an oxide film; (iii) a second step at the bottom of the trench to be the isolation diffusion region. Implanting a conductivity type impurity and implanting a first conductivity type impurity into the bottom of the trench to be the collector extraction region, (iv) forming an ammo on the entire surface of the silicon layer including the trench. Since the step of stacking the fas silicon and performing the heat treatment, and (v) the step of selectively removing the amorphous silicon on the silicon layer are included, the isolation diffusion region and the collector extraction region formed in the silicon layer are oxidized. Since it is separated by the film, it is possible to suppress the lateral diffusion of the separation diffusion region and the collector extraction region during the formation process, and further consider the depletion layer when an electric field is applied to this semiconductor device. Without
Since the transistor layout can be performed, the cell area can be significantly reduced.

Further, since amorphous silicon is laminated on the entire surface of the silicon layer including the trench and heat-treated, the isolation diffusion region and the collector extraction region become the isolation diffusion region at the same time as the amorphous silicon is single-crystallized. The second-conductivity-type impurities implanted into the bottom of the trench and the first-conductivity-type impurities implanted into the bottom of the trench, which will be the collector extraction region, are diffused upward into the single crystal silicon, so that the heat treatment process can be suppressed. This makes it possible to suppress an effective reduction in the thickness of the low-concentration first conductivity type silicon layer.

Therefore, it is possible to form an element isolation region having an extremely small area, and it is possible to contribute to mass production of integrated circuits such as bipolar LSI.

[Brief description of drawings]

FIG. 1 is a manufacturing process explanatory view showing an embodiment of a semiconductor device manufacturing method according to the present invention.

FIG. 2 is a manufacturing process explanatory view showing the embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 4 is a schematic cross-sectional view showing an example of a conventional semiconductor device.

[Explanation of symbols]

1 Silicon Substrate 2 Embedded Diffusion Region 3 Silicon Layer 4 SiO ₂ Film (Oxide Film) 5 Collector Extraction Region 6 Separation Diffusion Region 7a, 7b Trench 8 SiO ₂ Film (Oxide Film) 10 Amorphous Silicon

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/76 L 9169-4M 27/06

Claims (1)

[Claims] 1. A low-concentration first-conductivity-type silicon layer is laminated on the entire surface of a second-conductivity-type silicon substrate on which a high-concentration first-conductivity-type region is formed as an embedded diffusion region, and the silicon layer is formed on the silicon layer. After forming an oxide film on the entire surface, a trench reaching a buried diffusion region is formed in the silicon layer in a region where a collector extraction region is formed, and at the same time, a silicon substrate is reached in the silicon layer in a region where an isolation diffusion region is formed. A step of forming a trench; (ii) a step of covering only a side surface in the trench with an oxide film; (iii) an impurity of a second conductivity type is injected into a bottom portion of the trench to be the isolation diffusion region to form the collector extraction region. A step of implanting a first conductivity type impurity into the bottom of the trench, (iv) a step of stacking amorphous silicon on the entire surface of the silicon layer including the trench and performing a heat treatment (V) a method of manufacturing a semiconductor device characterized by comprising the step of selectively removing the amorphous silicon on said silicon layer.