CN101009484B - Novel single-end unit delay part - Google Patents
Novel single-end unit delay part Download PDFInfo
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- CN101009484B CN101009484B CN 200610023744 CN200610023744A CN101009484B CN 101009484 B CN101009484 B CN 101009484B CN 200610023744 CN200610023744 CN 200610023744 CN 200610023744 A CN200610023744 A CN 200610023744A CN 101009484 B CN101009484 B CN 101009484B
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- electric capacity
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Abstract
Nowadays, single end unit delay element possesses defects of weak antinoise capability and oversize domain, so the antinoise capability of integral circuit is weak and the domain area is big. The invention adopts PMOS capacitance to replace the NMOS capacitance used in current technique, so the antinoise capability of single end unit delay element is improved and the domain area is decreased, the performance of the DLL circuit and other analogue circuit is improved.
Description
Technical field
The present invention relates to integrated circuit (Integrated Circuit, IC) delay unit in the design, be particularly related to the single-end unit delay part (single ended Unit Delay) that often uses in the DLL circuit such as (delay phase-locked loop, Delay Loop Locking).
Background technology
Phase-locked loop is that it can play frequency multiplication and synthetic, reduces effects such as skew and shake output phase and input phase reponse system relatively.Be widely used in the electronics and the communications field, wherein a class comparison most important forms is DLL.
At present, single-end unit delay part has in integrated circuit (IC) design widely to be used, and in DLL, this kind parts just often are used especially.
With reference to the structural representation of DLL shown in Figure 1, wherein, the overall delay of analog D LL (1 part among Fig. 1) includes single-end unit delay part, and this single-end unit delay part is repeated to use to realize clock lock.And the combination of the delay feature of above-mentioned DLL by several these single-end unit delay parts realizes.For example, if we use 10 above-mentioned single-end unit delay parts to carry out clock lock, and to make each single-end unit delay part time of delay be 1/10th of the required clock cycle, 10 so above-mentioned single-end unit delay part combination backs have been about to the clock cycle bulk delay clock cycle, thereby have finished delay feature.This just means that also clock phase divides equally according to the quantity of the single-end unit delay part of forming above-mentioned whole DLL or other similar circuit.
By above-mentioned approach, though can realize clock delay fully; But, because the use of numerous above-mentioned single-end unit delay parts, make the weak and oversize shortcoming of domain (layout) of Noise Resistance Ability of this element, to the performance of entire circuit and creating a great impression of chip area.
And the single-end unit delay part that the overall delay among the existing DLL partly adopts usually as shown in Figures 2 and 3.Wherein, Fig. 2 has described a kind of structure relatively more commonly used, the output (out) (22) of inverter (inverter) is connected NMOS (N type-metal-oxide semiconductor fieldeffect transistor, N type metal-oxide-semiconductor field effect transistor) on the grid (23), the source electrode of NMOS, drain electrode all are connected V
SSOn (ground wire voltage) (24).From figure, can find, in this circuit, only use NMOS electric capacity, not use transmission transistor (pass transistor).Under these circumstances, because the capacitance of NMOS unit are is not high, so, reach needed capacitance and must adopt larger area NMOS to realize.
As seen, the way of above-mentioned use NMOS makes that the area of circuit layout is bigger.
In addition, because in said structure, NMOS electric capacity is directly gone up at P type substrate (P-SUB) and is made, and other element, for example transistor and resistance etc., also be produced on the same P type substrate, like this, NMOS electric capacity and element on every side, for example transistor and resistance etc., do not separate, from the interference of element on every side, for example fluctuation that causes of the instability of voltage or electric current just impacts NMOS electric capacity easily, thereby influence the stable of whole single-end unit delay part, make such structure not have good Noise Resistance Ability.
Analysis chart 3 again, and it has described another kind of common structure.Wherein, the output of inverter is connected on the drain terminal of transmission transistor, and the grid of this transmission transistor (33) is connected V
CTRLOn (control voltage), its source electrode is connected on the grid (35) of the NMOS electric capacity that is positioned at the below, and the source electrode of this NMOS electric capacity, drain electrode, substrate all are connected on the Vss (34).In this circuit, owing to when having used NMOS, also used the transmission transistor structure, thereby make the NMOS of unit are have bigger electric capacity, therefore, to compare with Fig. 2, the chip area of the single-end unit delay part that this kind structure is formed is less.But, under this kind situation, since the NMOS unit not with on every side other elements, for example transistor and resistance etc., separate mutually, the fluctuation of voltage, electric current on every side is still influential to the NMOS unit, thereby influences the stable of whole single-end unit delay part, thereby the noise resistance performance of entire circuit still needs to improve.
If can search out a kind of can be under the prerequisite of the clock delay function that does not influence above-mentioned DLL circuit or similar circuit, while can be improved the Noise Resistance Ability of entire circuit again and be reduced the method for single-end unit delay part layout size, for above-mentioned circuit very important meaning will be arranged so.
Summary of the invention
To achieve these goals, the invention provides a kind of technical scheme that reduces the area of single-end unit delay part and improve its Noise Resistance Ability.
The inventor recognizes, in the existing scheme all is that NMOS electric capacity directly is produced on the P type substrate, and other elements also directly are produced on the same P type substrate, thereby causes a little less than the Noise Resistance Ability of entire circuit, therefore, should improve its Noise Resistance Ability by changing this mode.
For this reason, the thought of the solution that the inventor proposes is, make N trap (N-WELL) at P type substrate, in this N trap, make PMOS (P type-metal-oxide semiconductor fieldeffect transistor then, P type metal-oxide-semiconductor field effect transistor), can improve the Noise Resistance Ability of single-end unit delay part like this, also can reduce its chip area, thereby realize purpose of the present invention.
The circuit of the single-end unit delay part that content provided according to the present invention has two kinds of schemes.
First kind of scheme comprises inverter and electric capacity, with reference to figure 4, it is characterized in that, described electric capacity is PMOS (45), and the output of inverter (43) is connected on the grid of PMOS, and the source electrode of PMOS, drain electrode all are connected V
CTRL(46) on.
Second kind of scheme comprises inverter and electric capacity, with reference to figure 5, it is characterized in that, described electric capacity is PMOS (55), and described PMOS also is connected with transmission transistor, and the output of inverter (52) is connected on the drain terminal (53) of transmission transistor V
CTRLBe connected on the grid (57) of transmission transistor, the source electrode of described transmission transistor (54) is connected on the grid (58) of PMOS, and the source electrode of PMOS, drain electrode and substrate all are connected V
CTRL(56) on.
Adopt said structure, in fact in P type substrate (P-SUB), form the N trap, in the N trap, make PMOS electric capacity again.Because N trap and P type substrate form PN junction, so the PMOS of making in the N trap, and has separated on every side.Because stopping of PN junction, the interference around making reduces greatly to the interference of PMOS, has improved the Noise Resistance Ability of single-end unit delay part, and then has improved the Noise Resistance Ability of the circuit that uses this single-end unit delay part.
In addition, PMOS electric capacity of the present invention has higher electric capacity with respect to original NMOS electric capacity, also will reduce so reach the specified needed area of electric capacity, thereby reach the effect that reduces single-end unit delay part.
Description of drawings
Fig. 1 is the structured flowchart of DLL circuit.
Fig. 2 is to use the circuit diagram of NMOS as the single-end unit delay part of electric capacity.Wherein, the 21st, input, the 22nd, output, the 23rd, the grid of NMOS.
Fig. 3 is to use the circuit diagram of single-end unit delay part of the structure of NMOS and transmission transistor.The 31st, the input of inverter, the 32nd, the output of inverter, the 33rd, the grid of transmission transistor is linked to V
CTRLOn, the 35th, the grid of PMOS electric capacity, the 34th, ground wire is designated as V
SS.
Fig. 4 is the circuit diagram of one embodiment of the present of invention, the 41st, and inverter, the 42nd, the input of inverter, the 43rd, the output of inverter, the 44th, the grid of PMOS, the 45th, PMOS electric capacity, line 46 are connected to control voltage V
CTRLOn.
Fig. 5 is the circuit diagram of one embodiment of the present of invention, the 52nd, and inverter, the 51st, the input of inverter, the 53rd, the drain electrode of transmission transistor, the 54th, transmission transistor, the 57th, the grid of transmission transistor is connected to control voltage V
CTRLOn, the 58th, the grid of PMOS electric capacity, the 55th, PMOS electric capacity, line 56 are connected to control voltage V
CTRLOn.
Fig. 6 is that prior art is used, i.e. Fig. 2 and NMOS employed in figure 3, and 64 is the NMOS structure chart, the 61st, the grid of NMOS is designated as the A end, and the 65th, the P substrate.。
Fig. 7 is the structure chart of the PMOS that adopts in one embodiment of the present of invention, the 72nd, and PMOS, 71 lines are connected to control voltage V
CTRLOn, the 75th, the grid of PMOS is designated as the A end, and 76 is ground wire voltage V
SS, 73 is the N trap, the 74th, and the P substrate.
Fig. 8 is in the prior art and the variations in threshold voltage comparison diagram of scheme provided by the invention.
Fig. 9 is the capacitance characteristic curve chart.The 91st, the groundwork district of the PMOS electric capacity that the present invention adopts, the 92nd, the groundwork district of the NMOS electric capacity that original technology adopts.
Figure 10 is the structure chart of the PMOS that adopts among another embodiment of the present invention, the 102nd, and PMOS, the 101st, the grid of PMOS, the 103rd, N trap, the 104th, P trap, the 105th, N substrate.
Embodiment
With reference to figure 1, it is the structured flowchart of DLL circuit, and it has described the operational environment of DLL.Wherein, overall delay parts (1) have two inputs, be respectively reference voltage and control voltage, delay has taken place through described output clock behind the overall delay parts, this output clock and reference clock are input to the phase detection parts as input parameter more jointly, after these phase detection parts compared two input parameters, its result was re-used as the input of voltage pump, and this voltage pump is promptly imported according to this and produced control voltage.Single-end unit delay part involved in the present invention promptly is used in the described overall delay parts (1).
Fig. 4 is the circuit diagram of one embodiment of the present of invention.With reference to figure 4, the output (43) of inverter (41) is connected on the grid of PMOS (45), and the source electrode of PMOS (45), drain electrode all are connected V
CTRL(46) on.
The circuit diagram of Fig. 5 one embodiment of the present of invention.With reference to figure 5, the output of inverter (52) is connected on the drain terminal (53) of transmission transistor (54), V
CTRLBe connected on the grid (57) of transmission transistor, the source electrode of transmission transistor (54) is connected on the grid (58) of PMOS electric capacity (55), and source electrode, drain electrode and the substrate of PMOS electric capacity (55) all are connected V
CTRL(56) on.
With reference to figure 6, it has described the structure chart of the nmos pass transistor of prior art employing.NMOS electric capacity (64) is directly gone up at P type substrate (65) and is made, and other element, for example transistor and resistance etc. though do not show in the drawings, also are produced on the same P type substrate (65).
With reference to figure 7, it has described the structure chart of the PMOS (72) of the present invention's employing.Go up making N trap (73) at P type substrate (74), in N trap (73), make PMOS (72).With reference to figure 4, because PMOS (72) is made in the N trap (73), N trap (73) forms PN junction with P type substrate (74), make that PMOS (72) and P type substrate (74) are isolated, with Fig. 2, Fig. 3 and structure shown in Figure 7, i.e. NMOS electric capacity and on every side element, for example transistor and resistance etc., the situation that does not have separation produces striking contrast.Because above-mentioned buffer action, make the Noise Resistance Ability of circuit of structure shown in Figure 7 be significantly improved with respect to the circuit of Fig. 2, Fig. 3, structure shown in Figure 7.
Compare with Fig. 2, among Fig. 4, Fig. 5 and Fig. 7, it still uses existing process conditions, and therefore for example at present frequent used twin well process, just can realize structure of the present invention under existing technology.
In addition, we also can compare explanation advantage of the present invention with the scheme of prior art and the present invention's employing.
With reference to figure 3, under the situation that adopts the single-end unit delay part of structure shown in this figure, when output during in decrement phase, voltage Vdd trend 0, then the drain terminal voltage of transmission transistor trends towards 0, make that this tube resistor trend is infinitely great, thereby electric capacity does not work.
When above-mentioned output end voltage is not 0, following several situation is arranged:
Work as V
CTRL＜V
TWhen (that is: the threshold voltage of transmission transistor), because V
CTRL＜V
T, transfer tube is not opened, and the situation of output can not influence capacitance.
Work as 2V
T＞V
CTRL＞V
T, and V
AThe voltage of A end (that is: be added in)＜V
TThe time, the transmission transistor conducting of NMOS, but the NMOS electric capacity of below is in accumulation area, i.e. Cap=ε A/Tox, the NMOS capacitance is bigger, and wherein Tox refers to that oxidated layer thickness, A refer to the mos capacity area;
Work as V
CTRL＞V
T, and VA＜V
TThe time, same, the NMOS of below is in accumulation area, and its electric capacity and its oxide layer capacitance are all Cap=ε A/Tox mutually, and capacitance is bigger;
Work as V
CTRL＞2V
T, and V
A＞V
TThe time, the NMOS of below enters depletion region, covers electric capacity and begins to occur, and its capacitance is: Cap=ε A/Tox, wherein, Cap=Cgs+Cgd+Cgb, Cgs are the covering electric capacity of finger grid and source electrode, and Cgd is the covering electric capacity of finger grid and drain electrode, Cgb is the electric capacity of finger grid to substrate, because under high frequency situations, the value of Cgb is 0, so Cap=Cgs+Cgd herein.
Because in Fig. 4 structure, the source electrode of NMOS electric capacity and drain electrode all connect together, so work as V
GsDuring＜VT, electric capacity is operated in by the district, works as V
GS＞V
TThe time, NMOS electric capacity is operated in depletion region.And the threshold voltage of NMOS is higher, so NMOS electric capacity operates mainly in by the district, electric capacity is not high relatively.
With reference to figure 5, adopt structure provided by the invention after, its performance will take place significantly to change, specific as follows shown in:
When output during in decrement phase, same, voltage Vdd trend 0, then the drain terminal voltage of transmission transistor trends towards 0, make that this tube resistor trend is infinitely great, thereby electric capacity does not work.
So:
Work as V
CTRL＜V
TThe time, transfer tube is not opened, and electric capacity does not influence output;
Work as V
CTRL＞V
TAnd V
CTRL-V
T(PMOS)＜V
A＜V
CTRL-V
T(NMOS) time, the transmission transistor conducting, PMOS electric capacity is at accumulation area, and at this moment, the grid end of PMOS is connected in output, and leak in the source and substrate all is connected in V
CTRL(0.85) go up Cap=ε A/Tox, capacitance is bigger;
Work as V
CTRL＞V
t, and VA (A terminal voltage)＜V
CTRLDuring-Vt (PMOS), the transmission transistor conducting, PMOS enters depletion region, and at this moment, capacitance is Cap=ε A/Tox (Cgs+Cgd);
Because among Fig. 3 or Fig. 5, the source class of mos capacitance leaks level and all connects together, so work as V
GsDuring＜VT, electric capacity is operated in by the district, works as V
GS＞V
TThe time, electric capacity is operated in depletion region.
Below table 1 mos capacitance has been described at the oxide layer electric capacity of each service area with cover capacitive component value such as electric capacity.Mos capacitance, promptly Cg mainly is made of for the covering capacitor C gd that drains for the covering capacitor C gs and the grid of source electrode capacitor C gb, the grid of grid for substrate, i.e. Cg=Cgb+Cgs+Cgd.For example, when mos capacitance worked in the unsaturation district, grid was 0 for the value of the capacitor C gb of substrate, and grid is ε A/2Tox for the value of the covering capacitor C gs of source electrode, grid is ε A/2Tox also for the value of the covering capacitor C gd of drain electrode, thereby makes that the value of mos capacitance is ε A/Tox.
Table 1
With reference to figure 8, it has described in the prior art and the contrast of the threshold voltage variation of scheme provided by the invention.Wherein, the horizontal line of the top is represented output voltage, and the horizontal line of its below represents to control voltage (V
CTRL), Xia Fang horizontal line is represented the threshold voltage of NMOS again, the most empty horizontal line of below is represented the threshold voltage of PMOS.The broken circle of the left and right sides is represented the rollback point of MOS transistor.As seen, the threshold voltage of PMOS is little more a lot of than the threshold voltage of NMOS, so under identical control voltage, PMOS is operated in depletion region more, NMOS is operated in cut-off region more.
Fig. 9 is the capacitance characteristic curve chart.Wherein 92 represent the main service area of NMOS electric capacity in the prior aries, the groundwork district of PMOS electric capacity in the 91 expressions solution provided by the present invention.With reference to figure 9, as seen, under identical control voltage, PMOS is operated in depletion region more, and NMOS is operated in cut-off region more, and therefore, capacitance characteristic has had remarkable improvement.
Thereby behind employing the present invention, Fig. 5 structural circuit is than Fig. 3 structural circuit, and capacitance improves, and curve is relatively stable, so chip area can correspondingly reduce, owing to adopted the trap of separating on the structure, makes the noise resistance performance that obvious improvement also arranged again.
With reference to Figure 10, it is the structure chart of another embodiment of the present invention.Different is with Fig. 7, and structure shown in Figure 10 adopts triple-well (triple well) technology.With reference to Figure 10, at first go up and make P trap (P-Well) at N type substrate (N-SUB), in the P trap, make little N trap (N-well) then, and then in the N trap, make required PMOS electric capacity.Such structure can be applied in summary of the invention provided by the invention on the N type substrate, thereby makes that the application of content of the present invention is more extensive.
In other embodiments, also can content of the present invention be applied in the different circuit by triple-well process with reference to Figure 10.Those skilled in the art can be understood and realized with reference to foregoing, so will not give unnecessary details.
Although the present invention is illustrated with aforesaid preferred embodiment, but the foregoing description is not to be used for limiting the present invention, any technical staff that this field is familiar with, enlightenment according to design philosophy of the present invention, concrete summary of the invention and embodiment, should various changes and adjustment, and by these changes with adjust resulting new content and should be contained by content of the present invention.
Claims (2)
1. single-end unit delay part that can reduce chip area and improve Noise Resistance Ability, comprise inverter and electric capacity, it is characterized in that, described electric capacity is PMOS, and the output of inverter is connected on the grid of PMOS, and the source electrode of PMOS, drain electrode all are connected on the control voltage, and described PMOS makes in the N trap, and this N trap is formed in the P type substrate or this N trap is formed in the P trap based on N type substrate.
2. single-end unit delay part that can reduce chip area and improve Noise Resistance Ability, comprise inverter and electric capacity, it is characterized in that, described electric capacity is PMOS, and this PMOS also is connected with transmission transistor, and the output of inverter is connected on the drain terminal of transmission transistor, control voltage is connected on the grid of transmission transistor, the source electrode of described transmission transistor is connected on the grid of PMOS, and the source electrode of PMOS, drain electrode and substrate all are connected on the control voltage, described PMOS makes in the N trap, and this N trap is formed in the P type substrate or this N trap is formed in the P trap based on N type substrate.
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| CN 200610023744 CN101009484B (en) | 2006-01-28 | 2006-01-28 | Novel single-end unit delay part |
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| CN 200610023744 CN101009484B (en) | 2006-01-28 | 2006-01-28 | Novel single-end unit delay part |
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| CN101009484B true CN101009484B (en) | 2011-05-11 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793238A (en) * | 1996-11-01 | 1998-08-11 | Cypress Semiconductor Corp. | RC delay with feedback |
| US6448833B2 (en) * | 2000-03-08 | 2002-09-10 | Nec Corporation | Delay circuit |
| CN1419292A (en) * | 2001-11-14 | 2003-05-21 | 三菱电机株式会社 | Semiconductor memory |
| CN1638276A (en) * | 2003-12-24 | 2005-07-13 | 三洋电机株式会社 | Delay circuit and display including the same |
-
2006
- 2006-01-28 CN CN 200610023744 patent/CN101009484B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5793238A (en) * | 1996-11-01 | 1998-08-11 | Cypress Semiconductor Corp. | RC delay with feedback |
| US6448833B2 (en) * | 2000-03-08 | 2002-09-10 | Nec Corporation | Delay circuit |
| CN1419292A (en) * | 2001-11-14 | 2003-05-21 | 三菱电机株式会社 | Semiconductor memory |
| CN1638276A (en) * | 2003-12-24 | 2005-07-13 | 三洋电机株式会社 | Delay circuit and display including the same |
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| Publication number | Publication date |
|---|---|
| CN101009484A (en) | 2007-08-01 |
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