Browse Books

Camarero C, Martínez C and Beivide R (2024). Ant Mill: an adversarial traffic pattern for low-diameter direct networks, The Journal of Supercomputing, 80:12, (18062-18080), Online publication date: 1-Aug-2024.

Wang Y, Zhao H, Wang Y, Wang B, Liu Y and Wu J (2024). PKCA, Transactions on Emerging Telecommunications Technologies, 35:4, Online publication date: 8-Apr-2024.

Yang J, Zheng H and Louri A (2024). Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration, IEEE Transactions on Parallel and Distributed Systems, 35:2, (349-361), Online publication date: 1-Feb-2024.

Yan J, Wang M, Qin Y and Yu Z CRAFT: Common Router Architecture for Throughput Optimization Algorithms and Architectures for Parallel Processing, (212-229)

Ravi G, Krishna T and Lipasti M (2023). TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency, ACM Transactions on Architecture and Code Optimization, 20:3, (1-25), Online publication date: 30-Sep-2023.

Reza M (2023). Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures, ACM Journal on Emerging Technologies in Computing Systems, 19:3, (1-26), Online publication date: 31-Jul-2023.

Sambangi R, Pandey A, Manna K, Mahapatra S and Chattopadhyay S (2023). Application Mapping Onto Manycore Processor Architectures Using Active Search Framework, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31:6, (789-801), Online publication date: 1-Jun-2023.

Zhou W, Ouyang Y, Xu D, Huang Z, Liang H and Wen X (2023). Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31:4, (442-455), Online publication date: 1-Apr-2023.

Adusumilli V and TG V (2023). Traffic Characterization Based Stochastic Modelling of Network-on-Chip, IEEE Transactions on Computers, 72:4, (1215-1222), Online publication date: 1-Apr-2023.

Khamis M, El-Ashry S, AbdElsalam M, El-Kharashi M and Shalaby A (2022). Emulation and verification framework for MPSoC based on NoC and RISC-V, Design Automation for Embedded Systems, 26:3-4, (133-159), Online publication date: 1-Dec-2022.

France-Pillois M, Gamatié A and Sassatelli G (2022). A Segmented Adaptive Router for Near Energy-Proportional Networks-on-Chip, ACM Transactions on Embedded Computing Systems, 21:4, (1-27), Online publication date: 31-Jul-2022.

Huang X, F. Ramos A and Deng Y (2022). Optimal circulant graphs as low-latency network topologies, The Journal of Supercomputing, 78:11, (13491-13510), Online publication date: 1-Jul-2022.

Yadav S and Raj R (2022). Power efficient network selector placement in control plane of multiple networks-on-chip, The Journal of Supercomputing, 78:5, (6664-6695), Online publication date: 1-Apr-2022.

Lee D, Lin B and Cheng C (2021). SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing, ACM Transactions on Architecture and Code Optimization, 19:1, (1-21), Online publication date: 31-Mar-2022.

Ge M, Ni X, Qi X, Chen S, Huang J, Kang Y and Wu F (2021). Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips, ACM Transactions on Design Automation of Electronic Systems, 27:1, (1-30), Online publication date: 31-Jan-2022.

Li C, Dong D, Yang S, Liao X, Sun G and Liu Y (2021). CIB-HIER, ACM Transactions on Architecture and Code Optimization, 18:4, (1-21), Online publication date: 31-Dec-2022.

Gangwar A, Sreedharan R, Prasad A, Agarwal N and Gade S Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip 2021 58th ACM/IEEE Design Automation Conference (DAC), (61-66)

Lee D, Lin B and Cheng C (2021). SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC, IEEE Embedded Systems Letters, 13:4, (158-161), Online publication date: 1-Dec-2021.

Bose A and Ghosal P A scalable NoC topology targeting network performance Proceedings of the 14th International Workshop on Network on Chip Architectures, (4-9)

Rettkowski J, Haase J, Primus S, Hübner M and Göhringer D Performance analysis of application-specific instruction-set routers in networks-on-chip Proceedings of the 14th International Workshop on Network on Chip Architectures, (16-21)

Park J, Kim B, Yun S, Lee E, Rhu M and Ahn J TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (268-281)

Ouyang Y, Sun C, Jia B, Wang Q and Liang H (2021). Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip, Microelectronics Journal, 116:C, Online publication date: 1-Oct-2021.

Zhang Y, Zhang N, Zhao T, Vilim M, Shahbaz M and Olukotun K SARA Proceedings of the 48th Annual International Symposium on Computer Architecture, (1041-1054)

Ro Y, Jin S, Huh J and Kim J Ghost routing to enable oblivious computation on memory-centric networks Proceedings of the 48th Annual International Symposium on Computer Architecture, (930-943)

Besta M, Domke J, Schneider M, Konieczny M, Girolamo S, Schneider T, Singla A and Hoefler T (2020). High-Performance Routing With Multipathing and Path Diversity in Ethernet and HPC Networks, IEEE Transactions on Parallel and Distributed Systems, 32:4, (943-959), Online publication date: 1-Apr-2021.

Chen P, Chen H, Zhou J, Liu D, Li S, Liu W, Chang W and Guan N Partial order based non-preemptive communication scheduling towards real-time networks-on-chip Proceedings of the 36th Annual ACM Symposium on Applied Computing, (145-154)

Ejaz A, Papaefstathiou V and Sourdis I (2021). HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers, IEEE/ACM Transactions on Networking, 29:1, (318-331), Online publication date: 1-Feb-2021.

Li M, Liu W, Duong L, Chen P, Yang L and Xiao C (2021). Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40:2, (260-273), Online publication date: 1-Feb-2021.

Deng Y, Guo M, Ramos A, Huang X, Xu Z and Liu W (2020). Optimal low-latency network topologies for cluster performance enhancement, The Journal of Supercomputing, 76:12, (9558-9584), Online publication date: 1-Dec-2020.

Bose A and Ghosal P A cube-tree hybrid NoC topology with 3D mirroring technique for load balancing Proceedings of the 1st ACM International Workshop on Nanoscale Computing, Communication, and Applications, (26-32)

Teh M, Hung Y, Michelogiannakis G, Yan S, Glick M, Shalf J and Bergman K TAGO Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (1-16)

Gangwar A, Agarwal N, Sreedharan R, Prasad A, Gade S and Xu Z Automated synthesis of custom networks-on-chip for real world applications Proceedings of the 39th International Conference on Computer-Aided Design, (1-9)

Wang L, Liu L, Wang X, Han J, Deng C and Wei S CDRing Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference, (1-6)

Zheng H, Wang K and Louri A A versatile and flexible chiplet-based system design for heterogeneous manycore architectures Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference, (1-6)

Wu Y, Shen M, Chen Y and Zhou Y Tuning applications for efficient GPU offloading to in-memory processing Proceedings of the 34th ACM International Conference on Supercomputing, (1-12)

McGlohon N, Ross R and Carothers C Evaluation of Link Failure Resilience in Multirail Dragonfly-Class Networks through Simulation Proceedings of the 2020 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, (105-116)

Abts D, Ross J, Sparling J, Wong-VanHaren M, Baker M, Hawkins T, Bell A, Thompson J, Kahsai T, Kimmell G, Hwang J, Leslie-Hurd R, Bye M, Creswick E, Boyd M, Venigalla M, Laforge E, Purdy J, Kamath P, Maheshwari D, Beidler M, Rosseel G, Ahmad O, Gagarin G, Czekalski R, Rane A, Parmar S, Werner J, Sproch J, Macias A and Kurtz B Think fast Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture, (145-158)

Cavalcante M, Kurth A, Schuiki F and Benini L Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems Proceedings of the 17th ACM International Conference on Computing Frontiers, (81-88)

Jain A, Laxmi V, Tripathi M, Gaur M and Bishnoi R (2020). TRACK, Integration, the VLSI Journal, 72:C, (92-110), Online publication date: 1-May-2020.

Derafshi D, Norollah A, Khosroanjam M and Beitollahi H (2020). HRHS: A High-Performance Real-Time Hardware Scheduler, IEEE Transactions on Parallel and Distributed Systems, 31:4, (897-908), Online publication date: 1-Apr-2020.

Xiang X, Sigdel P and Tzeng N (2020). Bufferless Network-on-Chips With Bridged Multiple Subnetworks for Deflection Reduction and Energy Savings, IEEE Transactions on Computers, 69:4, (577-590), Online publication date: 1-Apr-2020.

Zhanbolatov A, Vipin K, Dadlani A and Fedorov D StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures Applied Reconfigurable Computing. Architectures, Tools, and Applications, (361-375)

Song Y and Lin B (2020). Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding, ACM Transactions on Architecture and Code Optimization, 17:1, (1-26), Online publication date: 31-Mar-2020.

Dai Y, Wu K, Lai M, Li Q and Dong D PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction Algorithms and Architectures for Parallel Processing, (3-16)

Freivalds K, Ozolinš E and Šostaks A Neural shuffle-exchange networks - sequence processing in O(n log n) time Proceedings of the 33rd International Conference on Neural Information Processing Systems, (6630-6641)

Chen J, Zhou W, Dong Y, Wang Z, Cui C, Wu F, Zhou E and Tang Y (2019). Analyzing time-dimension communication characterizations for representative scientific applications on supercomputer systems, Frontiers of Computer Science: Selected Publications from Chinese Universities, 13:6, (1228-1242), Online publication date: 1-Dec-2019.

McDonald N, Isaev M, Flores A, Davis A and Kim J Practical and efficient incremental adaptive routing for HyperX networks Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (1-13)

Kunthara R, James R, Sleeba S and Jose J Asymmetric routing in 3D NoC using interleaved edge routers Proceedings of the 12th International Workshop on Network on Chip Architectures, (1-6)

Yazdanshenas S and Betz V (2019). The Costs of Confidentiality in Virtualized FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27:10, (2272-2283), Online publication date: 1-Oct-2019.

Chung J, Ro Y, Kim J, Ahn J, Kim J, Kim J, Lee J and Ahn J Enforcing Last-level Cache Partitioning through Memory Virtual Channels Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, (97-109)

Song Y and Lin B (2019). Uniform Minimal First: Latency Reduction in Throughput-Optimal Oblivious Routing for Mesh-Based Networks-on-Chip, IEEE Embedded Systems Letters, 11:3, (81-84), Online publication date: 1-Sep-2019.

Bahrami B, Jabraeil Jamali M and Saeidi S (2019). A hierarchical architecture based on traveling salesman problem for hybrid wireless network-on-chip, Wireless Networks, 25:5, (2187-2200), Online publication date: 1-Jul-2019.

Song Y, Alavoine O and Lin B (2019). A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets, ACM Transactions on Architecture and Code Optimization, 16:2, (1-23), Online publication date: 30-Jun-2019.

Chen Y and Louri A An online quality management framework for approximate communication in network-on-chips Proceedings of the ACM International Conference on Supercomputing, (217-226)

Zhang Y, Rucker A, Vilim M, Prabhakar R, Hwang W and Olukotun K Scalable interconnects for reconfigurable spatial architectures Proceedings of the 46th International Symposium on Computer Architecture, (615-628)

Bhatele A, Jain N, Mubarak M and Gamblin T Analyzing Cost-Performance Tradeoffs of HPC Network Designs under Different Constraints using Simulations Proceedings of the 2019 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, (1-12)

Izu C and Vallejo E Impact of Network Fairness on the Performance of Parallel Systems Proceedings of the Australasian Computer Science Week Multiconference, (1-10)

Vipin K and Kalomiros J (2019). AsyncBTree, International Journal of Reconfigurable Computing, 2019, Online publication date: 1-Jan-2019.

Besta M, Hassan S, Yalamanchili S, Ausavarungnirun R, Mutlu O and Hoefler T (2018). Slim NoC, ACM SIGPLAN Notices, 53:2, (43-55), Online publication date: 30-Nov-2018.

Turakhia Y, Bejerano G and Dally W (2018). Darwin, ACM SIGPLAN Notices, 53:2, (199-213), Online publication date: 30-Nov-2018.

Stephens B, Akella A and Swift M Your Programmable NIC Should be a Programmable Switch Proceedings of the 17th ACM Workshop on Hot Topics in Networks, (36-42)

Blumrich M, Jiang N and Dennison L Exploiting idle resources in a high-radix switch for supplemental storage Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, (1-13)

Blumrich M, Jiang N and Dennison L Exploiting idle resources in a high-radix switch for supplemental storage Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, (1-13)

Jha S, Formicola V, Martino C, Dalton M, Kramer W, Kalbarczyk Z and Iyer R (2018). Resiliency of HPC Interconnects: A Case Study of Interconnect Failures and Recovery in Blue Waters, IEEE Transactions on Dependable and Secure Computing, 15:6, (915-930), Online publication date: 1-Nov-2018.

Jain T and Schneider K Optimal self-routing split modules for radix-based interconnection networks Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design, (99-108)

Boraten T and Kodi A Securing NoCs against timing attacks with non-interference based adaptive routing Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Das A, Babu S, Jose J, Jose S and Palesi M Critical packet prioritisation by slack-aware re-routing in on-chip networks Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Bahrebar P and Stroobandt D (2018). Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs, ACM SIGBED Review, 15:3, (25-30), Online publication date: 15-Aug-2018.

Liu W, Ma S, Huang L and Wang Z (2018). The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs, International Journal of Parallel Programming, 46:4, (722-735), Online publication date: 1-Aug-2018.

Cheng X, Zhao Y, Zhao H and Xie Y Packet pump Proceedings of the 55th Annual Design Automation Conference, (1-6)

Cheng X, Zhao Y, Zhao H and Xie Y Packet Pump: Overcoming Network Bottleneck in On-Chip Interconnects for GPGPUs^* 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), (1-6)

Kim G, Choi H and Kim J TCEP Proceedings of the 45th Annual International Symposium on Computer Architecture, (712-725)

Naqvi S, Akram T, Haider S and Kamran M (2018). Artificial neural networks based dynamic priority arbitration for asynchronous flow control, Neural Computing and Applications, 29:7, (627-637), Online publication date: 1-Apr-2018.

Besta M, Hassan S, Yalamanchili S, Ausavarungnirun R, Mutlu O and Hoefler T Slim NoC Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, (43-55)

Turakhia Y, Bejerano G and Dally W Darwin Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, (199-213)

Chu T, Sato S and Kise K (2017). Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA, ACM Transactions on Reconfigurable Technology and Systems, 10:4, (1-27), Online publication date: 27-Dec-2017.

Thanh C, The A, Bui C, Pham H and Nguyen K An Efficient Compact Routing Scheme for Interconnection Topologies based on the Random Model Proceedings of the 8th International Symposium on Information and Communication Technology, (189-196)

Hojabr R, Modarressi M, Daneshtalab M, Yasoubi A and Khonsari A (2017). Customizing Clos Network-on-Chip for Neural Networks, IEEE Transactions on Computers, 66:11, (1865-1877), Online publication date: 1-Nov-2017.

Mische J, Mellwig C, Stegmeier A, Frieb M and Ungerer T Minimally buffered deflection routing with in-order delivery in a torus Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Effiong C, Sassatelli G and Gamatie A Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Bhardwaj K, Jiang W and Nowick S Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Wang P, Niknam S, Wang Z and Stefanov T A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, (1-8)

Gardea J, Jin Y, Badawy A and Cook J Performance Evaluation of Mesh-based 3D NoCs Proceedings of the 10th International Workshop on Network on Chip Architectures, (1-6)

Chen X, Lu Z, Liu S and Chen S (2017). Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems, ACM Transactions on Embedded Computing Systems, 16:5s, (1-21), Online publication date: 10-Oct-2017.

Li J, Li M, Xue C, Ouyang Y and Shen F (2017). Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches, IEEE Transactions on Computers, 66:10, (1747-1762), Online publication date: 1-Oct-2017.

Ebrahimi M and Daneshtalab M (2017). EbDa, ACM SIGARCH Computer Architecture News, 45:2, (703-715), Online publication date: 14-Sep-2017.

Wang M and Li Z (2017). A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25:9, (2419-2433), Online publication date: 1-Sep-2017.

Bahrami B, Jabraeil Jamali M and Saeidi S (2017). A Demand-Based Structure for the Architecture of Wireless Networks on Chip, Wireless Personal Communications: An International Journal, 96:1, (455-473), Online publication date: 1-Sep-2017.

Zhao X and Lu Z (2017). A Tool for xMAS-Based Modeling and Analysis of Communication Fabrics in Simulink, ACM Transactions on Modeling and Computer Simulation, 27:3, (1-26), Online publication date: 31-Jul-2017.

Yudi J, Humberto Llanos C and Huebner M (2017). System-level design space identification for Many-Core Vision Processors, Microprocessors & Microsystems, 52:C, (2-22), Online publication date: 1-Jul-2017.

Ebrahimi M and Daneshtalab M EbDa Proceedings of the 44th Annual International Symposium on Computer Architecture, (703-715)

Lottarini A, Edwards S, Ross K and Kim M Network Synthesis for Database Processing Units Proceedings of the 54th Annual Design Automation Conference 2017, (1-6)

Daya B, Peh L and Chandrakasan A Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems Proceedings of the 54th Annual Design Automation Conference 2017, (1-6)

Xiang X, Shi W, Ghose S, Peng L, Mutlu O and Tzeng N Carpool Proceedings of the International Conference on Supercomputing, (1-11)

Kim K, Boyapati R, Huang J, Jin Y, Yum K and Kim E Packet coalescing exploiting data redundancy in GPGPU architectures Proceedings of the International Conference on Supercomputing, (1-10)

Li C, Mukerjee M, Andersen D, Seshan S, Kaminsky M, Porter G and Snoeren A Using Indirect Routing to Recover from Network Traffic Scheduling Estimation Error Proceedings of the Symposium on Architectures for Networking and Communications Systems, (13-24)

Carothers C, Meredith J, Blanco M, Vetter J, Mubarak M, LaPre J and Moore S Durango Proceedings of the 2017 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, (97-108)

Song W, Kim G, Jung H, Chung J, Ahn J, Lee J and Kim J (2017). History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers, ACM SIGPLAN Notices, 52:4, (765-777), Online publication date: 12-May-2017.

Song W, Kim G, Jung H, Chung J, Ahn J, Lee J and Kim J (2017). History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers, ACM SIGARCH Computer Architecture News, 45:1, (765-777), Online publication date: 11-May-2017.

Hesham S, Rettkowski J, Goehringer D and Abd El Ghany M (2017). Survey on Real-Time Networks-on-Chip, IEEE Transactions on Parallel and Distributed Systems, 28:5, (1500-1517), Online publication date: 1-May-2017.

Song W, Kim G, Jung H, Chung J, Ahn J, Lee J and Kim J History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, (765-777)

Sotiriou-Xanthopoulos E, Xydis S, Siozios K, Economakos G and Soudris D (2016). A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis, ACM Transactions on Embedded Computing Systems, 16:1, (1-26), Online publication date: 28-Feb-2017.

Erickson A, Stewart I, Navaridas J and Kiasari A (2017). The stellar transformation, Computer Networks: The International Journal of Computer and Telecommunications Networking, 113:C, (29-45), Online publication date: 11-Feb-2017.

Asaduzzaman A, Chidella K and Vardha D (2017). An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency, IEEE Transactions on Parallel and Distributed Systems, 28:2, (374-385), Online publication date: 1-Feb-2017.

Kostrzewa A, Tobuschat S, Ecco L and Ernst R Adaptive load distribution in mixed-critical Networks-on-Chip 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), (732-737)

Sheng J, Xiong Q, Yang C and Herbordt M (2017). Collective Communication on FPGA Clusters with Static Scheduling, ACM SIGARCH Computer Architecture News, 44:4, (2-7), Online publication date: 11-Jan-2017.

Song W, Jung H, Ahn J, Lee J and Kim J (2017). Evaluation of Performance Unfairness in NUMA System Architecture, IEEE Computer Architecture Letters, 16:1, (26-29), Online publication date: 1-Jan-2017.

Domke J and Hoefler T Scheduling-aware routing for supercomputers Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (1-12)

Kostrzewa A, Tobuschat S, Saidi S and Ernst R Supporting Suspension-based Locking Mechanisms for Real-Time Networks-on-chip Proceedings of the 24th International Conference on Real-Time Networks and Systems, (215-224)

Zhang G, Chiu V and Sanchez D Exploiting semantic commutativity in hardware speculation The 49th Annual IEEE/ACM International Symposium on Microarchitecture, (1-12)

Kim G, Kim C, Jeong J, Parker M and Kim J Contention-based congestion management in large-scale networks The 49th Annual IEEE/ACM International Symposium on Microarchitecture, (1-13)

Zong W and Agyeman M On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures Proceedings of the 9th International Workshop on Network on Chip Architectures, (27-32)

Yao Y and Lu Z (2016). Opportunistic competition overhead reduction for expediting critical section in NoC based CMPs, ACM SIGARCH Computer Architecture News, 44:3, (279-290), Online publication date: 12-Oct-2016.

Kostrzewa A, Ernst R and Saidi S Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, (37-46)

Xue Y and Bogdan P Scalable and realistic benchmark synthesis for efficient NoC performance evaluation Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, (1-10)

Vaish N, Ferris M and Wood D (2016). Optimization Models for Three On-Chip Network Problems, ACM Transactions on Architecture and Code Optimization, 13:3, (1-27), Online publication date: 17-Sep-2016.

Moudi M, Othman M, Lun K and Rahiman A (2016). x-Folded TM, Journal of Network and Computer Applications, 73:C, (27-34), Online publication date: 1-Sep-2016.

Chen J, Tang Y, Dong Y, Xue J, Wang Z and Zhou W (2016). Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning, IEEE Transactions on Computers, 65:8, (2588-2602), Online publication date: 1-Aug-2016.

Saponara S and Fanucci L (2016). Configurable network-on-chip router macrocells, Microprocessors & Microsystems, 45:PA, (141-150), Online publication date: 1-Aug-2016.

Wu Y, Lu C and Chen Y (2016). A survey of routing algorithm for mesh Network-on-Chip, Frontiers of Computer Science: Selected Publications from Chinese Universities, 10:4, (591-601), Online publication date: 1-Aug-2016.

Qian Z, Bogdan P, Tsui C and Marculescu R (2016). Performance Evaluation of NoC-Based Multicore Systems, ACM Transactions on Design Automation of Electronic Systems, 21:3, (1-38), Online publication date: 26-Jul-2016.

Yao Y and Lu Z Opportunistic competition overhead reduction for expediting critical section in NoC based CMPs Proceedings of the 43rd International Symposium on Computer Architecture, (279-290)

Zoni D, Flich J and Fornaciari W (2016). CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs, IEEE Transactions on Parallel and Distributed Systems, 27:6, (1603-1616), Online publication date: 1-Jun-2016.

Liu S, Chen T, Li L, Feng X, Xu Z, Chen H, Chong F and Chen Y (2016). IMR: High-Performance Low-Cost Multi-Ring NoCs, IEEE Transactions on Parallel and Distributed Systems, 27:6, (1700-1712), Online publication date: 1-Jun-2016.

Markidis S, Peng I, Iakymchuk R, Laure E, Kestor G and Gioiosa R (2016). A Performance Characterization of Streaming Computing on Supercomputers, Procedia Computer Science, 80:C, (98-107), Online publication date: 1-Jun-2016.

Domke J, Hoefler T and Matsuoka S Routing on the Dependency Graph Proceedings of the 25th ACM International Symposium on High-Performance Parallel and Distributed Computing, (3-14)

Xiong Q, Lu Z, Wu F and Xie C Real-Time Analysis for Wormhole NoC Proceedings of the 26th edition on Great Lakes Symposium on VLSI, (75-80)

Wolfe N, Carothers C, Mubarak M, Ross R and Carns P Modeling a Million-Node Slim Fly Network Using Parallel Discrete-Event Simulation Proceedings of the 2016 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, (189-199)

Werner S, Navaridas J and Luján M (2016). A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip, ACM Computing Surveys, 48:4, (1-36), Online publication date: 2-May-2016.

Wang L, Hu S, Betis G and Ranjan R (2016). A Computing Perspective on Smart City, IEEE Transactions on Computers, 65:5, (1337-1338), Online publication date: 1-May-2016.

Lotfi-Kamran P, Modarressi M and Sarbazi-Azad H (2016). An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors, IEEE Transactions on Computers, 65:5, (1656-1662), Online publication date: 1-May-2016.

Bahrami B, Jamali M and Saeidi S (2016). Proposing an optimal structure for the architecture of wireless networks on chip, Telecommunications Systems, 62:1, (199-214), Online publication date: 1-May-2016.

Jonna G, Thuniki V and Mutyam M CASCADE Proceedings of the 29th International Conference on Architecture of Computing Systems -- ARCS 2016 - Volume 9637, (35-47)

Mineo A, Palesi M, Ascia G and Catania V (2016). Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24:4, (1535-1545), Online publication date: 1-Apr-2016.

Mosayyebzadeh A, Amiraski M and Hessabi S (2016). Thermal and power aware task mapping on 3D Network on Chip, Computers and Electrical Engineering, 51:C, (157-167), Online publication date: 1-Apr-2016.

Akbar R, Safaei F and Modallalkar S (2016). A novel power efficient adaptive RED-based flow control mechanism for networks-on-chip, Computers and Electrical Engineering, 51:C, (121-138), Online publication date: 1-Apr-2016.

Sandoval-Arechiga R, Parra-Michel R, Vazquez-Avila J and Gea-Garcia B NI + Router Microarchitecture for NoC-based Communication Systems Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, (131-132)

Abdel-Khalek R and Bertacco V Correct runtime operation for NoCs through adaptive-region protection Proceedings of the 2016 Conference on Design, Automation & Test in Europe, (1189-1194)

Muralidharan D and Muthaiah R (2016). Bus Based Synchronization Method for CHIPPER Based NoC, Scientific Programming, 2016, (3), Online publication date: 1-Mar-2016.

Ren P, Ren X, Sane S, Kinsy M and Zheng N (2016). A Deadlock-Free and Connectivity-Guaranteed Methodology for Achieving Fault-Tolerance in On-Chip Networks, IEEE Transactions on Computers, 65:2, (353-366), Online publication date: 1-Feb-2016.

Kim H, Kim G, Yeo H, Kim J and Maeng S (2016). Design and Analysis of Hybrid Flow Control for Hierarchical Ring Network-on-Chip, IEEE Transactions on Computers, 65:2, (480-494), Online publication date: 1-Feb-2016.

Hesse R and Jerger N Hierarchical Clustering for On-Chip Networks Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, (1-6)

Salama N and Sllame A Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, (1-6)

Liang C and Prvulovic M (2015). MiSAR, ACM SIGARCH Computer Architecture News, 43:3S, (414-426), Online publication date: 4-Jan-2016.

Nachiappan N, Zhang H, Ryoo J, Soundararajan N, Sivasubramaniam A, Kandemir M, Iyer R and Das C (2015). VIP, ACM SIGARCH Computer Architecture News, 43:3S, (655-667), Online publication date: 4-Jan-2016.

Abdelfattah M and Betz V (2015). Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24:1, (165-177), Online publication date: 1-Jan-2016.

Wu W and Louri A (2016). A Methodology for Cognitive NoC Design, IEEE Computer Architecture Letters, 15:1, (1-4), Online publication date: 1-Jan-2016.

Gorgues M and Flich J (2016). End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance, IEEE Computer Architecture Letters, 15:1, (9-12), Online publication date: 1-Jan-2016.

Bahrebar P and Stroobandt D Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip Proceedings of the 8th International Workshop on Network on Chip Architectures, (15-20)

Seshadri V, Mullins T, Boroumand A, Mutlu O, Gibbons P, Kozuch M and Mowry T Gather-scatter DRAM Proceedings of the 48th International Symposium on Microarchitecture, (267-280)

Kannan A, Jerger N and Loh G Enabling interposer-based disintegration of multi-core processors Proceedings of the 48th International Symposium on Microarchitecture, (546-558)

Seitanidis I, Psarras A, Chrysanthou K, Nicopoulos C and Dimitrakopoulos G (2015). ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:12, (3015-3028), Online publication date: 1-Dec-2015.

Papamichael M and Hoe J (2015). The CONNECT Network-on-Chip Generator, Computer, 48:12, (72-79), Online publication date: 1-Dec-2015.

Wijekoon J and Nishi H SLRouting Proceedings of the 11th Asian Internet Engineering Conference, (1-8)

Kathareios G, Minkenberg C, Prisacari B, Rodriguez G and Hoefler T Cost-effective diameter-two topologies Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (1-11)

Jiang N, Dennison L and Dally W Network endpoint congestion control for fine-grained communication Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (1-12)

Kostrzewa A, Saidi S, Ecco L and Ernst R Flexible TDM-based resource management in on-chip networks Proceedings of the 23rd International Conference on Real Time and Networks Systems, (151-160)

Leibo Liu , Chen Wu , Chenchen Deng , Shouyi Yin , Qinghua Wu , Jie Han and Shaojun Wei (2015). A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:11, (2566-2580), Online publication date: 1-Nov-2015.

Bhowmik B, Deka J and Biswas S Reliability on Top of Best Effort Delivery Proceedings of the 8th Annual ACM India Conference, (19-28)

Hassan S, Yalamanchili S and Mukhopadhyay S Near Data Processing Proceedings of the 2015 International Symposium on Memory Systems, (11-21)

Sarjoughian H and Gholami S (2015). Action-level real-time DEVS modeling and simulation, Simulation, 91:10, (869-887), Online publication date: 1-Oct-2015.

Demir Y and Hardavellas N Parka Proceedings of the 9th International Symposium on Networks-on-Chip, (1-8)

Runge A Fault-tolerant Network-on-Chip based on Fault-aware Flits and Deflection Routing Proceedings of the 9th International Symposium on Networks-on-Chip, (1-8)

Liu S, Lu Z and Jantsch A Highway in TDM NoCs Proceedings of the 9th International Symposium on Networks-on-Chip, (1-8)

Xue Y and Bogdan P User Cooperation Network Coding Approach for NoC Performance Improvement Proceedings of the 9th International Symposium on Networks-on-Chip, (1-8)

Zong W, Agyemen M, Wang X and Maky T Unbiased Regional Congestion Aware Selection Function for NoCs Proceedings of the 9th International Symposium on Networks-on-Chip, (1-8)

Costa P, Ballani H, Razavi K and Kash I (2015). R2C2, ACM SIGCOMM Computer Communication Review, 45:4, (551-564), Online publication date: 22-Sep-2015.

Pellauer M, Parashar A, Adler M, Ahsan B, Allmon R, Crago N, Fleming K, Gambhir M, Jaleel A, Krishna T, Lustig D, Maresh S, Pavlov V, Rayess R, Zhai A and Emer J (2015). Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures, ACM Transactions on Computer Systems, 33:3, (1-32), Online publication date: 11-Sep-2015.

Zhiliang Qian , Abbas S and Chi-Ying Tsui (2015). FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:9, (1854-1867), Online publication date: 1-Sep-2015.

Kyungsu Kang , Benini L and De Micheli G (2015). Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:9, (1828-1841), Online publication date: 1-Sep-2015.

Dalvandi A, Gurusamy M and Kee Chaing Chua (2015). Time-Aware VMFlow Placement, Routing, and Migration for Power Efficiency in Data Centers, IEEE Transactions on Network and Service Management, 12:3, (349-362), Online publication date: 1-Sep-2015.

Gomes A, Alves F, Ferreira R and Nacif J Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, (1-7)

Wijekoon J, Tennekoon R, Harahap E and Nishi H Introducing a distance vector routing protocol for ns-3 simulator Proceedings of the 8th International Conference on Simulation Tools and Techniques, (38-46)

Chaurasia A and Sehgal V (2015). Optimal buffer-size by synthetic self-similar traces for different traffics for NoC, ACM SIGBED Review, 12:3, (6-12), Online publication date: 17-Aug-2015.

Costa P, Ballani H, Razavi K and Kash I R2C2 Proceedings of the 2015 ACM Conference on Special Interest Group on Data Communication, (551-564)

Shaoli Liu , Tianshi Chen , Ling Li , Xi Li , Mingzhe Zhang , Chao Wang , Haibo Meng , Xuehai Zhou and Yunji Chen (2015). FreeRider: Non-Local Adaptive Network-on-Chip Routing with Packet-Carried Propagation of Congestion Information, IEEE Transactions on Parallel and Distributed Systems, 26:8, (2272-2285), Online publication date: 1-Aug-2015.

Fujiwara I, Koibuchi M, Matsutani H and Casanova H (2015). Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects, IEEE Transactions on Parallel and Distributed Systems, 26:7, (2051-2060), Online publication date: 1-Jul-2015.

Naruko T and Hiraki K FOLCS Proceedings of the 3rd International Workshop on Many-core Embedded Systems, (25-32)

Liang C and Prvulovic M MiSAR Proceedings of the 42nd Annual International Symposium on Computer Architecture, (414-426)

Nachiappan N, Zhang H, Ryoo J, Soundararajan N, Sivasubramaniam A, Kandemir M, Iyer R and Das C VIP Proceedings of the 42nd Annual International Symposium on Computer Architecture, (655-667)

Jiang W, Bhardwaj K, Lacourba G and Nowick S A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's Proceedings of the 52nd Annual Design Automation Conference, (1-6)

Xueqian Zhao and Zhonghai Lu (2015). Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34:6, (986-999), Online publication date: 1-Jun-2015.

Xu Y, Zhao B, Zhang Y and Yang J (2015). Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers, ACM Transactions on Parallel Computing, 2:1, (1-23), Online publication date: 21-May-2015.

Psathakis A, Papaefstathiou V, Chrysos N, Chaix F, Vasilakis E, Pnevmatikatos D and Katevenis M A Systematic Evaluation of Emerging Mesh-like CMP NoCs Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, (159-170)

Acı Ç and Akay M (2015). A hybrid congestion control algorithm for broadcast-based architectures with multiple input queues, The Journal of Supercomputing, 71:5, (1907-1931), Online publication date: 1-May-2015.

Li Z, Goswami N and Li T (2015). iConn, ACM Journal on Emerging Technologies in Computing Systems, 11:4, (1-23), Online publication date: 27-Apr-2015.

Xiaowen Wu , Jiang Xu , Yaoyao Ye , Xuan Wang , Nikdast M, Zhehui Wang and Zhe Wang (2015). An Inter/Intra-Chip Optical Network for Manycore Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:4, (678-691), Online publication date: 1-Apr-2015.

Guoyue Jiang , Zhaolin Li , Fang Wang and Shaojun Wei (2015). A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:4, (664-677), Online publication date: 1-Apr-2015.

Peng Zhang , Yuefan Deng , Rui Feng , Xingguo Luo and Jiangxing Wu (2015). Evaluation of Various Networks Configurated by Adding Bypass or Torus Links, IEEE Transactions on Parallel and Distributed Systems, 26:4, (984-996), Online publication date: 1-Apr-2015.

Azizi S, Safaei F and Roozikhar M (2015). A fault-tolerant routing algorithm in HyperX topology based on unsafety vectors, The Journal of Supercomputing, 71:4, (1224-1248), Online publication date: 1-Apr-2015.

Mirhosseini A, Sadrosadati M, Fakhrzadehgan A, Modarressi M and Sarbazi-Azad H An energy-efficient virtual channel power-gating mechanism for on-chip networks Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (1527-1532)

Zhu D, Chen L, Pinkston T and Pedram M TAPP Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (1241-1244)

Mazloumi A and Modarressi M A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (908-911)

Bishnoi R, Laxmi V, Gaur M and Flich J d2-LBDR Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (800-805)

Karkar A, Tong K, Mak T and Yakovlev A Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (794-799)

Van Laer A, Ellawala C, Madarbux M, Watts P and Jones T Coherence based message prediction for optically interconnected chip multiprocessors Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (613-616)

Chen C, Enachescu M and Cotofana S Enabling vertical wormhole switching in 3D NoC-bus hybrid systems Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, (507-512)

Michalewicz M, Orlowski L and Deng Y (2015). Creating interconnect topologies by algorithmic edge removal, Supercomputing Frontiers and Innovations: an International Journal, 2:4, (16-47), Online publication date: 1-Mar-2015.

Minghua Tang , Xiaola Lin and Palesi M (2015). Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm, IEEE Transactions on Parallel and Distributed Systems, 26:3, (891-901), Online publication date: 1-Mar-2015.

Sheng Ma , Zhiying Wang , Zonglin Liu and Jerger N (2015). Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs, IEEE Transactions on Computers, 64:3, (763-777), Online publication date: 1-Mar-2015.

Abdelfattah M, Bitar A and Betz V Take the Highway Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, (98-107)

Minghua Tang , Xiaola Lin and Palesi M (2015). An Offline Method for Designing Adaptive Routing Based on Pressure Model, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34:2, (307-320), Online publication date: 1-Feb-2015.

Mihajlovic M, Bongo A, Ciegis R, Frasheri N, Kimovski D, Kropf P, Margenov S, Neytcheva M, Rauber T, Runger G, Trobec R, Wuyts R, Wyrzykowski R and Gong J (2015). Applications for ultrascale computing, Supercomputing Frontiers and Innovations: an International Journal, 2:1, (19-48), Online publication date: 3-Jan-2015.

Chen X, Lu Z, Jantsch A, Chen S, Guo Y, Chen S and Chen H (2015). Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications, Journal of Electrical and Computer Engineering, 2015, (22-22), Online publication date: 1-Jan-2015.

Zhongqi Li , Qouneh A, Joshi M, Wangyuan Zhang , Xin Fu and Tao Li (2015). Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:1, (170-183), Online publication date: 1-Jan-2015.

Jose J, Jacob B and Kamal H An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers Proceedings of the 2014 International Workshop on Network on Chip Architectures, (31-36)

Han S, Lee J and Choi K Tree-Mesh Heterogeneous Topology for Low-Latency NoC Proceedings of the 2014 International Workshop on Network on Chip Architectures, (19-24)

Kayiran O, Nachiappan N, Jog A, Ausavarungnirun R, Kandemir M, Loh G, Mutlu O and Das C Managing GPU Concurrency in Heterogeneous Architectures Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, (114-126)

Chen Y, Luo T, Liu S, Zhang S, He L, Wang J, Li L, Chen T, Xu Z, Sun N and Temam O DaDianNao Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, (609-622)

Kim G, Lee M, Jeong J and Kim J Multi-GPU System Design with Memory Networks Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, (484-495)

Jeloka S, Das R, Dreslinski R, Mudge T and Blaauw D Hi-Rise Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, (471-483)

Yang H, Tripathi J, Jerger N and Gibson D Dodec Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, (496-508)

Mubarak M, Carothers C, Ross R and Carns P Using massively parallel simulation for MPI collective communication modeling in extreme-scale networks Proceedings of the 2014 Winter Simulation Conference, (3107-3118)

Besta M and Hoefler T Slim fly Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (348-359)

Song W, Kim J, Lee J and Abts D Security Vulnerability in Processor-Interconnect Router Design Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security, (358-368)

Chrysos N, Neeser F, Vanderpool B, Rudquist M, Valk K, Greenfield T and Basso C Integration and QoS of multicast traffic in a server-rack fabric with 640 100g ports Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, (113-124)

Siokis A, Christodoulopoulos K and Varvarigos E Laying out interconnects on optical printed circuit boards Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, (101-112)

Bitar A, Cassidy J, Enright Jerger N and Betz V Efficient and programmable ethernet switching with a NoC-enhanced FPGA Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, (89-100)

Badr M and Jerger N (2014). SynFull, ACM SIGARCH Computer Architecture News, 42:3, (109-120), Online publication date: 16-Oct-2014.

Towles B, Grossman J, Greskamp B and Shaw D (2014). Unifying on-chip and inter-node switching within the Anton 2 network, ACM SIGARCH Computer Architecture News, 42:3, (1-12), Online publication date: 16-Oct-2014.

Daryin A and Korzh A (2014). Early evaluation of direct large-scale InfiniBand networks with adaptive routing, Supercomputing Frontiers and Innovations: an International Journal, 1:3, (56-69), Online publication date: 12-Oct-2014.

Ancajas D, Chakraborty K, Roy S and Allred J Tackling QoS-induced aging in exascale systems through agile path selection Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, (1-10)

Panić M, Quiñones E, Zaykov P, Hernandez C, Abella J and Cazorla F Parallel many-core avionics systems Proceedings of the 14th International Conference on Embedded Software, (1-10)

Diguet J Self-Adaptive Network On Chips Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, (1-6)

Fu W, Chen T, Wang C and Liu L (2014). Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems, The Journal of Supercomputing, 69:3, (1491-1516), Online publication date: 1-Sep-2014.

Villar J, Andújar F, Alfaro F, Sánchez J and Duato J (2014). Formalization and configuration methodology for high-radix combined switches, The Journal of Supercomputing, 69:3, (1410-1444), Online publication date: 1-Sep-2014.

Tavakkol A, Arjomand M and Sarbazi-Azad H Design for scalability in enterprise SSDs Proceedings of the 23rd international conference on Parallel architectures and compilation, (417-430)

Valad Beigi M and Memik G MIN Proceedings of the 2014 international symposium on Low power electronics and design, (299-302)

Demir Y and Hardavellas N EcoLaser Proceedings of the 2014 international symposium on Low power electronics and design, (3-8)

Jose J and Mutyam M (2014). Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs, ACM Transactions on Design Automation of Electronic Systems, 19:4, (1-22), Online publication date: 1-Aug-2014.

Yang Y, Kumar R, Choi G and Gratz P (2014). WaveSync, ACM Transactions on Design Automation of Electronic Systems, 19:4, (1-22), Online publication date: 1-Aug-2014.

Tsai K, Chen H and Lin Y (2014). Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing, ACM Transactions on Design Automation of Electronic Systems, 19:4, (1-21), Online publication date: 1-Aug-2014.

Abdelfattah M and Betz V (2014). Networks-on-Chip for FPGAs, ACM Transactions on Reconfigurable Technology and Systems, 7:3, (1-22), Online publication date: 1-Aug-2014.

Swaminathan K, Lakshminarayanan G and Ko S (2014). Design and verification of an efficient WISHBONE-based network interface for network on chip, Computers and Electrical Engineering, 40:6, (1838-1857), Online publication date: 1-Aug-2014.

Qi H, Shiraz M, Gani A, Whaiduzzaman M and Khan S (2014). Sierpinski triangle based data center architecture in cloud computing, The Journal of Supercomputing, 69:2, (887-907), Online publication date: 1-Aug-2014.

Furhad M and Kim J (2014). A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures, The Journal of Supercomputing, 69:2, (766-792), Online publication date: 1-Aug-2014.

Prisacari B, Rodriguez G, Heidelberger P, Chen D, Minkenberg C and Hoefler T Efficient task placement and routing of nearest neighbor exchanges in dragonfly networks Proceedings of the 23rd international symposium on High-performance parallel and distributed computing, (129-140)

Badr M and Jerger N SynFull Proceeding of the 41st annual international symposium on Computer architecuture, (109-120)

Towles B, Grossman J, Greskamp B and Shaw D Unifying on-chip and inter-node switching within the Anton 2 network Proceeding of the 41st annual international symposium on Computer architecuture, (1-12)

Demir Y, Pan Y, Song S, Hardavellas N, Kim J and Memik G Galaxy Proceedings of the 28th ACM international conference on Supercomputing, (303-312)

Michelogiannakis G, Williams A, Williams S and Shalf J Collective memory transfers for multi-core chips Proceedings of the 28th ACM international conference on Supercomputing, (343-352)

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Dally W and Balfour J Author retrospective for design tradeoffs for tiled CMP on-chip networks ACM International Conference on Supercomputing 25th Anniversary Volume, (77-79)

Rao S, Jeloka S, Das R, Blaauw D, Dreslinski R and Mudge T VIX Proceedings of the 51st Annual Design Automation Conference, (1-6)

Navaridas J, Luján M, Plana L, Temple S and Furber S On generating multicast routes for SpiNNaker Proceedings of the 11th ACM Conference on Computing Frontiers, (1-10)

Sleeba S, Jose J and M.G. M WeDBless Proceedings of the 24th edition of the great lakes symposium on VLSI, (77-78)

Ortín-Obón M, Ramini L, Tatenguem Fankem H, Viñals V and Bertozzi D A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip Proceedings of the 24th edition of the great lakes symposium on VLSI, (267-272)

Mubarak M, Carothers C, Ross R and Carns P A case study in using massively parallel simulation for extreme-scale torus network codesign Proceedings of the 2nd ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, (27-38)

Wu X, Xu J, Ye Y, Wang Z, Nikdast M and Wang X (2014). SUOR, ACM Journal on Emerging Technologies in Computing Systems, 10:4, (1-25), Online publication date: 1-May-2014.

Grissom D, Curtis C and Brisk P (2014). Interpreting Assays with Control Flow on Digital Microfluidic Biochips, ACM Journal on Emerging Technologies in Computing Systems, 10:3, (1-30), Online publication date: 1-Apr-2014.

Jonna G, Jose J, Radhakrishnan R and Mutyam M Minimally buffered single-cycle deflection router Proceedings of the conference on Design, Automation & Test in Europe, (1-4)

Lee D, Parikh R and Bertacco V Brisk and limited-impact NoC routing reconfiguration Proceedings of the conference on Design, Automation & Test in Europe, (1-6)

Karkar A, Dahir N, Al-Dujaily R, Tong K, Mak T and Yakovlev A Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip Proceedings of the conference on Design, Automation & Test in Europe, (1-4)

Zhao X and Lu Z Empowering study of delay bound tightness with simulated annealing Proceedings of the conference on Design, Automation & Test in Europe, (1-6)

Bahrebar P and Stroobandt D Improving hamiltonian-based routing methods for on-chip networks Proceedings of the conference on Design, Automation & Test in Europe, (1-4)

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Oveis-Gharan M and Khan G Power and chip-area aware network-on-chip modeling for system on chip simulation Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques, (178-185)

Abdel-Khalek R and Bertacco V (2014). Post-silicon platform for the functional diagnosis and debug of networks-on-chip, ACM Transactions on Embedded Computing Systems, 13:3s, (1-25), Online publication date: 1-Mar-2014.

Jin Y and Pinkston T (2014). PAIS, ACM Transactions on Embedded Computing Systems, 13:3s, (1-21), Online publication date: 1-Mar-2014.

Parikh R and Bertacco V (2014). ForEVeR, ACM Transactions on Embedded Computing Systems, 13:3s, (1-30), Online publication date: 1-Mar-2014.

Fu W, Liu L and Chen T (2014). Direct distributed memory access for CMPs, Journal of Parallel and Distributed Computing, 74:2, (2109-2122), Online publication date: 1-Feb-2014.

Prisacari B, Rodriguez G, Garcia M, Vallejo E, Beivide R and Minkenberg C Performance implications of remote-only load balancing under adversarial traffic in Dragonflies Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, (1-4)

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Al-Dujaily R, Dahir N, Mak T, Xia F and Yakovlev A (2013). Dynamic programming-based runtime thermal management (DPRTM), ACM Transactions on Design Automation of Electronic Systems, 19:1, (1-27), Online publication date: 1-Dec-2013.

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Navaridas J, Furber S, Garside J, Jin X, Khan M, Lester D, Luján M, Miguel-Alonso J, Painkras E, Patterson C, Plana L, Rast A, Richards D, Shi Y, Temple S, Wu J and Yang S (2013). SpiNNaker, Parallel Computing, 39:11, (693-708), Online publication date: 1-Nov-2013.

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Lee J, Li S, Kim H and Yalamanchili S (2013). Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures, ACM Transactions on Design Automation of Electronic Systems, 18:4, (1-28), Online publication date: 1-Oct-2013.

Crisan D, Birke R, Cressier G, Minkenberg C and Gusat M (2013). Got loss? Get zOVN!, ACM SIGCOMM Computer Communication Review, 43:4, (423-434), Online publication date: 19-Sep-2013.

Zhang Y, Qu P, Qian Z, Wang H and Zheng W Software/Hardware Hybrid Network-on-Chip Simulation on FPGA Proceedings of the 10th IFIP International Conference on Network and Parallel Computing - Volume 8147, (167-178)

Ahn J, Son Y and Kim J (2013). Scalable high-radix router microarchitecture using a network switch organization, ACM Transactions on Architecture and Code Optimization, 10:3, (1-25), Online publication date: 16-Sep-2013.

Bakhoda A, Kim J and Aamodt T (2013). Designing on-chip networks for throughput accelerators, ACM Transactions on Architecture and Code Optimization, 10:3, (1-35), Online publication date: 16-Sep-2013.

Li Z and Li T ESPN Proceedings of the 2013 International Symposium on Low Power Electronics and Design, (377-382)

Lugones D, Christodoulopoulos K, Katrinis K, Ruffini M, O'Mahony D and Collier M Accelerating communication-intensive parallel workloads using commodity optical switches and a software-configurable control stack Proceedings of the 19th international conference on Parallel Processing, (713-724)

Bogdański B, Johnsen B, Reinemo S and Flich J Making the network scalable Proceedings of the 19th international conference on Parallel Processing, (685-698)

Crisan D, Birke R, Cressier G, Minkenberg C and Gusat M Got loss? Get zOVN! Proceedings of the ACM SIGCOMM 2013 conference on SIGCOMM, (423-434)

Stanley-Marbell P (2013). L24, ACM Transactions on Embedded Computing Systems, 13:1, (1-27), Online publication date: 1-Aug-2013.

Tang P, Park J, Kim D and Petrov V (2013). A framework for low-communication 1-D FFT, Scientific Programming, 21:3-4, (181-195), Online publication date: 1-Jul-2013.

Wassel H, Gao Y, Oberg J, Huffmire T, Kastner R, Chong F and Sherwood T (2013). SurfNoC, ACM SIGARCH Computer Architecture News, 41:3, (583-594), Online publication date: 26-Jun-2013.

Das R, Narayanasamy S, Satpathy S and Dreslinski R (2013). Catnap, ACM SIGARCH Computer Architecture News, 41:3, (320-331), Online publication date: 26-Jun-2013.

Wassel H, Gao Y, Oberg J, Huffmire T, Kastner R, Chong F and Sherwood T SurfNoC Proceedings of the 40th Annual International Symposium on Computer Architecture, (583-594)

Das R, Narayanasamy S, Satpathy S and Dreslinski R Catnap Proceedings of the 40th Annual International Symposium on Computer Architecture, (320-331)

Wang R, Chen L and Pinkston T Bubble coloring Proceedings of the 27th international ACM conference on International conference on supercomputing, (193-202)

Zahavi E, Cidon I and Kolodny A (2013). Gana, ACM Transactions on Embedded Computing Systems, 12:4, (1-20), Online publication date: 1-Jun-2013.

Dally W, Malachowsky C and Keckler S 21st century digital design tools Proceedings of the 50th Annual Design Automation Conference, (1-6)

Zhan J, Stoimenov N, Ouyang J, Thiele L, Narayanan V and Xie Y Designing energy-efficient NoC for real-time embedded systems through slack optimization Proceedings of the 50th Annual Design Automation Conference, (1-6)

Li K (2013). CusNoC, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21:4, (692-705), Online publication date: 1-Apr-2013.

Park S, Qazi M, Peh L and Chandrakasan A 40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS Proceedings of the Conference on Design, Automation and Test in Europe, (1637-1642)

Jose J, Nayak B, Kumar K and Mutyam M DeBAR Proceedings of the Conference on Design, Automation and Test in Europe, (1583-1588)

Qian Z, Juan D, Bogdan P, Tsui C, Marculescu D and Marculescu R SVR-NoC Proceedings of the Conference on Design, Automation and Test in Europe, (354-357)

Chen C, Park S, Krishna T, Subramanian S, Chandrakasan A and Peh L SMART Proceedings of the Conference on Design, Automation and Test in Europe, (338-343)

Misler M and Jerger N (2013). Moths, ACM Transactions on Embedded Computing Systems, 12:1s, (1-22), Online publication date: 1-Mar-2013.

Bunker T and Swanson S A latency-optimized hybrid network for clustering FPGAs (abstract only) Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (266-266)

Kinsy M, Pellauer M and Devadas S Heracles Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (125-134)

Saeedi M and Markov I (2013). Synthesis and optimization of reversible circuits—a survey, ACM Computing Surveys, 45:2, (1-34), Online publication date: 1-Feb-2013.

Jokanovic A, Prisacari B, Rodriguez G and Minkenberg C Randomizing task placement does not randomize traffic (enough) Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, (9-12)

Prolonge R and Clermidy F Network-on-chip traffic modeling for data flow applications Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, (1-6)

Bhardwaj V and Nitin N (2013). Message broadcasting via a new fault tolerant irregular advance omega network in faulty and nonfaulty network environments, Journal of Electrical and Computer Engineering, 2013, (6-6), Online publication date: 1-Jan-2013.

Stephens B, Cox A, Felter W, Dixon C and Carter J PAST Proceedings of the 8th international conference on Emerging networking experiments and technologies, (49-60)

Mische J and Ungerer T Low power flitwise routing in an unidirectional torus with minimal buffering Proceedings of the Fifth International Workshop on Network on Chip Architectures, (63-68)

Park H and Choi K Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips Proceedings of the Fifth International Workshop on Network on Chip Architectures, (51-56)

Badri S, Holsmark R and Kumar S Junction based routing Proceedings of the Fifth International Workshop on Network on Chip Architectures, (45-50)

Karkar A, Al-Dujaily R, Yakovlev A, Tong K and Mak T Surface wave communication system for on-chip and off-chip interconnects Proceedings of the Fifth International Workshop on Network on Chip Architectures, (11-16)

Sharifi A, Kultursay E, Kandemir M and Das C Addressing End-to-End Memory Access Latency in NoC-Based Multicores Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, (294-304)

Chen L and Pinkston T NoRD Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, (270-281)

Tang P, Park J, Kim D and Petrov V A framework for low-communication 1-D FFT Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, (1-12)

Jose J, Mahathi K, Shankar J and Mutyam M TRACKER Proceedings of the International Conference on Computer-Aided Design, (564-568)

Abdel-Khalek R and Bertacco V Functional post-silicon diagnosis and debug for networks-on-chip Proceedings of the International Conference on Computer-Aided Design, (557-563)

Ramanujam R and Lin B (2012). Randomized partially-minimal routing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20:11, (2080-2093), Online publication date: 1-Nov-2012.

Hong S, Oguntebi T, Casper J, Bronson N, Kozyrakis C and Olukotun K A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (513-520)

Salas M and Pasricha S The roce-bush router Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (171-180)

Wu X, Turner D, Chen C, Maltz D, Yang X, Yuan L and Zhang M (2012). NetPilot, ACM SIGCOMM Computer Communication Review, 42:4, (419-430), Online publication date: 24-Sep-2012.

Nychis G, Fallin C, Moscibroda T, Mutlu O and Seshan S (2012). On-chip networks from a networking perspective, ACM SIGCOMM Computer Communication Review, 42:4, (407-418), Online publication date: 24-Sep-2012.

Wang L, Kumar P, Yum K and Kim E APCR Proceedings of the 21st international conference on Parallel architectures and compilation techniques, (87-96)

Koibuchi M, Matsutani H, Amano H, Hsu D and Casanova H (2012). A case for random shortcut topologies for HPC interconnects, ACM SIGARCH Computer Architecture News, 40:3, (177-188), Online publication date: 5-Sep-2012.

Koka P, McCracken M, Schwetman H, Chen C, Zheng X, Ho R, Raj K and Krishnamoorthy A (2012). A micro-architectural analysis of switched photonic multi-chip interconnects, ACM SIGARCH Computer Architecture News, 40:3, (153-164), Online publication date: 5-Sep-2012.

Sayed M, Shalaby A, El-Sayed M and Goulart V (2012). Flexible router architecture for network-on-chip, Computers & Mathematics with Applications, 64:5, (1301-1310), Online publication date: 1-Sep-2012.

Garzón D, Gómez C, Gómez M, López P and Duato J Towards an efficient fat-tree like topology Proceedings of the 18th international conference on Parallel Processing, (716-728)

Varvello M, Perino D and Esteban J Caesar Proceedings of the second edition of the ICN workshop on Information-centric networking, (73-78)

Wu X, Turner D, Chen C, Maltz D, Yang X, Yuan L and Zhang M NetPilot Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication, (419-430)

Nychis G, Fallin C, Moscibroda T, Mutlu O and Seshan S On-chip networks from a networking perspective Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication, (407-418)

Compositional performance verification of NoC designs Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, (1-10)

Koibuchi M, Matsutani H, Amano H, Hsu D and Casanova H A case for random shortcut topologies for HPC interconnects Proceedings of the 39th Annual International Symposium on Computer Architecture, (177-188)

Koka P, McCracken M, Schwetman H, Chen C, Zheng X, Ho R, Raj K and Krishnamoorthy A A micro-architectural analysis of switched photonic multi-chip interconnects Proceedings of the 39th Annual International Symposium on Computer Architecture, (153-164)

Ben-Itzhak Y, Cidon I and Kolodny A Optimizing heterogeneous NoC design Proceedings of the International Workshop on System Level Interconnect Prediction, (32-39)

Park S, Krishna T, Chen C, Daya B, Chandrakasan A and Peh L Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI Proceedings of the 49th Annual Design Automation Conference, (398-405)

Kahng A, Lin B and Nath S Explicit modeling of control and data for improved NoC router estimation Proceedings of the 49th Annual Design Automation Conference, (392-397)

Singh P, Narayanan V and Landis D (2012). Targeted random test generation for power-aware multicore designs, ACM Transactions on Design Automation of Electronic Systems, 17:3, (1-19), Online publication date: 1-Jun-2012.

Lankes A, Wild T, Wallentowitz S and Herkersdorf A (2012). Benefits of selective packet discard in networks-on-chip, ACM Transactions on Architecture and Code Optimization, 9:2, (1-21), Online publication date: 1-Jun-2012.

Abts D and Felderman B (2012). A guided tour of data-center networking, Communications of the ACM, 55:6, (44-51), Online publication date: 1-Jun-2012.

Palumbo F, Pani D, Congiu A and Raffo L Concurrent hybrid switching for massively parallel systems-on-chip Proceedings of the 9th conference on Computing Frontiers, (173-182)

Sem-Jacobsen F and Lysne O Topology Agnostic Dynamic Quick Reconfiguration for Large-Scale Interconnection Networks Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012), (228-235)

Grissom D and Brisk P A high-performance online assay interpreter for digital microfluidic biochips Proceedings of the great lakes symposium on VLSI, (103-106)

Abts D and Felderman B (2012). A Guided Tour through Data-center Networking, Queue, 10:5, (10-23), Online publication date: 1-May-2012.

Gholami S and Sarjoughian H Real-time network-on-chip simulation modeling Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques, (103-112)

Chao H, Chen Y, Tung S, Hsiung P and Chen S Congestion-aware scheduling for NoC-based reconfigurable systems Proceedings of the Conference on Design, Automation and Test in Europe, (1561-1566)

Ray S and Brayton R Scalable progress verification in credit-based flow-control systems Proceedings of the Conference on Design, Automation and Test in Europe, (905-910)

Bhardwaj K, Chakraborty K and Roy S An MILP-based aging-aware routing algorithm for NoCs Proceedings of the Conference on Design, Automation and Test in Europe, (326-331)

Dai Z and Zhu J Saturating the transceiver bandwidth Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, (67-76)

Papamichael M and Hoe J CONNECT Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, (37-46)

Oxman G, Weiss S and Birk Y Buffered deflection routing for networks-on-chip Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, (9-12)

Wang X, Yu Z and Xu H A simple and efficient input selection function for networks-on-chip Proceedings of the 13th international conference on Distributed Computing and Networking, (525-539)

Rantala V, Liljeberg P and Plosila J (2012). Status data and communication aspects in dynamically clustered network-on-chip monitoring, Journal of Electrical and Computer Engineering, 2012, (4-4), Online publication date: 1-Jan-2012.

Huang P and Hwang W (2012). Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks, Journal of Electrical and Computer Engineering, 2012, (1-1), Online publication date: 1-Jan-2012.

Kumar A, Kumar M, Murali S, Kamakoti V, Benini L and De Micheli G (2012). A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands, Journal of Electrical and Computer Engineering, 2012, (5-5), Online publication date: 1-Jan-2012.

Tsai W, Lan Y, Hu Y and Chen S (2012). Networks on chips: structure and design methodologies, Journal of Electrical and Computer Engineering, 2012, (2-2), Online publication date: 1-Jan-2012.

Savva A, Theocharides T and Soteriou V (2012). Intelligent on/off dynamic link management for on-chip networks, Journal of Electrical and Computer Engineering, 2012, (6-6), Online publication date: 1-Jan-2012.

Matos D, Palermo G, Zaccaria V, Reinbrecht C, Susin A, Silvano C and Carro L Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip Proceedings of the 4th International Workshop on Network on Chip Architectures, (31-36)

Jose J, Shankar J, Mahathi K, Kumar D and Mutyam M BOFAR Proceedings of the 4th International Workshop on Network on Chip Architectures, (23-28)

Parikh R and Bertacco V Formally enhanced runtime verification to ensure NoC functional correctness Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, (410-419)

Abdel-Gawad A and Thottethodi M TransCom Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, (237-247)

Pan Y, Kim J and Memik G FeatherWeight Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, (105-116)

Michelogiannakis G, Jiang N, Becker D and Dally W Packet chaining Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, (83-94)

Krishna T, Peh L, Beckmann B and Reinhardt S Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, (71-82)

Wu Y, Min G, Ould-Khaoua M and Yin H (2011). Modelling and analysis of pipelined circuit switching in interconnection networks with bursty traffic and hot-spot destinations, Journal of Systems and Software, 84:12, (2097-2106), Online publication date: 1-Dec-2011.

Chen C, Park S, Krishna T and Peh L A low-swing crossbar and link generator for low-power networks-on-chip Proceedings of the International Conference on Computer-Aided Design, (779-786)

Shafiee A, Zolghadr M, Arjomand M and Sarbazi-Azad H Application-aware deadlock-free oblivious routing based on extended turn-model Proceedings of the International Conference on Computer-Aided Design, (213-218)

Stuart M, Stensgaard M and Sparsø J (2011). The ReNoC Reconfigurable Network-on-Chip, ACM Transactions on Embedded Computing Systems, 10:4, (1-26), Online publication date: 1-Nov-2011.

Krishnaiah G, Silpa B, Panda P and Kumar A Exploiting temporal decoupling to accelerate trace-driven NoC emulation Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (315-324)

Diemer J, Rox J, Negrean M, Stein S and Ernst R Real-time communication analysis for networks with two-stage arbitration Proceedings of the ninth ACM international conference on Embedded software, (243-252)

Pappas V and Verma D (2011). Self-organizing systems based on morphogenesis principles, IBM Journal of Research and Development, 55:5, (561-569), Online publication date: 1-Sep-2011.

Pineda-Villavicencio G (2011). Non-existence of bipartite graphs of diameter at least 4 and defect 2, Journal of Algebraic Combinatorics: An International Journal, 34:2, (163-182), Online publication date: 1-Sep-2011.

Udipi A, Muralimanohar N, Balasubramonian R, Davis A and Jouppi N (2011). Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems, ACM SIGARCH Computer Architecture News, 39:3, (425-436), Online publication date: 22-Jun-2011.

Ma S, Enright Jerger N and Wang Z (2011). DBAR, ACM SIGARCH Computer Architecture News, 39:3, (413-424), Online publication date: 22-Jun-2011.

Grot B, Hestness J, Keckler S and Mutlu O (2011). Kilo-NOC, ACM SIGARCH Computer Architecture News, 39:3, (401-412), Online publication date: 22-Jun-2011.

Mishra A, Vijaykrishnan N and Das C (2011). A case for heterogeneous on-chip interconnects for CMPs, ACM SIGARCH Computer Architecture News, 39:3, (389-400), Online publication date: 22-Jun-2011.

Fu B, Han Y, Ma J, Li H and Li X (2011). An abacus turn model for time/space-efficient reconfigurable routing, ACM SIGARCH Computer Architecture News, 39:3, (259-270), Online publication date: 22-Jun-2011.

Borovska P and Ivanova D Communication performance of a recirculative omega high-speed system area network for HPC Proceedings of the 12th International Conference on Computer Systems and Technologies, (491-497)

Mudigonda J, Yalagandula P and Mogul J Taming the flying cable monster Proceedings of the 3rd USENIX conference on Hot topics in cloud computing, (25-25)

Carrillo S, Harkin J, McDaid L, Pande S, Cawley S and Morgan F Adaptive routing strategies for large scale spiking neural network hardware implementations Proceedings of the 21th international conference on Artificial neural networks - Volume Part I, (77-84)

Walter I, Kantor E, Cidon I and Kutten S Capacity optimized NoC for multi-mode SoC Proceedings of the 48th Design Automation Conference, (942-947)

Kim G, Kim J and Yoo S FlexiBuffer Proceedings of the 48th Design Automation Conference, (936-941)

Udipi A, Muralimanohar N, Balasubramonian R, Davis A and Jouppi N Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems Proceedings of the 38th annual international symposium on Computer architecture, (425-436)

Ma S, Enright Jerger N and Wang Z DBAR Proceedings of the 38th annual international symposium on Computer architecture, (413-424)

Grot B, Hestness J, Keckler S and Mutlu O Kilo-NOC Proceedings of the 38th annual international symposium on Computer architecture, (401-412)

Mishra A, Vijaykrishnan N and Das C A case for heterogeneous on-chip interconnects for CMPs Proceedings of the 38th annual international symposium on Computer architecture, (389-400)

Fu B, Han Y, Ma J, Li H and Li X An abacus turn model for time/space-efficient reconfigurable routing Proceedings of the 38th annual international symposium on Computer architecture, (259-270)

Cianchetti M and Albonesi D (2011). A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors, ACM Journal on Emerging Technologies in Computing Systems, 7:2, (1-20), Online publication date: 1-Jun-2011.

Xu Y, Du Y, Zhang Y and Yang J A composite and scalable cache coherence protocol for large scale CMPs Proceedings of the international conference on Supercomputing, (285-294)

Palumbo F, Pani D, Deidda A and Raffo L Towards self-adaptive networks on chip for massively parallel processors Proceedings of the 8th ACM International Conference on Computing Frontiers, (1-2)

Kapadia N and Pasricha S VISION Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, (31-36)

Gill G, Attarde S, Lacourba G and Nowick S A low-latency adaptive asynchronous interconnection network using bi-modal router nodes Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (193-200)

Nitta C, Farrens M, Macdonald K and Akella V Inferring packet dependencies to improve trace based simulation of on-chip networks Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (153-160)

Wang D, Jerger N and Steffan J DART Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (145-152)

Papamichael M, Hoe J and Mutlu O FIST Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (137-144)

Ababei C, Kia H, Yadav O and Hu J Energy and reliability oriented mapping for regular Networks-on-Chip Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (121-128)

Kao Y and Chao H BLOCON Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (81-88)

Grange M, Weerasekera R, Pamunuwa D, Jantsch A and Weldezion A Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (57-64)

Matsutani H, Take Y, Sasaki D, Kimura M, Ono Y, Nishiyama Y, Koibuchi M, Kuroda T and Amano H A vertical bubble flow network using inductive-coupling for 3-D CMPs Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (49-56)

Joshi A and Mutyam M Prevention flow-control for low latency torus Networks-on-Chip Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (41-48)

Cho M, Shim K, Lis M, Khan O and Devadas S Deadlock-free fine-grained thread migration Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (33-40)

Alfaraj N, Zhang J, Xu Y and Chao H HOPE Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (17-24)

Greenberg A, Hamilton J, Jain N, Kandula S, Kim C, Lahiri P, Maltz D, Patel P and Sengupta S (2011). VL2, Communications of the ACM, 54:3, (95-104), Online publication date: 1-Mar-2011.

Teimouri N, Modarressi M, Tavakkol A and Sarbazi-azad H Energy-optimized on-chip networks using reconfigurable shortcut paths Proceedings of the 24th international conference on Architecture of computing systems, (231-242)

Nguyen S and Oyanagi S An improvement of router throughput for on-chip networks using on-the-fly virtual channel allocation Proceedings of the 24th international conference on Architecture of computing systems, (219-230)

Fall K, Iannaccone G, Manesh M, Ratnasamy S, Argyraki K, Dobrescu M and Egi N (2011). RouteBricks, ACM SIGOPS Operating Systems Review, 45:1, (112-125), Online publication date: 18-Feb-2011.

Pasricha S and Zou Y NS-FTR Proceedings of the 16th Asia and South Pacific Design Automation Conference, (443-448)

Chang Y, Chiu C, Lin S and Liu C On the design and analysis of fault tolerant NoC architecture using spare routers Proceedings of the 16th Asia and South Pacific Design Automation Conference, (431-436)

Hu W, Lu Z, Jantsch A and Liu H Power-efficient tree-based multicast support for networks-on-chip Proceedings of the 16th Asia and South Pacific Design Automation Conference, (363-368)

Gotmanov A, Chatterjee S and Kishinevsky M Verifying deadlock-freedom of communication fabrics Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation, (214-231)

Hassan K, Pétrot F, Locatelli R and Coppola M EEEP Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, (3-6)

Beiu V, Madappuram B, Kelly P and McDaid L On two-layer brain-inspired hierarchical topologies – a rent's rule approach – Transactions on High-Performance Embedded Architectures and Compilers IV, (311-333)

Liao X, Jigang W and Srikanthan T A modular simulator framework for network-on-chip based manycore chips using UNISIM Transactions on High-Performance Embedded Architectures and Compilers IV, (234-253)

Muralidhara S and Kandemir M Communication based proactive link power management Transactions on High-Performance Embedded Architectures and Compilers IV, (135-154)

Hirata Y, Matsutani H, Koibuchi M and Amano H A variable-pipeline on-chip router optimized to traffic pattern Proceedings of the Third International Workshop on Network on Chip Architectures, (57-62)

Kiasari A, Jantsch A and Lu Z A framework for designing congestion-aware deterministic routing Proceedings of the Third International Workshop on Network on Chip Architectures, (45-50)

Mangano D and Strano G Enabling dynamic and programmable QoS in SoCs Proceedings of the Third International Workshop on Network on Chip Architectures, (17-22)

Bakhoda A, Kim J and Aamodt T Throughput-Effective On-Chip Networks for Manycore Accelerators Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, (421-432)

Jafri S, Hong Y, Thottethodi M and Vijaykumar T Adaptive Flow Control for Robust Performance and Energy Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, (433-444)

Lee M, Kim J, Abts D, Marty M and Lee J Probabilistic Distance-Based Arbitration Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, (509-519)

Ogras U, Bogdan P and Marculescu R (2010). An analytical approach for network-on-chip performance analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:12, (2001-2013), Online publication date: 1-Dec-2010.

Kim H, Heo S, Lee J, Huh J and Kim J On-Chip Network Evaluation Framework Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis

Kahng A, Lin B, Samadi K and Ramanujam R Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations Proceedings of the International Conference on Computer-Aided Design, (256-263)

Ye X, Yin Y, Yoo S, Mejia P, Proietti R and Akella V DOS Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, (1-12)

Wang L, Kumar P, Boyapati R, Yum K and Kim E Efficient lookahead routing and header compression for multicasting in networks-on-chip Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, (1-10)

Krishnaiah G, Silpa B, Panda P and Kumar A FastFwd Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (247-256)

Leary G and Chatha K A holistic approach to network-on-chip synthesis Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (213-222)

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Auerbach G, Copty F and Paruthi V Formal verification of arbiters using property strengthening and underapproximations Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design, (21-24)

Nychis G, Fallin C, Moscibroda T and Mutlu O Next generation on-chip networks Proceedings of the 9th ACM SIGCOMM Workshop on Hot Topics in Networks, (1-6)

Jang W and Pan D (2010). An SDRAM-aware router for networks-on-chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:10, (1572-1585), Online publication date: 1-Oct-2010.

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Sharma V, Agarwal R, Gaur M, Laxmi V and V. V ERA Proceedings of the 2010 IFIP international conference on Network and parallel computing, (481-490)

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Grot B, Keckler S and Mutlu O Topology-Aware quality-of-service support in highly integrated chip multiprocessors Proceedings of the 2010 international conference on Computer Architecture, (357-375)

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Yoon Y, Concer N, Petracca M and Carloni L Virtual channels vs. multiple physical networks Proceedings of the 47th Design Automation Conference, (162-165)

Zhang X and Louri A A multilayer nanophotonic interconnection network for on-chip many-core communications Proceedings of the 47th Design Automation Conference, (156-161)

Bezerra G, Forrest S, Moses M, Davis A and Zarkesh-Ha P Modeling NoC traffic locality and energy consumption with rent's communication probability distribution Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, (3-8)

Park J and Dally W Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures, (1-10)

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Passas G, Katevenis M and Pnevmatikatos D A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (87-95)

Palumbo F, Pani D, Pilia A and Raffo L Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (249-256)

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Wu R, Wang Y and Zhao D A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (199-206)

Kao Y, Alfaraj N, Yang M and Chao H Design of High-Radix Clos Network-on-Chip Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (181-188)

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Nikitin N, Chatterjee S, Cortadella J, Kishinevsky M and Ogras U Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (125-134)

Kang Y, Kwon T and Draper J Fault-Tolerant Flow Control in On-chip Networks Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (79-86)

Ramanujam R, Soteriou V, Lin B and Peh L Design of a High-Throughput Distributed Shared-Buffer NoC Router Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (69-78)

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Horak M, Nowick S, Carlberg M and Vishkin U A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (43-50)

Michelogiannakis G, Sanchez D, Dally W and Kozyrakis C Evaluating Bufferless Flow Control for On-chip Networks Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (9-16)

Meng X, Pappas V and Zhang L Improving the scalability of data center networks with traffic-aware virtual machine placement Proceedings of the 29th conference on Information communications, (1154-1162)

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Fu B, Han Y, Li H and Li X Accelerating lightpath setup via broadcasting in binary-tree waveguide in optical NoCs Proceedings of the Conference on Design, Automation and Test in Europe, (933-936)

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Agarwal N, Peh L and Jha N In-network coherence filtering Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, (232-243)

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Kim J and Kim H Router microarchitecture and scalability of ring topology in on-chip networks Proceedings of the 2nd International Workshop on Network on Chip Architectures, (5-10)

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Min G, Wu Y, Ould-Khaoua M, Yin H and Li K Performance modelling and analysis of interconnection networks with spatio-temporal bursty traffic Proceedings of the 28th IEEE conference on Global telecommunications, (5246-5251)

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Sunkam Ramanujam R and Lin B Weighted random oblivious routing on torus networks Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, (104-112)

Dobrescu M, Egi N, Argyraki K, Chun B, Fall K, Iannaccone G, Knies A, Manesh M and Ratnasamy S RouteBricks Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles, (15-28)

Stuart M, Stensgaard M and Sparsø J Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, (481-490)

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Cohen D, Petrini F, Day M, Ben-Yehuda M, Hunter S and Cummings U (2009). Applying Amdahl's other law to the data center, IBM Journal of Research and Development, 53:5, (683-694), Online publication date: 1-Sep-2009.

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Li Z, Wu J, Shang L, Mickelson A, Vachharajani M, Filipovic D, Park W and Sun Y A high-performance low-power nanophotonic on-chip network Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, (291-294)

Greenberg A, Hamilton J, Jain N, Kandula S, Kim C, Lahiri P, Maltz D, Patel P and Sengupta S (2009). VL2, ACM SIGCOMM Computer Communication Review, 39:4, (51-62), Online publication date: 16-Aug-2009.

Greenberg A, Hamilton J, Jain N, Kandula S, Kim C, Lahiri P, Maltz D, Patel P and Sengupta S VL2 Proceedings of the ACM SIGCOMM 2009 conference on Data communication, (51-62)

Jang W and Pan D An SDRAM-aware router for Networks-on-Chip Proceedings of the 46th Annual Design Automation Conference, (800-805)

Cessna J and Bewley T Honeycomb-structured computational interconnects and their scalable extension to spherical domains Proceedings of the 11th international workshop on System level interconnect prediction, (27-36)

Jaros J Evolutionary optimization of multistage interconnection networks performance Proceedings of the 11th Annual conference on Genetic and evolutionary computation, (1537-1544)

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Pan Y, Kumar P, Kim J, Memik G, Zhang Y and Choudhary A Firefly Proceedings of the 36th annual international symposium on Computer architecture, (429-440)

Jiang N, Kim J and Dally W Indirect adaptive routing on large scale interconnection networks Proceedings of the 36th annual international symposium on Computer architecture, (220-231)

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Moscibroda T and Mutlu O A case for bufferless routing in on-chip networks Proceedings of the 36th annual international symposium on Computer architecture, (196-207)

Abts D, Enright Jerger N, Kim J, Gibson D and Lipasti M (2009). Achieving predictable performance through better memory controller placement in many-core CMPs, ACM SIGARCH Computer Architecture News, 37:3, (451-461), Online publication date: 15-Jun-2009.

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Jiang N, Kim J and Dally W (2009). Indirect adaptive routing on large scale interconnection networks, ACM SIGARCH Computer Architecture News, 37:3, (220-231), Online publication date: 15-Jun-2009.

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Navaridas J, Luján M, Miguel-Alonso J, Plana L and Furber S Understanding the interconnection network of SpiNNaker Proceedings of the 23rd international conference on Supercomputing, (286-295)

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Wang L, Zhang J, Yang X and Wen D Router with centralized buffer for network-on-chip Proceedings of the 19th ACM Great Lakes symposium on VLSI, (469-474)

Kang Y, Sondeen J and Draper J Multicast routing with dynamic packet fragmentation Proceedings of the 19th ACM Great Lakes symposium on VLSI, (113-116)

Kwon W, Yoo S, Um J and Jeong S In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem Proceedings of the Conference on Design, Automation and Test in Europe, (1058-1063)

Li Z, Wu J, Shang L, Dick R and Sun Y Latency criticality aware on-chip communication Proceedings of the Conference on Design, Automation and Test in Europe, (1052-1057)

Concer N, Iamundo S and Bononi L aEqualized Proceedings of the Conference on Design, Automation and Test in Europe, (749-754)

Modarressi M, Sarbazi-Azad H and Arjomand M A hybrid packet-circuit switched on-chip network based on SDM Proceedings of the Conference on Design, Automation and Test in Europe, (566-569)

Suárez D, Monreal T, Vallejo F, Beivide R and Viñals V Light NUCA Proceedings of the Conference on Design, Automation and Test in Europe, (530-535)

Liu Z, Zhang X, Zhao Y and Wang R A performance analysis framework for routing lookup in scalable routers Proceedings of the 23rd international conference on Information Networking, (225-229)

Qian Y, Lu Z and Dou W Analysis of communication delay bounds for network on chips Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (7-12)

Kodi A, Sarathy A, Louri A and Wang J Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (1-6)

Borrione D, Helmy A, Pierre L and Schmaltz J (2009). A formal approach to the verification of networks on chip, EURASIP Journal on Embedded Systems, 2009, (1-14), Online publication date: 1-Jan-2009.

Marculescu R, Ogras U, Peh L, Jerger N and Hoskote Y (2009). Outstanding research problems in NoC design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:1, (3-21), Online publication date: 1-Jan-2009.

Xiang D, Zhang Y and Sun J (2008). Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes, Journal of Systems Architecture: the EUROMICRO Journal, 54:12, (1164-1178), Online publication date: 1-Dec-2008.

Cho M, Cheng C, Kinsy M, Suh G and Devadas S Diastolic arrays Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, (457-464)

Chang M, Cong J, Kaplan A, Liu C, Naik M, Premkumar J, Reinman G, Socher E and Tam S Power reduction of CMP communication networks via RF-interconnects Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, (376-387)

Kumar A, Peh L and Jha N Token flow control Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, (342-353)

Yuho Jin , Yum K and Kim E Adaptive data compression for high-performance low-power on-chip networks Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, (354-363)

Raghavan A, Blundell C and Martin M Token tenure Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, (47-58)

Concer N, Petracca M and Carloni L Distributed flit-buffer flow control for networks-on-chip Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, (215-220)

Pavlidis V and Friedman E (2008). Three-dimensional Integrated Circuit Design, 10.5555/1457591, Online publication date: 25-Sep-2008.

Madelaine F and Stewart I (2008). Improved upper and lower bounds on the feedback vertex numbers of grids and butterflies, Discrete Mathematics, 308:18, (4144-4164), Online publication date: 1-Sep-2008.

Argyraki K, Baset S, Chun B, Fall K, Iannaccone G, Knies A, Kohler E, Manesh M, Nedevschi S and Ratnasamy S Can software routers scale? Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow, (21-26)

Palumbo F, Secchi S, Pani D and Raffo L A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, (96-105)

Jaros J and Dvorak V An evolutionary design technique for collective communications on optimal diameter-degree networks Proceedings of the 10th annual conference on Genetic and evolutionary computation, (1539-1546)

Wang J, Ho T, Ferrero D and Sung T (2008). Diameter variability of cycles and tori, Information Sciences: an International Journal, 178:14, (2960-2967), Online publication date: 1-Jul-2008.

Lee J, Ng M and Asanovic K Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks Proceedings of the 35th Annual International Symposium on Computer Architecture, (89-100)

Kim M, Davis J, Oskin M and Austin T Polymorphic On-Chip Networks Proceedings of the 35th Annual International Symposium on Computer Architecture, (101-112)

Kim J, Dally W, Scott S and Abts D Technology-Driven, Highly-Scalable Dragonfly Topology Proceedings of the 35th Annual International Symposium on Computer Architecture, (77-88)

Kodi A, Sarathy A and Louri A iDEAL Proceedings of the 35th Annual International Symposium on Computer Architecture, (241-250)

Jerger N, Peh L and Lipasti M Virtual Circuit Tree Multicasting Proceedings of the 35th Annual International Symposium on Computer Architecture, (229-240)

Balkan A, Qu G and Vishkin U An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing Proceedings of the 45th annual Design Automation Conference, (435-440)

Kodi A, Sarathy A and Louri A (2008). iDEAL, ACM SIGARCH Computer Architecture News, 36:3, (241-250), Online publication date: 1-Jun-2008.

Jerger N, Peh L and Lipasti M (2008). Virtual Circuit Tree Multicasting, ACM SIGARCH Computer Architecture News, 36:3, (229-240), Online publication date: 1-Jun-2008.

Kim M, Davis J, Oskin M and Austin T (2008). Polymorphic On-Chip Networks, ACM SIGARCH Computer Architecture News, 36:3, (101-112), Online publication date: 1-Jun-2008.

Lee J, Ng M and Asanovic K (2008). Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks, ACM SIGARCH Computer Architecture News, 36:3, (89-100), Online publication date: 1-Jun-2008.

Kim J, Dally W, Scott S and Abts D (2008). Technology-Driven, Highly-Scalable Dragonfly Topology, ACM SIGARCH Computer Architecture News, 36:3, (77-88), Online publication date: 1-Jun-2008.

Lu S and Yang X A clustering model for multicast on hypercube network Proceedings of the 3rd international conference on Advances in grid and pervasive computing, (211-221)

Jerger N, Peh L and Lipasti M Circuit-Switched Coherence Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (193-202)

Abad P, Puente V and Gregorio J Reducing the Interconnection Network Cost of Chip Multiprocessors Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (183-192)

Cohen I, Rottenstreich O and Keslassy I Statistical Approach to NoC Design Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (171-180)

Matsutani H, Koibuchi M, Wang D and Amano H Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (23-32)

Koibuchi M, Matsutani H, Amano H and Pinkston T A Lightweight Fault-Tolerant Mechanism for Network-on-Chip Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, (13-22)

Lotfi-Kamran P, Daneshtalab M, Lucas C and Navabi Z BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs Proceedings of the conference on Design, automation and test in Europe, (1408-1413)

Matsutani H, Koibuchi M, Wang D and Amano H Run-time power gating of on-chip routers using look-ahead routing Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (55-60)

Meter R, Munro W, Nemoto K and Itoh K (2008). Arithmetic on a distributed-memory quantum multicomputer, ACM Journal on Emerging Technologies in Computing Systems, 3:4, (1-23), Online publication date: 1-Jan-2008.

Ogras U and Marculescu R (2008). Analysis and optimization of prediction-based flow control in networks-on-chip, ACM Transactions on Design Automation of Electronic Systems, 13:1, (1-28), Online publication date: 1-Jan-2008.

Kodi A, Sarathy A and Louri A Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, (47-56)

Martinez A, Alfaro F, Sanchez J, Quiles F and Duato J (2007). A New Cost-Effective Technique for QoS Support in Clusters, IEEE Transactions on Parallel and Distributed Systems, 18:12, (1714-1726), Online publication date: 1-Dec-2007.

Gu H, Zhang J, Wang K and Wang C rHALB Proceedings of the 7th international conference on Advanced parallel processing technologies, (392-401)

Wang (2007). System-on-Chip Test Architectures, 10.5555/1564784, Online publication date: 20-Nov-2007.

Kodi A and Louri A Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems Proceedings of the 2007 ACM/IEEE conference on Supercomputing, (1-12)

Ali M, Welzl M, Hessler S and Hellebrand S (2007). An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip, International Journal of High Performance Systems Architecture, 1:2, (113-123), Online publication date: 1-Oct-2007.

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Pavlidis V and Friedman E (2007). 3-D topologies for networks-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:10, (1081-1090), Online publication date: 1-Oct-2007.

Stewart L, Gingold D, Leonard J and Watkins P RDMA in the SiCortex cluster systems Proceedings of the 14th European conference on Recent Advances in Parallel Virtual Machine and Message Passing Interface, (260-271)

Safaei F, Khonsari A, Fathy M, Talebanfard N and Ould-Khaoua M Communication-prediction of scouting switching in adaptively-routed torus networks Proceedings of the 2007 IFIP international conference on Network and parallel computing, (466-475)

Zekri A and Sedukhin S Performance evaluation of basic linear algebra subroutines on a matrix co-processor Proceedings of the 7th international conference on Parallel processing and applied mathematics, (1190-1199)

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Shacham A and Bergman K (2007). Building Ultralow-Latency Interconnection Networks Using Photonic Integration, IEEE Micro, 27:4, (6-20), Online publication date: 1-Jul-2007.

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Kim J, Dally W and Abts D Flattened butterfly Proceedings of the 34th annual international symposium on Computer architecture, (126-137)

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Scott S, Abts D, Kim J and Dally W The BlackWidow High-Radix Clos Network Proceedings of the 33rd annual international symposium on Computer Architecture, (16-28)

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Gu H, Xie Q, Wang K, Zhang J and Li Y X-torus Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part V, (149-157)

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Kim J, Park D, Nicopoulos C, Vijaykrishnan N and Das C Design and analysis of an NoC architecture from performance, reliability and energy perspective Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems, (173-182)

Gu H, Liu Z, Yang J, Qiu Z and Kang G Building a terabit router with XD networks Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture, (520-528)

Yokota T, Nishitani M, Ootsu K, Furukawa F and Baba T Cross-line Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems, (191-198)

Pullini A, Angiolini F, Bertozzi D and Benini L Fault tolerance overhead in network-on-chip flow control schemes Proceedings of the 18th annual symposium on Integrated circuits and system design, (224-229)

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Mello A, Tedesco L, Calazans N and Moraes F Virtual channels in networks on chip Proceedings of the 18th annual symposium on Integrated circuits and system design, (178-183)

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Nachiondo T, Flich J, Duato J and Gusat M Cost / performance trade-offs and fairness evaluation of queue mapping policies Proceedings of the 11th international Euro-Par conference on Parallel Processing, (1024-1034)

Kim J, Park D, Theocharides T, Vijaykrishnan N and Das C A low latency router supporting adaptivity for on-chip interconnects Proceedings of the 42nd annual Design Automation Conference, (559-564)

Kim J, Dally W, Towles B and Gupta A Microarchitecture of a High-Radix Router Proceedings of the 32nd annual international symposium on Computer Architecture, (420-431)

Kim J, Dally W, Towles B and Gupta A (2005). Microarchitecture of a High-Radix Router, ACM SIGARCH Computer Architecture News, 33:2, (420-431), Online publication date: 1-May-2005.

Gomez M, Lopez P and Duato J A Memory-Effective Routing Strategy for Regular Interconnection Networks Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01

Murali S, Benini L and De Micheli G Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (27-32)

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Ferreira J, Silveira J, Silveira J, Cataldo R, Webber T, Moraes F and Marcon C Efficient traffic balancing for NoC routing latency minimization 2016 IEEE International Symposium on Circuits and Systems (ISCAS), (2599-2602)

Wang L, Ma S and Wang Z A high performance reliable NoC eouter 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), (712-718)

Rout S, M B and Deb S Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), (97-102)

Chen P, Liu W, Li M, Yang L and Guan N Contention Minimized Bypassing in SMART NoC 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), (205-210)