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Token flow control

Published: 08 November 2008 Publication History

Abstract

As companies move towards many-core chips, an efficient on-chip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scalability and increasing bandwidth demands, state-of-the-art on-chip networks use a modular packet-switched design with routers at every hop which allow sharing of network channels over multiple packet flows. This, however, leads to packets going through a complex router pipeline at every hop, resulting in the overall communication energy/delay being dominated by the router overhead, as opposed to just wire energy/delay.

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cover image ACM Conferences
MICRO 41: Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
November 2008
483 pages
ISBN:9781424428366

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IEEE Computer Society

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Published: 08 November 2008

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MICRO 41 Paper Acceptance Rate 40 of 210 submissions, 19%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

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