research-article

Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems

Authors:

AISTECS '16: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

Article No.: 4, Pages 1 - 6

https://doi.org/10.1145/2857058.2857059

Published: 18 January 2016 Publication History

Get Access

Abstract

This paper describes a proposal for FAT tree based Network-on-Chip system based on MPLS forwarding mechanism. The FAT tree includes processing nodes and communication switches. IP node (processing nodes) has a message generator unit which randomly generates messages to different destinations with different packet lengths and buffering. The switch is based on MPLS technique and consists of the following units: crossbar switch, input/output link controllers and routing and arbitration units. A simulator has been developed in C++ to analyze the proposed architecture. A comparison with wormhole switch is provided to show the efficiency of the MPLS designed switch.

References

[1]

W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," Proc. of the DAC'38 Conference, Las Vegas, June 2001.

Digital Library

Google Scholar

[2]

De Michelli G, Benini L. Network on Chips. Morgan Kaufmann: Berlin, 2006.

Google Scholar

[3]

J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks -- An Engineering Approach, Morgan Kaufmann, 2002.

Digital Library

Google Scholar

[4]

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers, San Francisco, 2004.

Digital Library

Google Scholar

[5]

Rosen E., Viswanathan A., & Callon R.: Multiprotocol Label Switching architecture, IETF RFC 3031, 2001

Digital Library

Google Scholar

[6]

Harry G. Perros: "Connection-oriented Networks SONET/SDH, ATM, MPLS and OPTICAL NETWORKS," John Wiley & Sons Ltd, UK, 2005.

Digital Library

Google Scholar

[7]

Azeddien M. Sllame, Asma Elasar: Modeling and Simulating Network-on-Chip Designs: A Case Study of Fat Tree Interconnection Architecture, In International Journal of Computer Theory and Engineering, pp. 823--829, Vol. 5, No. 5, October 2013.

Google Scholar

[8]

Azeddien M. Sllame: Modeling and Simulating MPLS Networks, In IEEE International Symposium on Networks, Computers and Communications (ISNCC 2014), IEEE, Tunis, June 2014.

Crossref

Google Scholar

[9]

P. Magarshack, P.G. Paulin, "System-on-Chip Beyond the Nanometer Wall", Proceedings of DAC'03, June 2--6, 2003, Anaheim, USA.

Digital Library

Google Scholar

[10]

P. Guerrier, A. Greiner, "A generic architecture for on-chip packet switched interconnections", Proceedings of DATE"00 Conference.

Digital Library

Google Scholar

[11]

P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, "High-Throughput Switch-Based Interconnect for Future SoCs", Proceedings of 3rd IEEE IWSOC'3, Calgary, Canada.

Google Scholar

[12]

Manho Kim, Daewook Kim and Gerald E. Sobelman: Network-on-Chip Quality-of-Service through MultiProtocol Label Switching, In IEEE International Symposium on Circuits and Systems (ISCAS 2006), pp. 1843, 2006.

Google Scholar

[13]

Basavaraj Talwar, Shailesh Kulkarni and Bharadwaj Amrutur, "Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration", 22nd Intl. Conference on VLSI Design, Jan. 2009.

Digital Library

Google Scholar

Cited By

View all

Sllame ADaddsh M(2023)Designing Torus and HyperCube Network-on-Chip Systems Based on MPLS Networking Technique2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA)10.1109/MI-STA57575.2023.10169637(570-575)Online publication date: 21-May-2023
https://doi.org/10.1109/MI-STA57575.2023.10169637
Lallas EXenakis AStamoulis GKorinthios J(2018)QoS and MPLS design issues in NoCs2018 South-Eastern European Design Automation, Computer Engineering, Computer Networks and Society Media Conference (SEEDA_CECNSM)10.23919/SEEDA-CECNSM.2018.8544942(1-4)Online publication date: Sep-2018
https://doi.org/10.23919/SEEDA-CECNSM.2018.8544942
Sllame ASalama N(2016)An MPLS-based fat tree Network-on-Chip systems2016 International Conference on Advances in Computing and Communication Engineering (ICACCE)10.1109/ICACCE.2016.8073719(29-36)Online publication date: Nov-2016
https://doi.org/10.1109/ICACCE.2016.8073719

Recommendations

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

In this paper, we present a routing algorithm that combines the shortest path routing and adaptive routing schemes for NoCs. In specific, routing follows the shortest path to ensure low latency and low energy consumption. This routing scheme requires ...
Performance Evaluation of Switch-Based Wormhole Networks

Multistage interconnection networks (MINs) are a popular class of switch-based network architectures for constructing scalable parallel computers. Four wormhole MINs built from k k switches, where k = 2j for some j, are considered in this paper: ...
A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip
DMEMS '10: Proceedings of the 2010 First Workshop on Hardware and Software Implementation and Control of Distributed MEMS

Future Multiprocessor Systems-on-Chip (SoCs) will consist of various digital and analog components, such as processing cores, storage elements, customized IP-cores, analog peripheral devices, and many other items of MEMS. Network-on-chip is a promising ...

Comments

Information & Contributors

Information

Published In

AISTECS '16: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

January 2016

53 pages

ISBN:9781450340847

DOI:10.1145/2857058

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

HiPEAC: HiPEAC Network of Excellence

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2016

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

AISTECS '16

AISTECS '16: 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

January 18, 2016

Prague, Czech Republic

Acceptance Rates

Overall Acceptance Rate 7 of 8 submissions, 88%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
58
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 06 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Sllame ADaddsh M(2023)Designing Torus and HyperCube Network-on-Chip Systems Based on MPLS Networking Technique2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA)10.1109/MI-STA57575.2023.10169637(570-575)Online publication date: 21-May-2023
https://doi.org/10.1109/MI-STA57575.2023.10169637
Lallas EXenakis AStamoulis GKorinthios J(2018)QoS and MPLS design issues in NoCs2018 South-Eastern European Design Automation, Computer Engineering, Computer Networks and Society Media Conference (SEEDA_CECNSM)10.23919/SEEDA-CECNSM.2018.8544942(1-4)Online publication date: Sep-2018
https://doi.org/10.23919/SEEDA-CECNSM.2018.8544942
Sllame ASalama N(2016)An MPLS-based fat tree Network-on-Chip systems2016 International Conference on Advances in Computing and Communication Engineering (ICACCE)10.1109/ICACCE.2016.8073719(29-36)Online publication date: Nov-2016
https://doi.org/10.1109/ICACCE.2016.8073719

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Performance Evaluation of Switch-Based Wormhole Networks

A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip

Comments

Published In

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Recommendations

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Performance Evaluation of Switch-Based Wormhole Networks

A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip

Comments

Information

Published In

In-Cooperation

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations