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A novel differential scan attack on advanced DFT structures

Published: 25 October 2013 Publication History

Abstract

Scan chains insertion is the most common technique to ensure the testability of digital cores, providing high fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data thus becoming a threat to system security. So far, advanced test structures used to reduce test costs (e.g., response compaction) and achieve high fault coverage (e.g., X's masking decoder) have been considered as intrinsic countermeasures against these threats. This work proposes a new generic scan-based attack demonstrating that these test structures are not sufficiently effective to prevent leakage through the test infrastructure. This generic attack can be easily adapted to several cryptographic implementations for both symmetric and public key algorithms. The proposed attack is demonstrated on several ciphers.

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 18, Issue 4
    Special Section on Networks on Chip: Architecture, Tools, and Methodologies
    October 2013
    380 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/2541012
    Issue’s Table of Contents
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    Publication History

    Published: 25 October 2013
    Accepted: 01 March 2013
    Revised: 01 November 2012
    Received: 01 July 2012
    Published in TODAES Volume 18, Issue 4

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    Author Tags

    1. Scan-based DFT
    2. side-channel attacks

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