article

A spatial path scheduling algorithm for EDGE architectures

Authors:

Katherine E. Coons,

Kathryn S. McKinley,

Sundeep K. KushwahaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 34, Issue 5

Pages 129 - 140

https://doi.org/10.1145/1168919.1168875

Published: 20 October 2006 Publication History

Abstract

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

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Li YTan XXue RYe XLi WWang DZhang HFan D(2019)A Sharing Path Awareness Scheduling Algorithm for Dataflow Architecture2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00017(9-18)Online publication date: Aug-2019
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Nowatzki TArdalani NSankaralingam KWeng JEvripidou SStenström PO'Boyle M(2018)Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesignProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243212(1-15)Online publication date: 1-Nov-2018
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Index Terms

A spatial path scheduling algorithm for EDGE architectures
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 34, Issue 5

Proceedings of the 2006 ASPLOS Conference

December 2006

425 pages

ISSN:0163-5964

DOI:10.1145/1168919

Issue’s Table of Contents

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
October 2006
440 pages
ISBN:1595934510
DOI:10.1145/1168857
General Chair:
John Paul Shen
Intel Corp.
,
Program Chair:
Margaret R. Martonosi
Princeton University

Copyright © 2006 ACM.

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Association for Computing Machinery

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Publication History

Published: 20 October 2006

Published in SIGARCH Volume 34, Issue 5

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Cited By

Li YWu MYe XLi WXue RWang DZhang HFan D(2020)An Efficient Scheduling Algorithm for Dataflow Architecture Using Loop-PipeliningInformation Sciences10.1016/j.ins.2020.09.029Online publication date: Oct-2020
https://doi.org/10.1016/j.ins.2020.09.029
Li YTan XXue RYe XLi WWang DZhang HFan D(2019)A Sharing Path Awareness Scheduling Algorithm for Dataflow Architecture2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC/SmartCity/DSS.2019.00017(9-18)Online publication date: Aug-2019
https://doi.org/10.1109/HPCC/SmartCity/DSS.2019.00017
Nowatzki TArdalani NSankaralingam KWeng JEvripidou SStenström PO'Boyle M(2018)Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesignProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243212(1-15)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1145/3243176.3243212
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