article

Fast and Precise WCET Prediction by Separated Cache andPath Analyses

Authors:

Henrik Theiling,

Christian Ferdinand,

Reinhard WilhelmAuthors Info & Claims

Real-Time Systems, Volume 18, Issue 2/3

Pages 157 - 179

https://doi.org/10.1023/A:1008141130870

Published: 01 May 2000 Publication History

Abstract

Precise run-time prediction suffers from a complexity problem when doing an integrated analysis. This problem is characterised by the conflict between an optimal solution and the complexity of the computation of the solution.

The analysis of modern hardware consists of two parts: a) the analysis of the microarchitecture‘s behaviour (caches, pipelines) and b) the search for the longest program path. Because an integrated analysis has a significant computational complexity, we chose to separate these two steps. By this, an ordering problem arises, because the steps depend on each other.

In this paper we show how the microarchitecture analysis can be separated from the path analysis in order to make the overall analysis fast. Practical experiments will show that this separation, however, does not make the analysis more pessimistic than existing approaches. Furthermore, we show that the approach can be used to analyse executables created by a standard optimising compiler.

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Cited By

Lee JShin SBriand LNejati S(2023)Probabilistic Safe WCET Estimation for Weakly Hard Real-time Systems at Design StagesACM Transactions on Software Engineering and Methodology10.1145/361717633:2(1-34)Online publication date: 26-Aug-2023
https://dl.acm.org/doi/10.1145/3617176
Xiao JShen YPimentel A(2022)Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core SystemsACM Transactions on Embedded Computing Systems10.1145/348758121:3(1-28)Online publication date: 28-May-2022
https://dl.acm.org/doi/10.1145/3487581
Segarra JGran Tejero RViñals V(2021)A generic framework to integrate data caches in the WCET analysis of real-time systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102304120:COnline publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102304
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Fast and Precise WCET Prediction by Separated Cache andPath Analyses

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Information & Contributors

Information

Published In

cover image Real-Time Systems

Real-Time Systems Volume 18, Issue 2/3

Special issue on worst-case execution-time analysis

May 2000

171 pages

ISSN:0922-6443

Editors:
John A. Stankovic
Univ. of Virginia, Charlottesville
,
Wolfgang A. Halang
FernUniv., Hagen, Germany
,
Kim-Fung Man
City Univ. of Hong Kong, Hong Kong
,
Peter Puschner
Technische Univ. Wien, Vienna, Austria
,
Alan Burns
Univ. of York, York, U.K.

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Copyright © Copyright © 2000 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 May 2000

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Cited By

Lee JShin SBriand LNejati S(2023)Probabilistic Safe WCET Estimation for Weakly Hard Real-time Systems at Design StagesACM Transactions on Software Engineering and Methodology10.1145/361717633:2(1-34)Online publication date: 26-Aug-2023
https://dl.acm.org/doi/10.1145/3617176
Xiao JShen YPimentel A(2022)Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core SystemsACM Transactions on Embedded Computing Systems10.1145/348758121:3(1-28)Online publication date: 28-May-2022
https://dl.acm.org/doi/10.1145/3487581
Segarra JGran Tejero RViñals V(2021)A generic framework to integrate data caches in the WCET analysis of real-time systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2021.102304120:COnline publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.sysarc.2021.102304
Wu MWang CMcKinley KFisher K(2019)Abstract interpretation under speculative executionProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3314221.3314647(802-815)Online publication date: 8-Jun-2019
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Chattopadhyay SBeck MRezine AZeller A(2019)Quantifying the Information Leakage in Cache Attacks via Symbolic ExecutionACM Transactions on Embedded Computing Systems10.1145/328875818:1(1-27)Online publication date: 8-Jan-2019
https://dl.acm.org/doi/10.1145/3288758
Zhang ZGuo ZKoutsoukos XBini EPagetti C(2017)Handling write backs in multi-level cache analysis for WCET estimationProceedings of the 25th International Conference on Real-Time Networks and Systems10.1145/3139258.3139269(208-217)Online publication date: 4-Oct-2017
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Zheng WWu HYang Q(2017)WCET-Aware Dynamic I-Cache Locking for a Single TaskACM Transactions on Architecture and Code Optimization10.1145/304668314:1(1-26)Online publication date: 13-Mar-2017
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Damschen MBauer LHenkel J(2017)Timing Analysis of Tasks on Runtime Reconfigurable ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257230425:1(294-307)Online publication date: 1-Jan-2017
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Gan ZZhang MGu ZTan HZhang J(2017)Delay analysis and optimization for inter-core interference in real-time embedded multicore systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.004103:C(77-86)Online publication date: 1-May-2017
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Chattopadhyay S(2017)Directed Automated Memory Performance TestingProceedings, Part II, of the 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems - Volume 1020610.1007/978-3-662-54580-5_3(38-55)Online publication date: 22-Apr-2017
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