Article

A Worst Case Timing Analysis Technique for Multiple-Issue Machines

Authors:

S.-S. Lim,

J. H. Han,

J. Kim,

S. L. MinAuthors Info & Claims

RTSS '98: Proceedings of the IEEE Real-Time Systems Symposium

Page 334

Published: 02 December 1998 Publication History

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El-Haj-Mahmoud AAL-Zawawi AAnantaraman ARotenberg EConte TFaraboschi PMangione-Smith BNajjar W(2005)Virtual multiprocessorProceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1086297.1086326(213-224)Online publication date: 24-Sep-2005
https://dl.acm.org/doi/10.1145/1086297.1086326
Ermedahl AStappert FEngblom J(2005)Clustered Worst-Case Execution-Time CalculationIEEE Transactions on Computers10.1109/TC.2005.13954:9(1104-1122)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1109/TC.2005.139
Wenzel IKirner RPuschner PRieder B(2005)Principles of Timing Anomalies in Superscalar ProcessorsProceedings of the Fifth International Conference on Quality Software10.1109/QSIC.2005.49(295-306)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1109/QSIC.2005.49
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A Worst Case Timing Analysis Technique for Multiple-Issue Machines

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RTSS '98: Proceedings of the IEEE Real-Time Systems Symposium

December 1998

ISBN:081869212X

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IEEE Computer Society

United States

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Published: 02 December 1998

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El-Haj-Mahmoud AAL-Zawawi AAnantaraman ARotenberg EConte TFaraboschi PMangione-Smith BNajjar W(2005)Virtual multiprocessorProceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1086297.1086326(213-224)Online publication date: 24-Sep-2005
https://dl.acm.org/doi/10.1145/1086297.1086326
Ermedahl AStappert FEngblom J(2005)Clustered Worst-Case Execution-Time CalculationIEEE Transactions on Computers10.1109/TC.2005.13954:9(1104-1122)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1109/TC.2005.139
Wenzel IKirner RPuschner PRieder B(2005)Principles of Timing Anomalies in Superscalar ProcessorsProceedings of the Fifth International Conference on Quality Software10.1109/QSIC.2005.49(295-306)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1109/QSIC.2005.49
Oyamada MZschornack FWagner FNatividade da Silva Barros EWagner FCarro LRammig F(2004)Accurate software performance estimation using domain classification and neural networksProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016617(175-180)Online publication date: 4-Sep-2004
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Ermedahl AStappert FEngblom JMoreno JMurthy PConte TFaraboschi P(2003)Clustered calculation of worst-case execution timesProceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems10.1145/951710.951720(51-62)Online publication date: 30-Oct-2003
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Engblom JErmedahl ASjödin MGustafsson JHansson H(2003)Worst-case execution-time analysis for embedded real-time systemsTHANKSREF="*"ID="*"This work was performed within the Advanced Software Technology (ASTEC, httpInternational Journal on Software Tools for Technology Transfer (STTT)10.1007/s1000901000544:4(437-455)Online publication date: 1-Aug-2003
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Ward MAudsley NBhattacharyya SMudge TWolf WJerraya A(2002)Hardware implementation of the Ravenscar Ada tasking profileProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581641(59-68)Online publication date: 8-Oct-2002
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Mitra TRoychoudhury ALi XAboulhamid ENakamura Y(2002)Timing analysis of embedded software for speculative processorsProceedings of the 15th international symposium on System Synthesis10.1145/581199.581229(126-131)Online publication date: 2-Oct-2002
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Stappert FErmedahl AEngblom JGao GMudge TPalem K(2001)Efficient longest executable path search for programs with complex flows and pipeline effectsProceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/502217.502240(132-140)Online publication date: 16-Nov-2001
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Ward MAudsley NGao GMudge TPalem K(2001)Hardware compilation of sequential adaProceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/502217.502233(99-107)Online publication date: 16-Nov-2001
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Worst case timing analysis of RISC processors: R3000/R3010 case study

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