research-article

Timing Analysis of Tasks on Runtime Reconfigurable Processors

Authors:

Marvin Damschen,

Jorg HenkelAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 25, Issue 1

Pages 294 - 307

https://doi.org/10.1109/TVLSI.2016.2572304

Published: 01 January 2017 Publication History

Abstract

Real-time embedded systems need to be analyzable for timing guarantees. Despite significant scientific advances, however, timing analysis lags years behind current microarchitectures with out-of-order scheduling pipelines, several hardware threads, and multiple (shared) cache layers. To satisfy the increasing performance demands, analyzable performance features are required. We propose a novel timing analysis approach to introduce runtime reconfigurable instruction set processors as one way to escape the scarcity of analyzable performance while preserving the flexibility of the system. We introduce extensions to the state-of-the-art Integer linear programming (ILP)-based program path analysis for computing precise worst case time bounds in the presence of the widely used technique to continue processor execution during reconfiguration by emulating not yet reconfigured custom instructions (CIs) in software. We identify and safely bound a timing anomaly of runtime reconfiguration, where executing faster than worst case time during reconfiguration extends the execution time of the whole program. Stalling the processor during reconfiguration (easier to analyze but not state-of-the-art for reconfigurable processors) is not required in our approach. Finally, we show the precision of our analysis on a complex multimedia application with multiple reconfigurable CIs for several hardware parameters and give advice on how to deal with reconfiguration delay under timing guarantees.

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Cited By

Valente GMuttillo VFederici FPomante LDi Mascio T(2023)Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic InjectionIEEE Embedded Systems Letters10.1109/LES.2023.330540116:2(162-165)Online publication date: 15-Aug-2023
https://dl.acm.org/doi/10.1109/LES.2023.3305401
Bauer LDamschen MZiegenbein DHamann ABiondi AButtazzo GHenkel J(2019)Analyses and architectures for mixed-critical systemsProceedings of the International Conference on Embedded Software Companion10.1145/3349568.3356997(1-2)Online publication date: 13-Oct-2019
https://dl.acm.org/doi/10.1145/3349568.3356997
Choi JYang HHa S(2018)Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/327515424:1(1-26)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3275154
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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 25, Issue 1

January 2017

392 pages

ISSN:1063-8210

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Copyright © 2017.

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IEEE Educational Activities Department

United States

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Published: 01 January 2017

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Cited By

Valente GMuttillo VFederici FPomante LDi Mascio T(2023)Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic InjectionIEEE Embedded Systems Letters10.1109/LES.2023.330540116:2(162-165)Online publication date: 15-Aug-2023
https://dl.acm.org/doi/10.1109/LES.2023.3305401
Bauer LDamschen MZiegenbein DHamann ABiondi AButtazzo GHenkel J(2019)Analyses and architectures for mixed-critical systemsProceedings of the International Conference on Embedded Software Companion10.1145/3349568.3356997(1-2)Online publication date: 13-Oct-2019
https://dl.acm.org/doi/10.1145/3349568.3356997
Choi JYang HHa S(2018)Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT AnalysisACM Transactions on Design Automation of Electronic Systems10.1145/327515424:1(1-26)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3275154
Rossi EDamschen MBauer LButtazzo GHenkel J(2018)Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/318218311:2(1-24)Online publication date: 26-Jul-2018
https://dl.acm.org/doi/10.1145/3182183
Tagliavini GCesarini DMarongiu A(2018)Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP TaskingIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.281460229:9(2150-2163)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1109/TPDS.2018.2814602
Damschen MBauer LHenkel J(2017)CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time SystemsIEEE Embedded Systems Letters10.1109/LES.2017.27148449:3(77-80)Online publication date: 28-Aug-2017
https://dl.acm.org/doi/10.1109/LES.2017.2714844

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