research-article

Designing single-cycle long links in hierarchical NoCs

Authors:

Avinoam KolodnyAuthors Info & Claims

Microprocessors & Microsystems, Volume 38, Issue 8

Pages 814 - 825

https://doi.org/10.1016/j.micpro.2014.05.005

Published: 01 November 2014 Publication History

Abstract

Hierarchical topologies are frequently proposed for large Networks-on-Chip (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC delays of long links might reach dozens of clock cycles in advanced technology nodes, if delay reduction techniques (e.g. wire sizing and repeater insertion) are not applied. Some proposals assume that long links can be adjusted to satisfy timing requirements, but lack a deep evaluation of the tradeoffs and costs. Other proposals assume that long links must be pipelined, but do not provide a comprehensive justification.In this paper we evaluate the efficiency and the system costs of wire sizing and repeater insertion as methods to reduce link delays in hierarchical NoCs. We present a unified interconnect cost function that accounts for power and wiring overheads of these methods. Then, we quantify the costs of modifying long links in typical hierarchical NoCs for different target clock frequencies and technology nodes. Although long links might undergo aggressive adjustments, we find these overall costs to be low at the system level for typical cases, taking into account that there are only a few long links in most proposed hierarchical NoC architectures. A preliminary short version of this work entitled "Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip (NoCs)" was presented in the 16th Euromicro Conference on Digital System Design (DSD), 2013.

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Cited By

Dehghani A(2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
https://dl.acm.org/doi/10.1016/j.future.2020.01.001
Besta MHassan SYalamanchili SAusavarungnirun RMutlu OHoefler T(2018)Slim NoCACM SIGPLAN Notices10.1145/3296957.317715853:2(43-55)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3177158
Besta MHassan SYalamanchili SAusavarungnirun RMutlu OHoefler TShen XTuck JBianchini RSarkar V(2018)Slim NoCProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3177158(43-55)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3177158
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Designing single-cycle long links in hierarchical NoCs
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cover image Microprocessors & Microsystems

Microprocessors & Microsystems Volume 38, Issue 8

November 2014

342 pages

ISSN:0141-9331

Issue’s Table of Contents

Copyright © Elsevier B.V.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 November 2014

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Cited By

Dehghani A(2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
https://dl.acm.org/doi/10.1016/j.future.2020.01.001
Besta MHassan SYalamanchili SAusavarungnirun RMutlu OHoefler T(2018)Slim NoCACM SIGPLAN Notices10.1145/3296957.317715853:2(43-55)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3177158
Besta MHassan SYalamanchili SAusavarungnirun RMutlu OHoefler TShen XTuck JBianchini RSarkar V(2018)Slim NoCProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3177158(43-55)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3177158
Dehghani AJamshidi K(2016)A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/281457212:4(1-37)Online publication date: 15-Mar-2016
https://dl.acm.org/doi/10.1145/2814572
Dehghani AJamshidi K(2015)A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platformsThe Journal of Supercomputing10.1007/s11227-015-1430-z71:8(3116-3148)Online publication date: 1-Aug-2015
https://dl.acm.org/doi/10.1007/s11227-015-1430-z

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