A flexible radio transceiver for TVWS based on FBMC
In this paper a flexible radio approach for opportunistic access to the television white space (TVWS) is presented. Requirement stems from the coexistence scheme used in this band between opportunistic transmission and TV broadcast signals (or wireless ...
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning
We present a scalable architecture for multiple self-contained systems on FPGAs.We use secure bus bridges that offer hardware-enforced domain partitioning.Multiple soft processors can reliably operate from common memory resources.Our modular ...
Power consumption models for the use of dynamic and partial reconfiguration
Minimizing the energy consumption and silicon area are usually two major challenges in the design of battery-powered embedded computing systems. Dynamic and Partial Reconfiguration (DPR) opens up promising prospects with the ability to reduce jointly ...
On don't cares in test compression
Both test compression tools and ATPGs directly producing compressed test greatly benefit from don't care values present in the test. Actually, presence of these don't cares is essential for success of the compression. Contemporary ATPGs produce tests ...
A hardware-software co-design approach for implementing sparse matrix vector multiplication on FPGAs
The Field-Programmable Gate Array is an excellent match for the Sparse Matrix-Vector Multiply (SMVM) operation because of its enormous computational capacity and its ability to build a custom memory hierarchy that matches the memory access patterns of ...
A million-bit multiplier architecture for fully homomorphic encryption
In this work we present a full and complete evaluation of a very large multiplication scheme in custom hardware. We designed a novel architecture to realize a million-bit multiplication scheme based on the Schönhage-Strassen Algorithm. We constructed ...
A design assembly framework for FPGA back-end acceleration
There are well known cases where FPGAs provide high performance within a modest power budget, yet unlike conventional desktop solutions, they are oftentimes associated with long wait times before a device configuration is generated. Such long wait times ...
An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability
Near-threshold operation is today a key research area in Ultra-Low Power (ULP) computing, as it promises a major boost in energy efficiency compared to super-threshold computing and it mitigates thermal bottlenecks. Unfortunately near-threshold ...
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic
Dual-rail Precharge Logic (DPL) has been widely studied as an effective countermeasure category for mitigating Side Channel Attack (SCA) threats, where unwanted physical leakages from running crypto devices are inspected and analyzed to retrieve ...
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric
This paper presents a hardware based solution for a scalable runtime address generation scheme for DSP applications mapped to a parallel distributed coarse grain reconfigurable computation and storage fabric. The scheme can also deal with non-affine ...
Seven recipes for setting your FPGA on fire - A cookbook on heat generators
Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel ...
Instruction selection and scheduling for DSP kernels
As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of ...
Designing single-cycle long links in hierarchical NoCs
Hierarchical topologies are frequently proposed for large Networks-on-Chip (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC delays of long links might reach dozens of clock cycles in advanced ...
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes
Asynchronous circuit design is a promising technology for large-scale multi-core systems. As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to ...
MultiPARTES
The consumer market is continuously pushing for smarter, faster, more durable and cheaper products with ever more complex and sophisticated functionality. Other fields such as safety-critical and dependable applications are not unaware of these ...
E2LP
- Ivan Kastelan,
- Jorge R. Lopez Benito,
- Enara Artetxe Gonzalez,
- Jan Piwinski,
- Moshe Barak,
- Miodrag Temerinac
The main idea behind this project is to provide a unified platform which will cover a complete process for embedded systems learning. A modular approach is considered for skills practice through supporting individualization in learning. This platform ...
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths
Numerous applications in important domains, such as communication and multimedia, show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in ...
Improving the design flow for parallel and heterogeneous architectures running real-time applications
- Héctor Posadas,
- Alejandro Nicolás,
- Pablo Peñil,
- Eugenio Villar,
- Florian Broekaert,
- Michel Bourdelles,
- Albert Cohen,
- Mihai T. Lazarescu,
- Luciano Lavagno,
- Andrei Terechko,
- Miguel Glassee,
- Manuel Prieto
In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to guide and assist the designer in the development ...
TERAFLUX
- Roberto Giorgi,
- Rosa M. Badia,
- François Bodin,
- Albert Cohen,
- Paraskevas Evripidou,
- Paolo Faraboschi,
- Bernhard Fechner,
- Guang R. Gao,
- Arne Garbade,
- Rahul Gayatri,
- Sylvain Girbal,
- Daniel Goodman,
- Behran Khan,
- Souad Koliaï,
- Joshua Landwehr,
- Nhat Minh Lê,
- Feng Li,
- Mikel Lujàn,
- Avi Mendelson,
- Laurent Morin,
- Nacho Navarro,
- Tomasz Patejko,
- Antoniu Pop,
- Pedro Trancoso,
- Theo Ungerer,
- Ian Watson,
- Sebastian Weis,
- Stéphane Zuckerman,
- Mateo Valero
Display Omitted Scalable architecture for manycore, tera-device computing.Task-parallel programming models combining dataflow and stateful computations.Parallel simulation of large-scale multi-node architectures.Fault detection and recovery for task-...
A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips
A fault tolerant routing algorithm (FT-DyXYZ) for 3D Network-on-Chip is presented.FT-DyXYZ has low overhead and utilizes proximity congestion to balance traffic.FT-DyXYZ outperforms planar-adaptive routing in fault free and faulty situations.FT-DyXYZ ...
Model of a hybrid processor executing C++ with additional quantum functions
Display Omitted Provide a VHDL simulation model of a hybrid quantum/classical processor.Provide a processor capable of executing classical and quantum programs.Provide an assembler to interpret both classical and quantum assembly instructions.Provide C++...
Automatic custom instruction identification for application-specific instruction set processors
The application-specific instruction set processors (ASIPs) have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom ...
CRANarch
Cloud Radio Access Network (C-RAN) becomes a promising infrastructure, which can improve hardware resource utilization of traditional Radio Access Network (RAN). For C-RAN, data centers are essential hardware platform, and these data centers are ...
Variability-tolerant routing algorithms for Networks-on-Chip
Display Omitted Modifying XY, West-First, Negative-First, and Odd-Even algorithms to consider link failure probability when routing.Proposing the NoC failure rate as a measure of tolerance against process-induced random and systematic delay ...
A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata
Quantum-dot cellular automata (QCA) are promising models in nanotechnology based on the single electron effects of quantum dots and molecules. The present study designs and simulates the elements and principal standard configurable logic block (CLB) of ...
CORDIC-based VLSI architecture for real time implementation of flat top window
Since decades, popular window techniques such as Hanning, Hamming, Blackman and Flat top window have been used to minimize unwanted effects like spectral leakage and scalloping losses due to direct truncation of signals before fast Fourier transform (...
