DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing
Pages 505 - 520
Abstract
Wireless Network-on-Chips (WiNoCs) were expected to handle the communication requirements of the long-distance processing elements. Hence, high-performance WiNoC designs that achieve low-latency and high-throughput are crucial for future performance requirements. The size and organization of the buffer directly affects network performance, while the buffer also determines the area overhead of the router. We propose DCBuf, a distributed CNT-based (Carbon nanotubes) inter-subnet wireless interconnects and centralized intra-port buffer sharing architecture for a symmetry Wireless Network-on-Chip. The centrosymmetric wireless hub structure combined with CNT-based wireless interconnects maximizes the performance ceiling of WiNoC. Moreover, this approach allows to reuse the table-based shared-buffer for different traffic while ensuring that minimizes buffering requirements without sacrificing performance. The architecture uses just two registers per private VC and a shared buffer sized large enough to cover the demand of different traffic that appears either on the NoC links or due to the internal pipeline of the NoC buffers. In this perspective, the shared buffer within an input-port is considered space queues not statically assigned to a specific VC. Cycle-accurate network simulations including both synthetic traffic patterns and real application workloads running in a full-system simulation framework validate the efficacy and efficiency of the proposed architecture.
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Published: 01 February 2022
Accepted: 22 December 2021
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