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On-chip networks (NoCs) have become a popular choice for designing large multiprocessor architectures. Software-based emulation is often used to perform the design verification. However, if the considered design is sufficiently large, software-...

Streaming applications are being extensively run on portable embedded systems, which are battery-operated and with limited memory. Thus, minimizing the total energy consumption of such a system is important. We investigate the problem of offline ...

• Scheduling periodic tasks on NoC-based MPSoCs to minimize energy, considering memory.
• New task mapping and scheduling using retiming and DVFS to reduce energy consumption.
• A heuristic to compute the memory usage of the schedule.

The Network-on-Chip (NoC) is a communication infrastructure designed to integrate various components of a System-on-Chip (SoC) and connect multi-core processors. In on-chip networks, routing is a process that determines how a data packet should ...

The proliferation of multiprocessor system-on-chip (MPSoC) architectures within the Internet of Things (IoT) has introduced notable security challenges. These architectures’ distributed nature, required for smooth communications between the IP ...

In recent years, numerous multicore RISC-V platforms have emerged. Within the RISC-V ecosystem, Networks-on-Chip (NoCs) such as OpenPiton are employed in designs that aim to scale to a large number of cores. This paper presents a set of extensions and ...

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is ...

In today’s world, the demands for high-performance computing necessitate faster on-chip communication. Current chips with a large number of on-chip elements need an efficient alternative such as network-on-chip (NoC) for on-chip ...

Network-on-chip (NoC) exists with the advantages of high communication efficiency, scalability and reliability. In recent years, NoC-based deep neural network (DNN) accelerators have been proposed. Although existing NoC research solutions can ...

It is essential for implementing processing systems of edge computing, internet of things (IoT) and wireless multimedia sensor networks (WMSN) to use low-power parallel and distributed architectures with high speed and low power ...

• Exploration the potential of hybrid path/tree based multicasting by designing an efficient routing algorithm for high traffic NoCs.

Network-on-Chip (NoC) is the state of the art on-chip interconnection network for packet based communication. NoCs can offer low packet latency, high bandwidth, high throughput with minimum area, better energy efficiency and fault ...

• A Vivado HLS implementation of NoC Simulator.
• Performance metrics like latency, ...

Scheduling models can be used to evaluate whether a particular system is able to meet its timing constrains. In many-core processors, with tens to hundreds of processors in the same chip, the analysis of the timing behavior needs to ...

As FPGAs provide tremendous improvements in performance and energy efficiency in a wide range of workloads, cloud infrastructures increasingly incorporate them in their infrastructure for on-demand application acceleration. However, accelerator ...

A Network-on-Chip (NoC) is an essential component of a chip multiprocessor (CMP) which however contributes to a large fraction of system energy. The unpredictability of traffic across a NoC frequently involves an expensive over-sizing of NoC resources ...

Convolutional Neural Networks (CNNs) have a wide range of applications due to their superior performance in image and pattern classification. However, the performance of CNNs comes at the price of high computational load and memory ...

Bubble flow control is a flow control mechanism commonly used in torus network. Bubble flow control ensures the orderly flow of packets in the ring by efficiently allocating intra-ring buffer resources and solves the intra-ring deadlock problem. ...$$$$

This paper reviews the massively micro-parallel compute system POETS (Partially Ordered Event Triggered System) and illustrates its potential for speeding up demanding applications. Application domains that benefit from POETS include simulations of ...

• The additional of wireless shortcuts increases the capability of wireless transmission.

The communication performance over conventional long-distant routers cannot satisfy the requirements of future multi-core systems. Wireless Network-on-Chip (WiNoC) architecture with CMOS compatible transceivers is utilized to obtain ...

Wireless Network-on-Chips (WiNoCs) were expected to handle the communication requirements of the long-distance processing elements. Hence, high-performance WiNoC designs that achieve low-latency and high-throughput are crucial for future ...

The heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad ...$$$$

Deflection routing is considered a promising approach for improving the energy efficiency of networks-on-chip (NoCs) because of its hardware simplicity and minimal buffer requirements. The major weakness of the deflection routing is poor ...