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On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration

Published: 01 October 2015 Publication History

Abstract

Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of wireless network-on-chip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of: 1) the number of cores within the chip, and 2) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity), and network-level considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.

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  1. On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration

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          cover image IEEE/ACM Transactions on Networking
          IEEE/ACM Transactions on Networking  Volume 23, Issue 5
          October 2015
          331 pages
          ISSN:1063-6692
          • Editor:
          • R. Srikant
          Issue’s Table of Contents

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          IEEE Press

          Publication History

          Published: 01 October 2015
          Accepted: 12 June 2014
          Revised: 21 February 2014
          Received: 19 September 2013
          Published in TON Volume 23, Issue 5

          Author Tags

          1. area
          2. design space exploration
          3. emerging interconnect technologies
          4. multicore processors
          5. network-on-chip
          6. on-chip antennas
          7. power
          8. wireless network-on-chip
          9. wireless transceivers

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