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Performance modeling and analysis of carbon nanotube bundles for future VLSI circuit applications

Published: 01 September 2014 Publication History

Abstract

In this work, we have presented a comprehensive analysis of the performance of copper (Cu) and existing carbon nano tube (CNT) bundle structures (i.e. SWCNT, DWCNT and MWCNT) across nanometer technology nodes like 45, 32, 22 and 16 nm at local, intermediate and global level interconnects. Double walled carbon nano tubes (DWCNTs) and multi walled carbon nano tubes (MWCNTs) are modeled like simple single walled carbon nano tube (SWCNT) equivalent model with high accuracy. The analytical closed form delay expressions for SWCNT, DWCNT and MWCNT bundles have been found out. It has been observed that sparse SWCNT bundle interconnects show about 50 % performance improvement for 20 $$\upmu $$ μ m long local level interconnects over Cu in 16 nm technology node, whereas the performance advantage numbers for MWCNT and sparse DWCNT bundles are 50 and 35 % respectively. For 200 $$\upmu $$ μ m long intermediate level interconnects, the performance advantage numbers are 85, 80 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. For 10 mm long global level interconnects, the performance advantage numbers are 85, 85 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. It is also observed that the performance numbers improve with scaling for all levels of interconnects. It is also shown that the ratio of delay of CNT bundles and Cu for various levels of interconnects agree well with the existing work.

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    Published In

    cover image Journal of Computational Electronics
    Journal of Computational Electronics  Volume 13, Issue 3
    September 2014
    209 pages

    Publisher

    Springer-Verlag

    Berlin, Heidelberg

    Publication History

    Published: 01 September 2014

    Author Tags

    1. CNT
    2. DWCNT
    3. Delay
    4. Interconnects
    5. MWCNT
    6. Performance
    7. SWCNT

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