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In recent years, the application of deep learning (DL) models has sparked considerable interest in timing prediction within the place-and-route (P&R) flow of IC chip design. Specifically, at the pre-route stage, an accurate prediction of post-...

• We proposed a net and arc GNN (Graph Neural Network) model that considers the relationships with neighboring nets and arcs.
• Our model takes into account the surrounding environment with precision by considering the relationships with ...

Transient analysis, limited by the variability of process-induced physical and geometrical parameters in the capacitively coupled Li-doped MLGNR interconnects operating at the subthreshold mode, is the subject of this paper. An analytical approach ...

Because of their unique properties, different varieties of carbon nanotubes (CNTs), either pure or hybrid, have been proposed as a promising substitute for interconnects in several industrial applications. In this study, a new FDTD-based method ...

A simplified equivalent distributed temperature-dependent RLC circuit model of coupled multilayer graphene nanoribbon (MLGNR) interconnects has been discussed by considering the relaxation time induced mean free path (MFP), and its ...

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the ...

With the feasibility to scale the devices and interconnects in highly sophisticated VLSI technology, the demand for high-speed and low-power e-applications have also subsequently increased stupendously. Based on the applications and ...

Durable and reliable fabrication of on-skin systems remains an open research question to enable developing on-skin interfaces at scale. One of the main challenges is the complexity in achieving robust devices to connect hard goods (printed circuit ...

A comprehensive analysis is carried out herein on the impact of the interconnect geometry with nanoscale dimensions on the crosstalk-induced gate oxide reliability in coupled multilayer graphene nanoribbon (MLGNR) interconnects. Simplified circuit ...

STT-MRAM has emerged as versatile memory technology, capable of serving a broad range of memory applications. A key figure of merit for the STT-MRAM device is the tunneling magnetoresistance ratio (TMR), which distinguishes between the ...

A novel and highly accurate finite-difference time-domain model is developed for bundled single-walled carbon nanotube (SWCNT) interconnects by considering a fixed configuration that consists of a CMOS driver, a bundled SWCNT interconnect system, and an ...

In order to analyse crosstalk delay and stability in single wall carbon nanotube bundle (SWCNT) interconnects, the time and frequency domain response are investigated in this paper. Based on the transmission line model and by using matrix formulation, ...

In this work, spin coating driven self-assembly of C60 fullerenes on copper based substrates has been investigated. In particular, the substrates investigated include chemically and thermally pre- treated copper, electropolished copper and graphene ...

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization ...

A comparative performance analysis in terms of delay, power dissipation, power delay product (PDP), and crosstalk noise between SWCNT bundle interconnects with resistance estimated using conventionally (temperature independent model), and thermally ...

This paper addresses the impact of interlayer resistance due to c-axis resistivity and contact resistance on performance in terms of delay, power dissipation and power delay product (PDP) of Multi-layer graphene nanoribbon (MLGNR) interconnect. The ...

In this work, we evaluate the material properties of graphene and assess the potential application of graphene to replace copper wires in Back-End-Of-Line (BEOL) interconnects. Based on circuit and system-level simulations, high restrictions are imposed ...

Latest developments in electronic systems lead hardware architects to completely rethink the traffic exchanges inside Systems on Chip. Constraints on more parallelism, less power, more coherency, less order while designing system fabrics and ...

Ultra-low power designs extensively exploit the sub-threshold region of operation of Complementary metal-oxide semiconductor (CMOS) circuits. Though sub-threshold circuit operation shows huge potential towards satisfying the ultra-low power requirement, ...

In this paper, an analytical framework to model crosstalk in sub-threshold regime of buffer driven coupled interconnects has been presented. Sub-threshold current model is used to represent the transistor. Propagation delay and timing are determined for ...

Ultra-low power circuit design has received a wide attention due to the fast growth and prominence of portable battery-operated devices with stringent power constraint. Though sub-threshold circuit operation shows huge potential toward satisfying the ...