COP400

National Semiconductor COP400

National Semiconductor COP420 in 28-pin plastic DIP. Late 1982 date code.
General information
Launched	1977;47 years ago (1977)
Common manufacturer	National Semiconductor Western Digital
Performance
Max. CPU clock rate	to 250 KHz
Data width	4 (RAM), 8 (ROM)
Address width	7 (RAM), 11 (ROM)
Architecture and classification
Application	Embedded
Instruction set	COP400
Number of instructions	40
Physical specifications
Package	24, 28, 40-pin DIP
History
Predecessor	MM5799 (PMOS COP)
Successor	COP8

The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller. ^[1] COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. ^[2] Some COP400 devices were second-sourced by Western Digital as the WD4200 family. ^{[3] [4]} In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series (e.g. the COP402 with designation КР1820ВЕ1). ^[5]

Contents

• Memory
• ROM
• RAM
• CPU registers
• I/O registers and ports
• Baseline
• High end
• Instruction set
• Example code
• Interrupt
• Architectural extensions
• Dual CPU
• Return stack in RAM
• Larger address space
• Applications
• Intellectual property
• Emulator
• See also
• References

The COP400 is implemented in CMOS or N-channel silicon gate MOS technology. It was typically packaged in 24- or 28-pin DIP packages. Instruction cycle time of the faster family members is 4 microseconds. The COP400 family offered several memory and pinout configurations.

Notable products that used COP400-family chips include the Apple Lisa, Milton Bradley and Mattel electronic games, Coleco Head to Head Basketball, the Grundy Newbrain, and others.

Memory

The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum.

CPU registers

The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 × 8 bits) and RAM (128 × 4 bits). Family members with only 512 or 1024 bytes of ROM will have only a 9- or 10-bit PC. Those with 64 or 32 locations of RAM will have only a 2-bit Br register. Some low end family members omit the SC stack register. ^[6]

The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register.

A 4-bit ALU performs the arithmetic and logic functions, storing results in A. ASC and CASC operations output a carry to the 1-bit C register, most often employed to indicate arithmetic overflow.

All ROM addressing is accomplished via the 9-, 10-, or 11-bit PC register. Its binary value selects one of the bytes contained in ROM, usually the next program instruction. The value of PC is automatically incremented by 1 prior to the execution of the current instruction to point to the next sequential ROM location, unless the current instruction is a transfer of control instruction. In the latter case, PC is loaded with the appropriate non-sequential value to implement the transfer of control operation. The PC automatically rolls over to point to the next 64 byte page or 256 byte block of program memory. The upper 1, 2, or 3 bits of PC are also used in the JID and LQID instructions.

Three levels of subroutine are implemented by the subroutine save registers, SA, SB, and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. Some implementations do not have a SC.

I/O registers and ports

There are no port numbers or memory addresses associated with the COP400 I/O devices. All the physical I/O registers and ports are referenced by the COP400 assembly language directly by name.

Instruction set

The COP400 family is designed to have very compact code. The most frequently used instructions are one byte. In some cases there are special one-byte forms of two byte instructions. Some features that can be used to make object code more compact are:

• The LBI instruction loads the seven-bit B register with an immediate value. The general-form instruction takes two bytes. There is a one-byte form of LBI that can only set Br to 0, 1, 2, and 3 and can only set Bd to 9, 10, 11, 12, 13, 14, 15, and 0 (decimal). The single byte LBI can only access 32 RAM locations.
• Multiple LBI instructions can be stacked in series. Only the first LBI will be executed. Subsequent LBI instructions will execute as NOPs. This allows multiple entry points with different starting addresses for a shared routine.
• JSR, in the general subroutine branch form, is two bytes and can access any memory location directly. JSRP is a single byte form of subroutine branch that can access only the locations in the third 64-byte page. This page is called the subroutine page or page 2, numbered from zero. A JSRP cannot be coded from inside page 2 or 3.
• JMP, in the general branch form, is two bytes and can access any memory location directly. JP is a single byte form of branch that can access any location in the current 64-byte page. The upper bits of PC remain unchanged. If the JP instruction is executed inside page 2 or 3, then it can access any of the 128 addresses in pages 2 and 3. This is useful for creating a one byte JSRP entry point in page 2 that can then branch to a subroutine on page 3 with a single byte JP.
• The B register can be used to point to up to four RAM strings with little overhead. The LD, X, XIS, and XDS memory access instructions can Exclusive OR the lower two bits of Br with a two-bit immediate. This allows the register portion of B (Br) to be flipped to one of the other digit strings that share the same digit (Bd) address.
• The Bd register portion can be used as a memory pointer and a loop counter simultaneously. The XIS instruction will skip if Bd, after incrementing, overflows to zero, falling through the loop. Likewise the XDS instruction will skip if Bd, after decrementing, underflows to 15 (decimal).

Types supported: Type 1 is very low-end such as COP410. Type 2, such as the COP420, is most common. Type 3 typically have resources to support 40 pins even if package does not have 40 pins. Type 4 is not shown as there is no evidence that Type 4 was produced.

            040 09      041 19      042 2F       043 15      044 14      045 C3      046 48 

; Copy a block of memory from one location to another.;; There are three entry points: copyA, copyB, and copyC.; The values of the LBI instructions are expressed as; LBI Br, Bd.;copyA:LBI0,10;Copy 6 nybbles starting 0,10 to 1,10copyB:LBI1,10;Copy 6 nybbles starting 1,10 to 0,10copyC:LBI2,0;Copy 16 nybbles starting 2,0 to 3,0loop:LD1;Load src in A. XOR Br with 1 to get destXIS1;Save A in dest. Inc Bd. XOR Br with 1 to get srcJPloop;loop until Bd goes past last digit locationRET

Interrupt

Early COP400 devices that have 28 pins or more support a single interrupt. The IN 1 line is used as the interrupt input. Interrupt is enabled by setting bit 1 of the EN register to 1 with a LEI instruction. In response to low-going pulse of at least two instruction cycles long on IN 1, all transfer of control instructions such as JP are completed and all sequential LBI instructions are executed. The PC is then pushed on the subroutine stack and control is transferred to the interrupt handler at address 0xFF. No subroutines may be called in the interrupt service routine on devices with a hardware stack. ^[6] Curiously, later devices such as the COP440 support four interrupt sources and two service routines but only one interrupt source can be selected at a time. Subroutines are supported inside interrupt service routines on devices with a stack pointer.

Architectural extensions

Although the majority of COP400 devices were targeted at low-end applications, several extensions to the architecture were created to address more demanding applications. Dual CPU, a deeper stack in RAM, and larger address spaces were added to some devices by 1985. ^[7]

Applications

• Apple Lisa utilized a COP421 to control the keyboard, mouse, RTC, and soft power switch. A second COP421 controls the spindle motor of the Widget hard disk drive. ^[8]
• Several manufacturers used COP400 in their early electronic games: ^[9]
  • COP410 and COP411, 512 byte ROM, 32 x 4 RAM: Mattel's Funtronics Jacks, Red Light Green Light, Tag, and Plus One.
  • COP420 and COP421, 1024 byte ROM, 64 x 4 RAM: Milton Bradley Lightfight and Electronic Battleship 1982. Castle Toy Company Einstein. Coleco Head to Head Basketball. National Semiconductor Quiz Kid Racer. LJN Toys Ltd I Took a Lickin' from a Chicken.
  • COP444, 2048 byte ROM, 128 x 4 RAM: Entex Space Invader. Mattel Dalla$, Texas Instruments My Little Computer. ^[10]
• Western Digital used a WD4200 (COP420) as the basis for their WD2412 time-of-day clock. ^[11]
• The Grundy Newbrain computer uses a COP420 to manage its keyboard, tape I/O, and its built-in 16 character VF alphanumeric display. ^[12]

Intellectual property

T400 μController is an open source implementation of the COP400 microcontroller written in VHDL. COP420/421 and COP410L/411L devices are supported. T400 is intended to be a replacement for the original chip in SOCs recreating legacy systems. T400 has been implemented in several FPGA families. T400 is available under GNU General Public License. ^[13]

Emulator

There is an open-source MAME emulator for the COP400 family and several hand held games and specialty calculators. ^{[14] [15]}

See also

• National Semiconductor COP8

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References