10 nm process

Semiconductor device fabrication
MOSFET scaling (process nodes)
0 20 μm  – 1968 0 10 μm  – 1971 00 6 μm  – 1974 00 3 μm  – 1977   1.5 μm  – 1981 00 1 μm  – 1984 800 nm  – 1987 600 nm  – 1990 350 nm  – 1993 250 nm  – 1996 180 nm  – 1999 130 nm  – 2001 0 90 nm  – 2003 0 65 nm  – 2005 0 45 nm  – 2007 0 32 nm  – 2009 0 28 nm  – 2010 0 22 nm  – 2012 0 14 nm  – 2014 0 10 nm  – 2016 00 7 nm  – 2018 00 5 nm  – 2020 00 3 nm  – 2022
Future 00 2 nm  ~ 2025
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
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In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the "10 nanometer process" as the MOSFET technology node following the "14 nm" node.

Contents

• Background
• Technology production history
• Process nodes
• Foundry
• DRAM "10 nm class"
• References

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; ^[1] neither gate length, metal pitch or gate pitch on a "10nm" device is ten nanometers. ^{[2] [3] [4]} For example, GlobalFoundries' "7 nm" processes are dimensionally similar to Intel's "10 nm" process. ^[5] TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.^{[ citation needed ]}

All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of "10 nm-class" chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of "10 nm" chips in 2016, and Intel later began production of "10 nm" chips in 2018.^{[ needs update ]}

Background

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM was projected to be 11  nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the "10 nm" node. ^{[6] [7]}

In 2011, Samsung announced plans to introduce the "10 nm" process the following year. ^{[8] [ needs update ]} In 2012, Samsung announced eMMC flash memory chips that are produced using the "10 nm" process. ^[9]

As of 2018, "10 nm" as it was generally understood was only in high-volume production at Samsung. GlobalFoundries had skipped "10 nm",^{[ needs update ]} Intel had not yet started high-volume "10 nm" production, due to yield issues,^{[ needs update ]} and TSMC had considered "10 nm" to be a short-lived node, ^[10] mainly dedicated to processors for Apple during 2017–2018, moving on to "7 nm" in 2018.^{[ needs update ]}

There is also a distinction to be made between "10 nm" as marketed by foundries and "10 nm" as marketed by DRAM companies.

Technology production history

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a "10 nm-class" process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm". ^[11] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at "10 nm". ^[12] The technology's main announced challenge at that time had been triple patterning for its metal layer. ^{[13] [14] [ needs update ]}

TSMC began commercial production of "10 nm" chips in early 2016, before moving onto mass production in early 2017. ^[15]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone, which used the company's version of the "10 nm" processor. ^{[16] [ needs update ]} On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the "10 nm" FinFET process. ^[17]

On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a "10 nm" FinFET process, containing 4.3 billion transistors on a die of 87.66 mm².

In April 2018, Intel announced a delay in volume production of "10 nm" mainstream CPUs until sometime in 2019. ^[18] In July, the exact time was further pinned down to the holiday season. ^[19] In the meantime, however, they did release a low-power "10 nm" mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled. ^{[20] [ needs update ]}

In June 2018 at VLSI 2018, Samsung announced their "11LPP" and "8LPP" processes. "11LPP" was a hybrid based on Samsung "14 nm" and "10 nm" technology. "11LPP" was based on their "10 nm" BEOL, not their "20 nm" BEOL like the "14LPP". "8LPP" was based on the "10LPP" process. ^{[21] [22] [ needs update ]}

Nvidia released their GeForce 30 series GPUs in September 2020. They were at that time made on a custom version of Samsung's "8 nm" process, called "Samsung 8N", with a transistor density of 44.56 million transistors per mm². ^{[23] [24] [ needs update ]}

Process nodes

DRAM "10 nm class"

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.^{[ citation needed ]} The "10 nm" foundry structures are generally much larger.^{[ citation needed ]}

Generally "10 nm class" refers to DRAM with a 10-19 nm feature size, and was first introduced c. 2016. As of 2020, there were three generations of "10 nm class" DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3). ^[42] 3rd Generation "1z" DRAM was first introduced c. 2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography; ^{[43] [44]} subsequent production did utilise EUV lithography. ^[45]

Beyond 1z Samsung named its next node (fourth generation "10 nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022)^{[ needs update ]}; whilst Micron referred^{[ needs update ]} to succeeding "nodes" as "D1α" and "D1β". ^[46] Micron announced volume shipment of 1α class DRAM in early 2021. ^[47]

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In semiconductor manufacturing, the "2 nm process" is the next MOSFET die shrink after the "3 nm" process node.

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References