US20070205472A1 - Formation of a disposable spacer to post dope a gate conductor - Google Patents

Formation of a disposable spacer to post dope a gate conductor Download PDF

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US20070205472A1
US20070205472A1 US11/697,371 US69737107A US2007205472A1 US 20070205472 A1 US20070205472 A1 US 20070205472A1 US 69737107 A US69737107 A US 69737107A US 2007205472 A1 US2007205472 A1 US 2007205472A1
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gate
layer
spacer
polysi
disposable
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US11/697,371
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David Horak
Toshiharu Furukawa
Akihisa Sekiguchi
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • This invention generally relates to semiconductor device manufacturing, and more particularly, the invention relates to a method of fabricating semiconductor devices having a reduced carrier-depletion effect of polysilicon (polySi) gate conductor. Even more specifically, the invention relates to the use of a fat disposable spacer, in such fabrication methods, to facilitate post-doping of the polySi gate conductor without disturbing the optimum source and drain doping profile for a high performance metal oxide semiconductor filed effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor filed effect transistor
  • the effective gate dielectric thicknesses (Tinv) of the order of 2 nm or less are required to improve short-channel behavior and to increase the on-current without increasing the off-current.
  • the contribution of carrier-depletion effect of the polySi gate conductor at the gate dielectric interface, the so called “polySi depletion effect,” to the effective gate dielectric thickness becomes significantly large when the Tinv is of the order of 2 nm or less. It has been recognized that it is important to dope the polySi gate heavily, particularly near the gate dielectric interface, to reduce the polySi depletion effect.
  • pre-doping One method to decouple the gate and S/D implant is known as “pre-doping” of PolySi.
  • the polySi is implanted prior to PolySi etching to define the gate conductor to boost polySi-doping levels.
  • the disadvantage of this method is that the PFET and NFET areas are doped using different species (e.g., boron and arsenic) which can cause these areas to etch differently during the PolySi etch. This is a serious concern for device length control of both NFET and PFET.
  • post-doping Another method to decouple the gate that has been used is known as post-doping with “anti-spacer.” It is called post-doping because the additional doping to the gate is made after the gate PolySi etching to avoid the problems associated with etching of the dual doped PolySi.
  • a planarizing polymer layer such as an anti-reflective coating material (ARC) is spun onto the wafer after the PolySi has been etched.
  • the ARC fills areas between the PolySi lines, which blocks the implant from going into the Si S/D regions while thin enough ARC is left on top of the PolySi.
  • the most serious drawback of this technique is that enough ARC material actually stays on top of the PolySi of either a wide PolySi line or dense multiple PolySi lines, which blocks the implant from going into the PolySi, where it is needed.
  • An object of this invention is to fabricate a semiconductor device having a reduced carrier-depletion effect of a polysilicon (polysi) gate conductor.
  • Another object of the invention is to use a fat disposable spacer, in a semiconductor fabrication process, to facilitate post-doping of the polySi gate conductor without disturbing the optimum source and drain doping profile for a high performance metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • the method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer.
  • This latter step includes the steps of forming a first gate layer on the dielectric layer, and forming a second layer on top of the first gate layer.
  • a disposable spacer is formed around the first and second gate layers. The increased stack height by addition of the second layer enables to form a wide disposable spacer.
  • the second layer is removed, and ions are implanted in the first gate layer to supply additional dopant to the polySi gate above the gate dielectric layer.
  • the wide disposable spacer keeps the implant away from the critical regions of S/D diffusion.
  • FIG. 1 shows portions of a semiconductor wafer with a poly Si gate and disposable poly Ge stack.
  • FIG. 2 shows a disposable spacer around the poly Si gate and disposable Poly Ge stack.
  • FIG. 3 illustrates an ion implantation process applied to the semiconductor wafer.
  • FIGS. 4 and 5 illustrate further ion implantation processes applied to the semiconductor wafer.
  • FIG. 6 shows the semiconductor wafer after further processing.
  • the present invention which provides a method of fabricating a MOSFET device in which additional doping of the polySi gate without disturbing the critical region of the source/drain regions of the extensions is achieved, will now be described in greater detail by referring to the drawings that accompany the present application. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals.
  • FIG. 1 illustrates portions of an initial structure that may be employed in the present invention.
  • the initial structure shown in FIG. 1 comprises semiconductor substrate 10 , a layer of gate dielectric 12 formed on a surface of semiconductor substrate 10 , and a patterned gate stack 14 formed on portions of gate dielectric 12 .
  • a multitude of stacks 14 are formed on dielectric 12 , however for the sake of simplicity, only one stack is shown in the drawings.
  • semiconductor substrate 10 comprises any semiconducting material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds.
  • Semiconductor substrate 10 may also include a layered substrate comprising the same or different semiconducting materials, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate.
  • the substrate may be of the n- or p-type depending on the desired device to be fabricated.
  • semiconductor substrate 10 may contain active device regions, wiring regions, isolation regions or other like regions that are typically present in MOSFET-containing devices. For clarity, these regions are not shown in the drawings, but are nevertheless meant to be included within substrate 10 .
  • semiconductor substrate 10 is comprised of Si.
  • a layer of gate dielectric material 12 such as a silicon oxide, silicon nitride, silicon oxynitride, high k material such as Al 2 O 3 , HfO 2 , ZrO 2 , or any combination and multilayers thereof, is then formed on a surface of semiconductor substrate 10 utilizing a conventional process well known in the art.
  • the layer of gate dielectric material may be formed by a thermal growing process such as oxidation, nitridation or oxynitridation or, alternatively, by utilizing a chemical vapor deposition (CVD), plasma-assisted CVD, evaporation or chemical solution deposition.
  • CVD chemical vapor deposition
  • gate dielectric 12 has a thickness of from about 1 to about 20 nm after deposition, with a thickness of from about one to about three nm being more highly preferred.
  • the gate dielectric material employed in the present invention may be a conventional dielectric material such as SiO 2 or Si 3 N 4 , SiO x N y , or alternatively, high-k dielectrics such as oxides of Ta, Zr, Hf, Al or combinations thereof may be employed.
  • gate dielectric 12 is comprised of an oxide such as SiO 2 , or oxynitride SiO x N y , Al 2 O 3 (aluminum oxide)or HfSi x O y (hafnium silicate).
  • each gate stack is comprised of two layers 20 and 22 , one on top of the other.
  • the first layer 20 is comprised of intrinsic polycrystalline or so called poly silicon
  • the second layer 22 is comprised of polycrystalline or so called poly germanium.
  • each layer may be about 50 to 150 nm in height. The thicker the polySi layer, the more difficult it is to heavily dope the polySi near the gate dielectric 12 without degrading the S/D diffusion profile, since the higher energy implantation is required to heavily dope the polySi near the gate dielectric.
  • the gate stack 14 is positioned by using conventional lithography and etching steps. The photoresist used is stripped after the etch to form the gate stack structure shown in FIG. 1 .
  • gate material denotes a conductive material, a material that can be made conductive via a subsequent process such as ion implantation, or any combination thereof.
  • suitable gate materials include, but are not limited to: polysilicon, amorphous silicon or polysilicon germanium.
  • the gate material is formed on the surface of gate dielectric 12 utilizing conventional deposition processes well known in the art including, but not limited to: CVD, or plasma-assisted CVD.
  • an oxide/nitride line 24 is deposited on the stack and on the semiconductor substrate 10 immediately around the gate stack.
  • an oxide, disposable space 26 is formed around the gate stack 14 by conformally depositing the oxide and directionally etching the oxide by reactive ion etching (RIE).
  • the RIE removes the liner 24 and spacer 26 from the top of the gate stack 14 and the exposed Si substrate area.
  • the disposable layer 22 of at least the same thickness as, or thicker than, that of polySi layer 20 , was added and the at least 2 ⁇ fatter space 26 was formed so that the deep polySi doping implantation (discussed below) is kept away from the critical region of S/D diffusion near the extension.
  • the disposable poly Ge layer 22 is removed from gate stack 14 ; and this may be done, for example, by a H 2 O 2 or HNO 3 etching process, while the PFET area is covered by a photo resist.
  • an As or P deep ion implantation process 100 is employed to dope the N+ polySi layer 20 .
  • the implant goes into the substrate 10 , forming extension regions 30 , but it is kept sufficiently away from the active device area by the fat spacer 26 .
  • spacer 26 and the liner 24 may be removed and second n+ and p+ extensions 34 are formed by ion implantation 102 with using blocking photoresist mask (not shown in the figure) and spacers 36 .
  • This second spacer 36 may be formed using any suitable procedure, and, for instance, the spacer may be formed using a CVD oxide deposition and directional etch process.
  • n+ and p+ source/drain diffusion regions 30 are doped by ion implantation 104 with the third spacer 40 formed over spacer 36 and with using blocking photoresist mask (not shown in the Figure).
  • CoSi 2 or NiSi layer 42 may be formed on top of the semiconductor substrate 10 and the top of PolySi gate conductor. Conventional semiconductor fabrication techniques may be used to form silicide layer 42 . Passivation insulator is formed over the device, and then contacts and metal wiring are formed to make working CMOS circuits.
  • the process described here is one of the preferred embodiments and the process sequence may be varied to achieve the same results.
  • the S/D extension implantations can be made right after the deposition of the liner layer 24 as a spacer before the formation of the fat disposable spacer 26 .
  • hollow implantations which are not an essential part of the present invention, may be made at the same process step as the extension ion implantations.

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Abstract

A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • The present application is a divisional application of application Ser. No. 10/752,386, filed Jan. 6, 2004.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention generally relates to semiconductor device manufacturing, and more particularly, the invention relates to a method of fabricating semiconductor devices having a reduced carrier-depletion effect of polysilicon (polySi) gate conductor. Even more specifically, the invention relates to the use of a fat disposable spacer, in such fabrication methods, to facilitate post-doping of the polySi gate conductor without disturbing the optimum source and drain doping profile for a high performance metal oxide semiconductor filed effect transistor (MOSFET).
  • 2. Background Art
  • With decreasing gate lengths in metal oxide semiconductor field effect transistors (MOSFETs), the effective gate dielectric thicknesses (Tinv) of the order of 2 nm or less are required to improve short-channel behavior and to increase the on-current without increasing the off-current. The contribution of carrier-depletion effect of the polySi gate conductor at the gate dielectric interface, the so called “polySi depletion effect,” to the effective gate dielectric thickness becomes significantly large when the Tinv is of the order of 2 nm or less. It has been recognized that it is important to dope the polySi gate heavily, particularly near the gate dielectric interface, to reduce the polySi depletion effect. However, with the conventional manufacturing process, where the gate polySi and S/D diffusion are implanted at the same time, it is not possible to dope the polySi gate in such a way to minimize the polySi depletion effect without compromising the optimum source and drain (S/D) diffusion doping profile, because the polySi and S/D diffusion are doped by the same ion implantations. It is desirable to decouple the PolySi and S/D implantation so that they can be optimized separately.
  • One method to decouple the gate and S/D implant is known as “pre-doping” of PolySi. The polySi is implanted prior to PolySi etching to define the gate conductor to boost polySi-doping levels. The disadvantage of this method is that the PFET and NFET areas are doped using different species (e.g., boron and arsenic) which can cause these areas to etch differently during the PolySi etch. This is a serious concern for device length control of both NFET and PFET.
  • Another method to decouple the gate that has been used is known as post-doping with “anti-spacer.” It is called post-doping because the additional doping to the gate is made after the gate PolySi etching to avoid the problems associated with etching of the dual doped PolySi. With the post-doping method with anti-spacer, a planarizing polymer layer such as an anti-reflective coating material (ARC) is spun onto the wafer after the PolySi has been etched. The ARC fills areas between the PolySi lines, which blocks the implant from going into the Si S/D regions while thin enough ARC is left on top of the PolySi. However, the most serious drawback of this technique is that enough ARC material actually stays on top of the PolySi of either a wide PolySi line or dense multiple PolySi lines, which blocks the implant from going into the PolySi, where it is needed.
    • SUMMARY OF THE INVENTION
  • An object of this invention is to fabricate a semiconductor device having a reduced carrier-depletion effect of a polysilicon (polysi) gate conductor.
  • Another object of the invention is to use a fat disposable spacer, in a semiconductor fabrication process, to facilitate post-doping of the polySi gate conductor without disturbing the optimum source and drain doping profile for a high performance metal oxide semiconductor field effect transistor (MOSFET).
  • These and other objectives are attained with a method of forming a doped gate structure on a semiconductor device, and a semiconductor structure formed in that method. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second layer on top of the first gate layer. A disposable spacer is formed around the first and second gate layers. The increased stack height by addition of the second layer enables to form a wide disposable spacer. The second layer is removed, and ions are implanted in the first gate layer to supply additional dopant to the polySi gate above the gate dielectric layer. The wide disposable spacer keeps the implant away from the critical regions of S/D diffusion.
  • Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows portions of a semiconductor wafer with a poly Si gate and disposable poly Ge stack.
  • FIG. 2 shows a disposable spacer around the poly Si gate and disposable Poly Ge stack.
  • FIG. 3 illustrates an ion implantation process applied to the semiconductor wafer.
  • FIGS. 4 and 5 illustrate further ion implantation processes applied to the semiconductor wafer.
  • FIG. 6 shows the semiconductor wafer after further processing.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention, which provides a method of fabricating a MOSFET device in which additional doping of the polySi gate without disturbing the critical region of the source/drain regions of the extensions is achieved, will now be described in greater detail by referring to the drawings that accompany the present application. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals.
  • Reference is first made to FIG. 1 which illustrates portions of an initial structure that may be employed in the present invention. Specifically, the initial structure shown in FIG. 1 comprises semiconductor substrate 10, a layer of gate dielectric 12 formed on a surface of semiconductor substrate 10, and a patterned gate stack 14 formed on portions of gate dielectric 12. It should be noted that preferably a multitude of stacks 14 are formed on dielectric 12, however for the sake of simplicity, only one stack is shown in the drawings.
  • The structure shown in FIG. 1 is comprised of conventional materials well know in the art and it is fabricated utilizing processing steps that are also well known in the art. For example, semiconductor substrate 10 comprises any semiconducting material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds. Semiconductor substrate 10 may also include a layered substrate comprising the same or different semiconducting materials, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate. The substrate may be of the n- or p-type depending on the desired device to be fabricated.
  • Additionally, semiconductor substrate 10 may contain active device regions, wiring regions, isolation regions or other like regions that are typically present in MOSFET-containing devices. For clarity, these regions are not shown in the drawings, but are nevertheless meant to be included within substrate 10. In one highly preferred embodiment of the present invention, semiconductor substrate 10 is comprised of Si.
  • Next, a layer of gate dielectric material 12 such as a silicon oxide, silicon nitride, silicon oxynitride, high k material such as Al2O3, HfO2, ZrO2, or any combination and multilayers thereof, is then formed on a surface of semiconductor substrate 10 utilizing a conventional process well known in the art. For example, the layer of gate dielectric material may be formed by a thermal growing process such as oxidation, nitridation or oxynitridation or, alternatively, by utilizing a chemical vapor deposition (CVD), plasma-assisted CVD, evaporation or chemical solution deposition.
  • The thickness of the layer of the gate dielectric material formed at this point of the present invention is not critical to the present invention, but typically, gate dielectric 12 has a thickness of from about 1 to about 20 nm after deposition, with a thickness of from about one to about three nm being more highly preferred. It is noted that the gate dielectric material employed in the present invention may be a conventional dielectric material such as SiO2 or Si3N4 , SiOxNy, or alternatively, high-k dielectrics such as oxides of Ta, Zr, Hf, Al or combinations thereof may be employed. In one highly preferred embodiment of the present invention, gate dielectric 12 is comprised of an oxide such as SiO2, or oxynitride SiOxNy, Al2O3 (aluminum oxide)or HfSixOy (hafnium silicate).
  • After forming gate dielectric 12 on a surface of semiconductor substrate 10, a plurality of gate stacks 14 are formed atop the layer of gate dielectric. As shown in FIG. 1, each gate stack is comprised of two layers 20 and 22, one on top of the other. Preferably, the first layer 20 is comprised of intrinsic polycrystalline or so called poly silicon, and the second layer 22 is comprised of polycrystalline or so called poly germanium. Also, for example, each layer may be about 50 to 150 nm in height. The thicker the polySi layer, the more difficult it is to heavily dope the polySi near the gate dielectric 12 without degrading the S/D diffusion profile, since the higher energy implantation is required to heavily dope the polySi near the gate dielectric. The gate stack 14 is positioned by using conventional lithography and etching steps. The photoresist used is stripped after the etch to form the gate stack structure shown in FIG. 1.
  • The term “gate material” as used herein denotes a conductive material, a material that can be made conductive via a subsequent process such as ion implantation, or any combination thereof. Illustrative examples of suitable gate materials that can be employed in the present invention include, but are not limited to: polysilicon, amorphous silicon or polysilicon germanium.
  • The gate material is formed on the surface of gate dielectric 12 utilizing conventional deposition processes well known in the art including, but not limited to: CVD, or plasma-assisted CVD.
  • With reference to FIG. 2, after gate stack 14 is formed, an oxide/nitride line 24 is deposited on the stack and on the semiconductor substrate 10 immediately around the gate stack. After this, an oxide, disposable space 26 is formed around the gate stack 14 by conformally depositing the oxide and directionally etching the oxide by reactive ion etching (RIE). The RIE removes the liner 24 and spacer 26 from the top of the gate stack 14 and the exposed Si substrate area. The disposable layer 22, of at least the same thickness as, or thicker than, that of polySi layer 20, was added and the at least 2× fatter space 26 was formed so that the deep polySi doping implantation (discussed below) is kept away from the critical region of S/D diffusion near the extension.
  • With reference to FIGS. 2 and 3, the disposable poly Ge layer 22 is removed from gate stack 14; and this may be done, for example, by a H2O2 or HNO3 etching process, while the PFET area is covered by a photo resist. After the poly Ge layer is removed, an As or P deep ion implantation process 100 is employed to dope the N+ polySi layer 20. The implant goes into the substrate 10, forming extension regions 30, but it is kept sufficiently away from the active device area by the fat spacer 26.
  • With reference to FIGS. 3 and 4, after the deep implant 100 to dope the poly Si layer, spacer 26 and the liner 24 may be removed and second n+ and p+ extensions 34 are formed by ion implantation 102 with using blocking photoresist mask (not shown in the figure) and spacers 36. This second spacer 36 may be formed using any suitable procedure, and, for instance, the spacer may be formed using a CVD oxide deposition and directional etch process.
  • With reference to FIG. 5, after the n+ and p+ extension implantation, n+ and p+ source/drain diffusion regions 30 are doped by ion implantation 104 with the third spacer 40 formed over spacer 36 and with using blocking photoresist mask (not shown in the Figure).
  • Further processing steps may then be used to complete the fabrication of the semiconductor device. With reference to FIG. 6, CoSi2 or NiSi layer 42 may be formed on top of the semiconductor substrate 10 and the top of PolySi gate conductor. Conventional semiconductor fabrication techniques may be used to form silicide layer 42. Passivation insulator is formed over the device, and then contacts and metal wiring are formed to make working CMOS circuits.
  • The process described here is one of the preferred embodiments and the process sequence may be varied to achieve the same results. For example, the S/D extension implantations can be made right after the deposition of the liner layer 24 as a spacer before the formation of the fat disposable spacer 26. Also, hollow implantations, which are not an essential part of the present invention, may be made at the same process step as the extension ion implantations.
  • While it is apparent that the invention herein disclosed is well calculated to fulfill the objects stated above, it will be appreciated that numerous modifications and embodiments may be devised by those skilled in the art, and it is intended that the appended claims cover all such modifications and embodiments as fall within the true spirit and scope of the present invention.

Claims (6)

1-12. (canceled)
13. A semiconductor structure, comprising:
a substrate including a gate dielectric layer;
a gate stack on the gate dielectric layer, said gate stack including a first gate layer on the dielectric layer and comprised of a first material, and a second layer on top of the first gate layer and comprised of a second material different than the first material; and
a disposable spacer extending around the gate stack, and extending upward above the substrate to a level higher than the top of the first gate layer.
14. A semiconductor structure according to claim 13, wherein the disposable spacer thickness is equal or thicker than the first gate layer so that at least 2× fatter spacer is formed.
15. A semiconductor structure according to claim 13, wherein the spacer extends upward substantially to the top of the gate stack.
16. A semiconductor structure according to claim 13, further comprising a liner deposited on the gate stack between the gate stack and the spacer.
17. A semiconductor structure according to claim 16, wherein said liner is also deposited on the semiconductor substrate, between said substrate and the spacer.
US11/697,371 2004-01-06 2007-04-06 Formation of a disposable spacer to post dope a gate conductor Abandoned US20070205472A1 (en)

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US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US6489207B2 (en) * 1998-05-01 2002-12-03 International Business Machines Corporation Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor
US6531365B2 (en) * 2001-06-22 2003-03-11 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
US6534351B2 (en) * 2001-03-19 2003-03-18 International Business Machines Corporation Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices
US20030181028A1 (en) * 2002-03-19 2003-09-25 Yeap Geoffrey C-F Integrated circuit device and method therefor

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US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US6489207B2 (en) * 1998-05-01 2002-12-03 International Business Machines Corporation Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor
US6534351B2 (en) * 2001-03-19 2003-03-18 International Business Machines Corporation Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices
US6531365B2 (en) * 2001-06-22 2003-03-11 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
US20030181028A1 (en) * 2002-03-19 2003-09-25 Yeap Geoffrey C-F Integrated circuit device and method therefor
US20040124450A1 (en) * 2002-03-19 2004-07-01 Yeap Geoffrey C-F Integrated circuit device and method therefor

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