US20060213778A1 - Method for electrochemical plating on semiconductor wafers - Google Patents

Method for electrochemical plating on semiconductor wafers Download PDF

Info

Publication number
US20060213778A1
US20060213778A1 US11/089,404 US8940405A US2006213778A1 US 20060213778 A1 US20060213778 A1 US 20060213778A1 US 8940405 A US8940405 A US 8940405A US 2006213778 A1 US2006213778 A1 US 2006213778A1
Authority
US
United States
Prior art keywords
current
wafer
level
stages
increasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/089,404
Inventor
Hsi-Kuei Cheng
Steven Lin
Chih-Chang Huang
Tzu-Ling Liao
Hsien-Ping Peng
Ming-Yuan Cheng
Ying-Jing Lu
Chieh-Tsao Wang
Ray Chuang
Chen-Peng Fan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US11/089,404 priority Critical patent/US20060213778A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, HSI-KUEI, CHENG, MING-YUAN, CHUANG, RAY, FAN, CHEN-PENG, FENG, HSIEN-PING, HUANG, CHIH-CHANG, LIAO, TZU-LING, LIN, STEVEN, LU, YING-JING, WANG, CHIEH-TSAO
Publication of US20060213778A1 publication Critical patent/US20060213778A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/615—Microstructure of the layers, e.g. mixed structure
    • C25D5/617—Crystalline layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Definitions

  • This invention generally relates to electrodeposition of conductive films on semiconductor wafers, and deals more particularly with an improved method of controlling the electroplating current in order to better control grain size and improve film quality.
  • Many typical phototolithographic integrated circuit chip fabrication processes include a deposition phase in which material of different electrical characteristics is deposited in a space created in a diffusion material.
  • Deposition phases of lithographic processes are often utilized to create components such as resistors, diodes and transistors, and electrical interconnections between components.
  • Current technology electrical connections often include lines and plugs that are deposited in dielectric layers of the wafer.
  • lines typically comprised aluminum, or an aluminum alloy, and plugs included tungsten.
  • interconnections comprising copper are becoming more prevelant. Copper interconnections typically provide several advantages over other materials, including lower electrical resistivity and better electromigration resistance.
  • Electrochemical deposition of copper is a leading technology because of its low cost, fast deposition rate, and superior copper properties. Copper interconnect electrodeposition faces a number of challenges in the form of non-uniformity of the copper layer over the wafer and filling small, high aspect ratio contactless without void formation.
  • Electrochemical plating techniques and apparatus are well developed in the art.
  • the electrochemical deposition of copper is caused by the passage of the electrical current between two electrodes through a copper sulfate solution or other copper containing electrolytes.
  • the electrical current to the electrode is electronic, while the current in the electrolyte is ionic.
  • electrochemical reduction occurs, while electrochemical oxidation occurs at the anode which is normally formed of copper.
  • copper ions removed at the cathode are replaced by copper ions produced at the anode. Copper ions are transported to the cathode by electrical drift, diffusion and convection.
  • Electroplating can be carried out at constant current, constant voltage or variable forms of current or voltage.
  • the distribution of current, and hence the distribution of the thickness of the copper layer across the cathode depends on its geometry, the kinetics of the electrochemical reaction and concentration variations, as determined by the hydrodynamics and the convection mass transport in the electrolyte.
  • the SiO 2 -covered wafer is coated with a thin conductive layer of copper, normally referred to as the seed layer, in order to assure electronic conductivity.
  • the wafer is exposed to an electrolyte containing copper ions and the electrical contact is established between the seed layer and the power supply by several contact points along the periphery of the wafer. Constant current is passed for a certain length of time, resulting in a corresponding thickness of the copper layer.
  • Copper electroplating is usually obtained from an aqueous solution of CUSO 4 and H 2 SO 4 , in the presence of several additives and leveling agents. Additives such as accelerators and suppressors are used to control the deposition rate and assure void-free filling of the sub-.25 micron high aspect ratio structures.
  • the electroplated copper film is formed in several distinct stages in which differing amounts of current, and sometimes voltages, are applied to achieve different deposition rates and microstructure formation.
  • the electrical current is switched almost instantly from one level to another as one stage is finished and the next stage is commenced, resulting in a step-like discontinuity in the applied current waveform.
  • grain size formation of the copper film is directly related to current density, consequently a sharp change in grain structure occurs when the current is switched from one level to another.
  • there is a relationship between the grain size and resistivity the larger the grain size, the lower the resistivity.
  • Edge pullback is a phenomenon where low or sometimes no copper plating occurs on the edges of adjacent surface features. Accordingly, it would be desirable to provide an improved process for electroplating conductive metal such as copper which yields a more uniform grain size, avoids local stresses in the plated film, and increases the window for the thermal budget in post processing of the plated wafer.
  • the present invention is directed toward satisfying this need.
  • a method for a electroplating conductive materials such as copper on a semiconductor wafer comprising the steps of immersing the wafer in a plating bath; applying a continuous DC current to the wafer in order to effect electroplating of the material onto the wafer; increasing the magnitude of the DC current over time as the DC current is being continuously applied to the wafer.
  • the DC current is increased gradually between successive stages of the plating process. These gradual increases in the applied electrical current are preferably linear.
  • a method of electroplating and conductive material on a semiconductor wafer comprises the steps of immersing the wafer in a plating bath; applying a continuously positive DC current to the wafer in each of a plurality of separate stages in order to achieve differing plated material structures on the wafer; and, gradually increasing the applied current between the stages to avoid discontinuities in the current flow to the wafer.
  • FIG. 1 is a graph showing the current applied in a prior art, multistage electroplating process
  • FIG. 2 is a view similar to FIG. 1 , but showing the applied current when using the method forming a preferred embodiment of the present invention.
  • FIG. 3 is a graph showing the applied plating current.
  • a more uniform and continuous grain structure is achieved throughout the plated film.
  • thermal stresses within the film are reduced, and overall film quality is improved.
  • the more robust Cu film will not shrink or expand even by the high thermal budget of post process.
  • a typical process for electroplating copper on a semiconductor wafer began with depositing a barrier layer of a material such as tantalum nitride by means of sputtering.
  • a seed layer of copper is applied over the barrier layer using, for example, atomic layer deposition techniques.
  • the seed layer of copper is applied to assure good electrical contact and adhesion of subsequent layers of copper.
  • the seed layer of copper may be between 100 and 1000 angstroms, for example.
  • Copper electroplating is then performed using a conventional electroplating apparatus which includes a vessel (not shown) containing an aqueous solution of CuSO 4 and H 2 SO 4 , in the presence of various additives and leveling agents.
  • the wafer is held by flexibly mounted gripping fingers (not shown) on the bottom of a spinning clam shell support which rotates the wafer while submerged within the plating bath.
  • the wafer is electrically connected to a power source and acts as a cathode.
  • a copper anode disposed within the bath is also connected to the electrical power source.
  • Suitable pumps are used to create a flow of the plating bath over the face of the wafer as the latter is rotated up to speeds of 2000 rpms.
  • the “recipe” used to form the copper film calls for multiple steps or stages in which differing levels of electrical current are applied to the wafer for differing amounts of time. For example, one level of continuous or pulse current signals are delivered to the plating circuit as the wafer is initially being immersed, following which the current is increased to an intermediate but lower level but while the initial level of the film is being formed. Subsequently, the current is increased in order to accelerate the deposition process. These multiple stages are followed in order to obtain a desired grain structure and assure plating of specific wafer features, including filling gaps and trenches.
  • FIG. 1 One typical recipe used in the prior art is shown in FIG. 1 in which a series of alternating positive and negative current pulses 10 are initially applied, following which current is instantaneously increased at 12 to an initial, continuous level I 1 . After a desired period of time, the current is again instantaneously increased at 14 to a higher current level I 2 , and after another interval, time the current is finally increased in an instantaneous, step like fashion at 16 to highest level of current I 3 . From FIG. 1 it can be seen that a series of “discontinuities” occur in the applied current, respectively at 12 , 14 and 16 . These discontinuities and the rapid changes in current flow result in relatively sharp boundaries between grain structures of differing sizes. These relatively sharp boundaries and differing grain structures produce stresses in the microstructure of the film which can impair film quality and even result in film defects.
  • a novel method of electroplating conductive material on a semiconductor wafer controls transition in the applied current during successive stages of the electroplating process which substantially reduces or eliminates sharp changes in the grain structure of the plated film.
  • an initial, positive, continuous level of current is applied to the plating circuit at 18 for an initial period of time which could be considered the first step or stage in the plating recipe cycle.
  • the current is then gradually increased at 20 , in a straight line or linear fashion over a period of time until the current increases to a second, higher level I 1 representing the second stage in the plating cycle.
  • the current is increased from I 1 to a higher level I 2 in a gradual, linear manner indicated at 22 .
  • the current is increased from I 2 in a linear, gradual manner designated at 24 until current level I 3 is achieved representing the fourth and final stage of the plating process.
  • I 3 current level
  • the first stage indicated at 18 an initial, thin film layer is formed.
  • the second stage the thickness of the film is increased at a more rapid deposition rate.
  • the time-current recipe is selected primarily to fill gaps following which the thickness of the film is increased until the last stage is reached which is particularly directed at filling trenches.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of electroplating conductive material on semiconductor wafers improves deposited film quality by providing greater control over the formation of the film grain structure. Better grain size control is achieved by applying a continuous DC plating current to the wafer which avoids sharp discontinuities in the current as the applied current is increased in successive stages during a plating cycle. Current discontinuities are avoided by gradually increasing the current in a ramp-like fashion between the successive plating stages.

Description

    FIELD OF THE INVENTION
  • This invention generally relates to electrodeposition of conductive films on semiconductor wafers, and deals more particularly with an improved method of controlling the electroplating current in order to better control grain size and improve film quality.
    • BACKGROUND OF THE INVENTION
  • Many typical phototolithographic integrated circuit chip fabrication processes include a deposition phase in which material of different electrical characteristics is deposited in a space created in a diffusion material. Deposition phases of lithographic processes are often utilized to create components such as resistors, diodes and transistors, and electrical interconnections between components. Current technology electrical connections often include lines and plugs that are deposited in dielectric layers of the wafer. In the past, lines typically comprised aluminum, or an aluminum alloy, and plugs included tungsten. However, as component sizes become smaller and more layers of metallization are fabricated, interconnections comprising copper are becoming more prevelant. Copper interconnections typically provide several advantages over other materials, including lower electrical resistivity and better electromigration resistance. The techniques used to achieve copper metallization include CVD, selective electroless deposition, sputtering (PVD) and electroplating. Electrochemical deposition of copper is a leading technology because of its low cost, fast deposition rate, and superior copper properties. Copper interconnect electrodeposition faces a number of challenges in the form of non-uniformity of the copper layer over the wafer and filling small, high aspect ratio contactless without void formation.
  • Electrochemical plating techniques and apparatus are well developed in the art. The electrochemical deposition of copper is caused by the passage of the electrical current between two electrodes through a copper sulfate solution or other copper containing electrolytes. The electrical current to the electrode is electronic, while the current in the electrolyte is ionic. At the cathode, electrochemical reduction occurs, while electrochemical oxidation occurs at the anode which is normally formed of copper. In this arrangement, copper ions removed at the cathode are replaced by copper ions produced at the anode. Copper ions are transported to the cathode by electrical drift, diffusion and convection. Electroplating can be carried out at constant current, constant voltage or variable forms of current or voltage. The distribution of current, and hence the distribution of the thickness of the copper layer across the cathode depends on its geometry, the kinetics of the electrochemical reaction and concentration variations, as determined by the hydrodynamics and the convection mass transport in the electrolyte. In the case of copper electroplating on a silicon wafer, the SiO2-covered wafer is coated with a thin conductive layer of copper, normally referred to as the seed layer, in order to assure electronic conductivity. The wafer is exposed to an electrolyte containing copper ions and the electrical contact is established between the seed layer and the power supply by several contact points along the periphery of the wafer. Constant current is passed for a certain length of time, resulting in a corresponding thickness of the copper layer.
  • Because copper reacts with SiO2, it is necessary to confine it using a barrier layer material, such as tantalum nitride which is pre-deposited on the SiO2 by sputtering. The copper seed layer is then deposited in order to assure good electrical contact and adhesion. Copper electroplating is usually obtained from an aqueous solution of CUSO4 and H2SO4, in the presence of several additives and leveling agents. Additives such as accelerators and suppressors are used to control the deposition rate and assure void-free filling of the sub-.25 micron high aspect ratio structures.
  • Rather than supply a single level of current throughout the plating process in order to achieve a desired thickness of the copper film, the electroplated copper film is formed in several distinct stages in which differing amounts of current, and sometimes voltages, are applied to achieve different deposition rates and microstructure formation. The electrical current is switched almost instantly from one level to another as one stage is finished and the next stage is commenced, resulting in a step-like discontinuity in the applied current waveform. It is known that the grain size formation of the copper film is directly related to current density, consequently a sharp change in grain structure occurs when the current is switched from one level to another. It is also known that there is a relationship between the grain size and resistivity; the larger the grain size, the lower the resistivity.
  • Sharp changes in grain size, and thus of resistivity, is undesirable for a number of reasons, including the creation of unbalanced thermal stresses, for example that can result in defects such as so called “edge pullback.” Edge pullback is a phenomenon where low or sometimes no copper plating occurs on the edges of adjacent surface features. Accordingly, it would be desirable to provide an improved process for electroplating conductive metal such as copper which yields a more uniform grain size, avoids local stresses in the plated film, and increases the window for the thermal budget in post processing of the plated wafer. The present invention is directed toward satisfying this need.
    • SUMMARY OF THE INVENTION
  • According to one aspect of the invention, a method is provided for a electroplating conductive materials such as copper on a semiconductor wafer, comprising the steps of immersing the wafer in a plating bath; applying a continuous DC current to the wafer in order to effect electroplating of the material onto the wafer; increasing the magnitude of the DC current over time as the DC current is being continuously applied to the wafer. The DC current is increased gradually between successive stages of the plating process. These gradual increases in the applied electrical current are preferably linear.
  • According to another aspect of the invention, a method of electroplating and conductive material on a semiconductor wafer comprises the steps of immersing the wafer in a plating bath; applying a continuously positive DC current to the wafer in each of a plurality of separate stages in order to achieve differing plated material structures on the wafer; and, gradually increasing the applied current between the stages to avoid discontinuities in the current flow to the wafer.
  • As a result of the gradual increase of the current between successive stages, a more uniform and continuous grain structure is achieved throughout the plated film. As a result of the more uniform grain structure, thermal stresses within the film are reduced, and overall film quality is improved.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the drawings, which form an integral part of the specification and are to be read to the conjunction therewith, and in which like reference numerals are employed to designate identical components in the various views:
  • FIG. 1 is a graph showing the current applied in a prior art, multistage electroplating process;
  • FIG. 2 is a view similar to FIG. 1, but showing the applied current when using the method forming a preferred embodiment of the present invention; and,
  • FIG. 3 is a graph showing the applied plating current. As a result of the smooth, continuous current between successive stages, a more uniform and continuous grain structure is achieved throughout the plated film. As a result of the more uniform grain structure, thermal stresses within the film are reduced, and overall film quality is improved. The more robust Cu film will not shrink or expand even by the high thermal budget of post process.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring first to FIG. 1, a typical process for electroplating copper on a semiconductor wafer began with depositing a barrier layer of a material such as tantalum nitride by means of sputtering. Next, a seed layer of copper is applied over the barrier layer using, for example, atomic layer deposition techniques. The seed layer of copper is applied to assure good electrical contact and adhesion of subsequent layers of copper. The seed layer of copper may be between 100 and 1000 angstroms, for example. Copper electroplating is then performed using a conventional electroplating apparatus which includes a vessel (not shown) containing an aqueous solution of CuSO4 and H2SO4, in the presence of various additives and leveling agents. The wafer is held by flexibly mounted gripping fingers (not shown) on the bottom of a spinning clam shell support which rotates the wafer while submerged within the plating bath. The wafer is electrically connected to a power source and acts as a cathode. A copper anode disposed within the bath is also connected to the electrical power source. Suitable pumps are used to create a flow of the plating bath over the face of the wafer as the latter is rotated up to speeds of 2000 rpms.
  • Typically, the “recipe” used to form the copper film calls for multiple steps or stages in which differing levels of electrical current are applied to the wafer for differing amounts of time. For example, one level of continuous or pulse current signals are delivered to the plating circuit as the wafer is initially being immersed, following which the current is increased to an intermediate but lower level but while the initial level of the film is being formed. Subsequently, the current is increased in order to accelerate the deposition process. These multiple stages are followed in order to obtain a desired grain structure and assure plating of specific wafer features, including filling gaps and trenches.
  • One typical recipe used in the prior art is shown in FIG. 1 in which a series of alternating positive and negative current pulses 10 are initially applied, following which current is instantaneously increased at 12 to an initial, continuous level I1. After a desired period of time, the current is again instantaneously increased at 14 to a higher current level I2, and after another interval, time the current is finally increased in an instantaneous, step like fashion at 16 to highest level of current I3. From FIG. 1 it can be seen that a series of “discontinuities” occur in the applied current, respectively at 12, 14 and 16. These discontinuities and the rapid changes in current flow result in relatively sharp boundaries between grain structures of differing sizes. These relatively sharp boundaries and differing grain structures produce stresses in the microstructure of the film which can impair film quality and even result in film defects.
  • In accordance with the present invention a novel method of electroplating conductive material on a semiconductor wafer controls transition in the applied current during successive stages of the electroplating process which substantially reduces or eliminates sharp changes in the grain structure of the plated film. Referring to FIG. 2, in accordance to the present invention, an initial, positive, continuous level of current is applied to the plating circuit at 18 for an initial period of time which could be considered the first step or stage in the plating recipe cycle. The current is then gradually increased at 20, in a straight line or linear fashion over a period of time until the current increases to a second, higher level I1 representing the second stage in the plating cycle. Similarly, the current is increased from I1 to a higher level I2 in a gradual, linear manner indicated at 22. Finally, the current is increased from I2 in a linear, gradual manner designated at 24 until current level I3 is achieved representing the fourth and final stage of the plating process. Generally, during the first stage indicated at 18 an initial, thin film layer is formed. In the second stage the thickness of the film is increased at a more rapid deposition rate. During the third stage the time-current recipe is selected primarily to fill gaps following which the thickness of the film is increased until the last stage is reached which is particularly directed at filling trenches.
  • Applying a continuous, positive current to the wafer and gradually increasing the current from each level to a higher level has been found to provide a more continuous grain structure, free of sharp boundaries that can later result in thermal stresses causing defects or inadequate plating coverage. In contrast to the prior art method in which discontinuities are present in the current waveform, the current is applied in a continuous, smooth manner, free of sharp discontinuities.
  • As a result of the smooth, continuous current between successive stages, a more uniform and continuous grain structure is achieved throughout the plated film. As a result of the more uniform grain structure, thermal stresses within the film are reduced, and overall film quality is improved. The more robust Cu film will not shrink or expand even by the high thermal budget of post process.
  • From the forgoing, it is apparent that the novel method of electroplating conductive material on a semiconductor wafer not only provides for the reliable accomplishment of the objects of the invention but does so in a particularly simple and economical manner. Those skilled in the art will recognize that various modifications may be made to the embodiment chosen to illustrate the invention without departing from the spirit and scope of the present contribution of the art. Accordingly, it is to be understood that the protection sought and to be afforded hereby should be deemed to extend to the subject matter claimed in all equivalents thereof fairly within the scope of the invention.

Claims (20)

1. A method of electroplating conductive material on a semiconductor wafer, comprising the steps of:
(A) immersing the wafer in a plating bath;
(B) applying a continuous DC current to the wafer in order to effect electroplating of the material onto the wafer; and,
(C) increasing the magnitude of DC current over time as the DC current is being continuously applied to the wafer.
2. The method of claim 1, wherein:
step (C) includes increasing the applied DC current to each of a plurality of discrete current levels, and
step (B) includes gradually increasing the applied DC current between the discrete current levels.
3. The method of claim 1, wherein:
step (C) includes increasing the applied DC current from at least a first current level to a second current level, and
step (B) includes gradually ramping up the current from the first level to the second level.
4. The method of claim 2, wherein step (C) includes successively increasing the current in 3 stages to respectively deposit an initial film of the material on the wafer, fill gaps in the wafer and fill trenches in the wafer.
5. The method of claim 4, wherein step (B) includes gradually increasing the current between each of the stages.
6. The method of claim 1, wherein step (B) includes gradually ramping up the current between the successive stages.
7. The method of claim 5, wherein the gradual increase in current is essentially linear.
8. The method of claim 6, wherein each of the upward current ramps is linear.
9. The method of claim 1, wherein the continuously applied current in step (B) is a positive current.
10. The method of claim 1, wherein the material is copper.
11. A method of electroplating a conductive material on a semiconductor wafer, comprising the steps of:
(A) immersing the wafer in a plating bath;
(B) applying a continuously positive DC current to the wafer in each of a plurality of separate stages in order to achieve differing plated material structures on the wafer; and,
(C) gradually increasing the applied current between the stages to avoid discontinuities in the current flow to the wafer.
12. The method of claim 11, wherein:
step (B) includes increasing the applied DC current to each of a plurality of discrete current levels, and
step (C) includes gradually increasing the applied DC current between the discrete current levels.
13. The method of claim 11, wherein:
step (B) includes increasing the applied DC current from at least a first current level to a second current level, and
step (C) includes gradually ramping up the current from the first level to the second level.
14. The method of claim 12, wherein step (B) includes successively increasing the current in 3 stages to respectively deposit an initial film of the material on the wafer, fill gaps in the wafer and fill trenches in the wafer.
15. The method of claim 14, wherein the gradual increase of current in step (C) is linear.
16. The method of claim 11, wherein the gradual increase of current in step (C) is linear.
17. The method of claim 13, wherein the current is ramped linearly.
18. The method of claim 11, wherein the material is copper.
19. The method of claim 11, wherein step (B) the current is applied in 3 stages.
20. The method of claim 13, wherein the material is copper.
US11/089,404 2005-03-23 2005-03-23 Method for electrochemical plating on semiconductor wafers Abandoned US20060213778A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/089,404 US20060213778A1 (en) 2005-03-23 2005-03-23 Method for electrochemical plating on semiconductor wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/089,404 US20060213778A1 (en) 2005-03-23 2005-03-23 Method for electrochemical plating on semiconductor wafers

Publications (1)

Publication Number Publication Date
US20060213778A1 true US20060213778A1 (en) 2006-09-28

Family

ID=37034100

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/089,404 Abandoned US20060213778A1 (en) 2005-03-23 2005-03-23 Method for electrochemical plating on semiconductor wafers

Country Status (1)

Country Link
US (1) US20060213778A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080067072A1 (en) * 2006-08-18 2008-03-20 Semitool, Inc. Method and system for depositing alloy composition
US20090114530A1 (en) * 2007-11-01 2009-05-07 Tomohiro Noda Continuous plating apparatus
US20090283860A1 (en) * 2008-05-13 2009-11-19 Stmicroelectronics, Inc. High precision semiconductor chip and a method to construct the semiconductor chip
US20140262797A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Electro Chemical Plating Process
US20150035640A1 (en) * 2013-08-02 2015-02-05 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device
EP2624266A4 (en) * 2010-09-30 2017-12-27 Hitachi Metals, Ltd. Method for forming electric copper plating film on surface of rare earth permanent magnet
US10508358B2 (en) * 2012-09-17 2019-12-17 Government Of The United States Of America, As Represented By The Secretary Of Commerce Process for forming a transition zone terminated superconformal filling
US11579344B2 (en) 2012-09-17 2023-02-14 Government Of The United States Of America, As Represented By The Secretary Of Commerce Metallic grating

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603593A (en) * 1952-07-15 Electeodepositiqn of metaiis
US6409903B1 (en) * 1999-12-21 2002-06-25 International Business Machines Corporation Multi-step potentiostatic/galvanostatic plating control
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
US20040188265A1 (en) * 2003-03-25 2004-09-30 Yang Cao Methods for reducing protrusions and within die thickness variations on plated thin film
US6946065B1 (en) * 1998-10-26 2005-09-20 Novellus Systems, Inc. Process for electroplating metal into microscopic recessed features
US6974531B2 (en) * 2002-10-15 2005-12-13 International Business Machines Corporation Method for electroplating on resistive substrates

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2603593A (en) * 1952-07-15 Electeodepositiqn of metaiis
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
US6946065B1 (en) * 1998-10-26 2005-09-20 Novellus Systems, Inc. Process for electroplating metal into microscopic recessed features
US6409903B1 (en) * 1999-12-21 2002-06-25 International Business Machines Corporation Multi-step potentiostatic/galvanostatic plating control
US6974531B2 (en) * 2002-10-15 2005-12-13 International Business Machines Corporation Method for electroplating on resistive substrates
US20040188265A1 (en) * 2003-03-25 2004-09-30 Yang Cao Methods for reducing protrusions and within die thickness variations on plated thin film

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9359683B2 (en) * 2006-08-18 2016-06-07 Applied Materials, Inc. Method of forming metal and metal alloy features
US20080067072A1 (en) * 2006-08-18 2008-03-20 Semitool, Inc. Method and system for depositing alloy composition
US20090114530A1 (en) * 2007-11-01 2009-05-07 Tomohiro Noda Continuous plating apparatus
US8940137B2 (en) * 2007-11-01 2015-01-27 Almex Pe Inc. Continuous plating apparatus configured to control the power applied to individual work pieces within a plating tank
US20090283860A1 (en) * 2008-05-13 2009-11-19 Stmicroelectronics, Inc. High precision semiconductor chip and a method to construct the semiconductor chip
US8338192B2 (en) * 2008-05-13 2012-12-25 Stmicroelectronics, Inc. High precision semiconductor chip and a method to construct the semiconductor chip
EP2624266A4 (en) * 2010-09-30 2017-12-27 Hitachi Metals, Ltd. Method for forming electric copper plating film on surface of rare earth permanent magnet
US10770224B2 (en) 2010-09-30 2020-09-08 Hitachi Metals, Ltd. Method for forming electrolytic copper plating film on surface of rare earth metal-based permanent magnet
US10508358B2 (en) * 2012-09-17 2019-12-17 Government Of The United States Of America, As Represented By The Secretary Of Commerce Process for forming a transition zone terminated superconformal filling
US11579344B2 (en) 2012-09-17 2023-02-14 Government Of The United States Of America, As Represented By The Secretary Of Commerce Metallic grating
US11733439B2 (en) 2012-09-17 2023-08-22 Government Of The United States Of America. As Represented By The Secretary Of Commerce Process for making a metallic grating
US9476135B2 (en) * 2013-03-12 2016-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Electro chemical plating process
US20140262797A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Electro Chemical Plating Process
US20150035640A1 (en) * 2013-08-02 2015-02-05 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device
US10217563B2 (en) * 2013-08-02 2019-02-26 Cyntec Co., Ltd. Method of manufacturing multi-layer coil and multi-layer coil device

Similar Documents

Publication Publication Date Title
US6074544A (en) Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer
US6884335B2 (en) Electroplating using DC current interruption and variable rotation rate
US7144805B2 (en) Method of submicron metallization using electrochemical deposition of recesses including a first deposition at a first current density and a second deposition at an increased current density
US6399479B1 (en) Processes to improve electroplating fill
US6946065B1 (en) Process for electroplating metal into microscopic recessed features
JP5203602B2 (en) Method for direct electroplating of copper onto a non-copper plateable layer
Takahashi Electroplating copper onto resistive barrier films
US20030155249A1 (en) Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
US7799684B1 (en) Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers
US20060213778A1 (en) Method for electrochemical plating on semiconductor wafers
US7268075B2 (en) Method to reduce the copper line roughness for increased electrical conductivity of narrow interconnects (<100nm)
US8277619B2 (en) Apparatus for electrochemical plating semiconductor wafers
US9714474B2 (en) Seed layer deposition in microscale features
US6689686B2 (en) System and method for electroplating fine geometries
US7204924B2 (en) Method and apparatus to deposit layers with uniform properties
EP1125007B1 (en) Submicron metallization using electrochemical deposition
US20080237048A1 (en) Method and apparatus for selective electrofilling of through-wafer vias
US9435048B2 (en) Layer by layer electro chemical plating (ECP) process
US20060226014A1 (en) Method and process for improved uniformity of electrochemical plating films produced in semiconductor device processing
US20040217013A1 (en) Apparatus and method for electropolishing a metal wiring layer on a semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD., TAIWA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHENG, HSI-KUEI;LIN, STEVEN;HUANG, CHIH-CHANG;AND OTHERS;REEL/FRAME:016416/0620

Effective date: 20050114

STCB Information on status: application discontinuation

Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION