TWI845263B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

Description

Memory device and manufacturing method thereof

The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a memory device and a method for manufacturing the same.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure, so they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

The present invention provides a channel plug for a vertical channel of a memory device with a small aspect ratio, which can reduce the difficulty of the process and improve the reliability of the device.

The present invention provides a channel plug of a vertical channel of a memory element having a doping, and the junction can partially overlap or completely overlap with the topmost conductive layer laterally, so that the gate induced drain leakage (GIDL) can be reduced during erasing.

A memory element of an embodiment of the present invention includes: a first internal connection structure, a second internal connection structure, a stacking structure, a stop layer and a plurality of channel column structures. The first internal connection structure is located above a substrate. The second internal connection structure is located above the first internal connection structure. The stacking structure is located between the first internal connection structure and the second internal connection structure, wherein the stacking structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately. The stop layer is located between the stacking structure and the second internal connection structure. The plurality of channel column structures extend through the stacking structure, and each channel column structure includes: a channel column, a first channel plug and a second channel plug. The channel column extends through the stacking structure and the stop layer. The first channel plug is located at the first end of the channel column and is connected to the first internal connection structure. The second channel plug is located at the second end of the channel column and is connected to the second internal connection structure. The bottom surface of the second channel plug is closer to the substrate than the bottom surface of the stop layer.

A method for manufacturing a memory element according to an embodiment of the present invention comprises the following steps: forming a stacked structure on a first surface of a stop layer; the stacked structure comprises a plurality of alternately stacked intermediate layers and a plurality of insulating layers; replacing a portion of the plurality of intermediate layers with a plurality of conductive layers; forming a plurality of channel pillar structures extending through the stacked structure; forming a charge storage structure on the outer surface of the plurality of channel pillar structures; the above-mentioned formation of each channel pillar structure comprises the following steps: forming a channel pillar extending through the stacked structure and the stop layer; forming an insulating pillar in the channel pillar; forming a first channel plug located at a first end of the channel pillar and electrically connected to the first internal connection structure. Removing a portion of the insulating column at the second end of each channel column to form a groove. Forming a second channel plug of each channel column structure in the groove.

Based on the above, the channel plug of the vertical channel of the memory device of the embodiment of the present invention has a small aspect ratio, so the difficulty of the process can be reduced when forming the groove of the channel plug, and the reliability of the device can be improved. Because the channel plug of the vertical channel has doping, the junction can overlap partially or completely with the topmost conductive layer laterally, so the gate induced drain leakage (GIDL) can be reduced when erasing.

10: Base

20: Component layer

30: Internal connection structure

30a: Part 1

30b: Part 2

31a: The topmost wire

31b: Top layer of wires

32:Joint structure

32a: Part 1

32b: Part 2

34a: Joint layer

34b: Joint layer

36a:Joining plug

36b:Joint plug

38a:Joint pad

38b:Joint pad

40:Internal connection structure

42: Dielectric layer

44a: Conductor pad

44b:Interlayer window

46: Contact window

48: Conductor wire

50: Dielectric layer

60: Channel material

60a: Channel plug

60b: Semiconductor pad

93: Conductor layer

100: Base

101: Insulation layer

102: Insulation layer

103: Stop layer

104: Middle layer

105: Dielectric layer

106: Open mouth

107: Dielectric layer

108: Charge storage structure

110: Channel layer/channel column

111: Insulating lining

112: Insulation Pillar

113: Conductor layer

114: Channel plug

115: Dielectric layer

116: Separation channel

117: Gap wall

126: Conductor layer

128: Dielectric layer

129: Stop layer

130: Dielectric layer

200: Area

COA: Contact Window

CP: Vertical channel column

CP1: Channel column structure

D1: Distance

DVC: Virtual column

E1: terminal

E2: End

H1: Height

JS: Interview

LP: Lower part

PIC: Support structure

R1: Groove

P1: Part 1

P2: Part 2

RSC: Reverse ladder structure

S1: Surface/bottom

S1, S2: surface

S3, S5: bottom surface

S4: Top

SC: Step structure

SK1: Stacked structure

SK2: Stacked structure

SLIT:Separation wall

T1:Thickness

TV:Piercing

UP: Upper part

Figures 1A to 1Q are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention.

Figure 2 is an enlarged view of a local area of Figure 1Q.

Figures 3 to 5 are cross-sectional schematic diagrams of several memory elements according to other embodiments of the present invention.

Figures 1A to 1Q are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 10 is provided. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. The active components are, for example, transistors, diodes, etc. The passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) component. Since the component layer 20 is formed below the memory array (for example, below the stacked structure SK2 of FIG. 1Q ), and the component layer 20 is, for example, a complementary metal oxide semiconductor (CMOS), this structure may also be referred to as a CMOS-Bonded-Array (CbA) structure.

Referring to FIG. 1A , a first portion 30a of an internal connection structure 30 is formed on a component layer 20. The first portion 30a of the internal connection structure 30 may include multiple dielectric layers (not shown) and internal connections (not shown) formed in the multiple dielectric layers. The internal connections include multiple plugs (not shown) and multiple wires (not shown). The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the component layer 20 by plugs. The first portion 30a of the internal connection structure 30 may be formed by a single metal inlay, a double metal inlay process, or any known method.

Referring to FIG. 1A , a first portion 32a of a bonding structure 32 (shown in FIG. 1J ) is formed on a first portion 30a of an inner connection structure 30. The first portion 32a of the bonding structure 32 includes a bonding layer 34a, a bonding plug 36a, and a bonding pad 38a. The bonding layer 34a is, for example, silicon oxide, silicon nitride, or a combination thereof. The bonding plug 36a and the bonding pad 38a are, for example, copper. The bonding pad 38a is connected to the topmost wire 31a of the first portion 30a of the inner connection structure 30 via the bonding plug 36a. The bonding pad 38a and the bonding plug 36a can be formed by single inlay or double inlay. The bonding pad 38a, the bonding plug 36a, and the bonding layer 34a can be planarized and coplanar by a chemical mechanical polishing process.

1A , another substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. An insulating layer 101 and a stop layer 103 are formed on the substrate 100. The insulating layer 101 is, for example, silicon oxide. The stop layer 103 is formed on the insulating layer 101. The stop layer 103 may be an insulating material, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ) or a combination thereof.

Referring to FIG. 1A , a lower portion LP of a stacked structure SK1 is formed on a surface S1 of a stop layer 103. The lower portion LP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 alternately stacked with each other. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 may be used as a sacrificial layer, which will be partially or completely removed in a subsequent process.

Referring to FIG. 1B , multiple dummy columns DVC then pass through the lower LP of the stacked structure SK1. Multiple dummy columns DVC can be formed into openings (not shown) by a single-stage lithography and etching process or a multi-stage lithography and etching process. The opening extends through the lower LP of the stacked structure SK1 to the stop layer 103, and even to the insulating layer 101. Then, a filling material (or self-alignment material) is filled into the opening to form it. The profile of the sidewall of the opening formed by the multi-stage lithography and etching process is, for example, a bamboo-node shape.

Referring to FIG. 1C , an upper portion UP of a stacking structure SK1 is formed on a substrate 100. The upper portion UP of the stacking structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked on each other. The materials of the insulating layers 102 and the intermediate layers 104 of the upper portion UP of the stacking structure SK1 are the same as the materials of the insulating layers 102 and the intermediate layers 104 of the lower portion LP of the stacking structure SK1. Then, the intermediate layers 104 and the insulating layers 102 of the stacking structure SK1 are patterned to form a step structure SC. In some embodiments, the step structure SC can be formed by a multi-stage patterning process, but the present invention is not limited thereto. The patterning process may include processes such as lithography, etching and trimming. A dielectric layer 107 is formed on the substrate 100 to cover the step structure SC. The material of the dielectric layer 107 is, for example, silicon oxide. The method of forming the dielectric layer 107 is, for example, to form a dielectric material to fill and cover the step structure SC. A planarization process is then performed, such as a chemical mechanical polishing process, to remove excess dielectric material.

Referring to FIG. 1D , a patterning process is performed to remove a portion of the stacked structure SK1 to form an opening (not shown) and expose the dummy column DVC. Next, the dummy column DVC exposed by the opening is removed to form one or more openings 106 extending through the stacked structure SK1. In one embodiment, the opening 106 may have slightly inclined side walls. In another embodiment, the opening 106 may have substantially vertical side walls (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel (VC) hole. In one embodiment, the opening 106 can be formed by a single-stage lithography and etching process. In another embodiment, the opening 106 is formed by multiple-stage lithography and etching processes. The sidewall profile of the opening 106 formed by multiple stages of lithography and etching processes is, for example, in the shape of a bamboo node.

Referring to FIG. 1E , a charge storage structure 108 is then formed in the opening 106 . The charge storage structure 108 contacts the insulating layer 102 and the intermediate layer 104 . In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. The charge storage structure 108 is, for example, a conformal layer formed on the sidewalls and bottom surface of the opening 106 . A vertical channel column CP is then formed in the remaining space of the opening 106 . The vertical channel column CP can be formed by the following method.

1E , a channel layer 110 is formed on the inner sidewall and bottom surface of the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes undoped polysilicon. Then, an insulating column (or core insulating column) 112 is formed on the inner surface of the channel layer 110. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a channel plug 114 is formed in the opening 106, and the channel plug 114 contacts the channel layer 110. The channel plug 114 extends from the top surface (not shown) of the uppermost insulating layer 102 to a certain depth of the opening 106. In one embodiment, the material of the channel plug 114 includes a semiconductor material with doping, such as polysilicon with doping. The channel layer 110, the insulating column 112, and the channel plug 114 can be collectively referred to as a vertical channel column CP. The vertical channel column CP passes through the stacked structure SK1 and extends to the stop layer 103, and even extends to the insulating layer 101. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column CP. Thereafter, a dielectric layer 115 is formed above the substrate 100. The material of the dielectric layer 115 includes silicon oxide.

Referring to FIG. 1F , a plurality of supporting structures PIC and a plurality of through-holes TV are formed. The supporting structure PIC and the plurality of through-holes TV may extend from the top surface of the dielectric layer 115 through the stacking structure SK1 and the stop layer 103 to prevent the step structure SC from collapsing during the subsequent removal of the intermediate layer 104. In the present embodiment, the supporting structure PIC and the plurality of through-holes TV may have the same structure, each including an insulating liner 111 and a conductive layer 113. In other embodiments, the supporting structure PIC may be formed simultaneously with the formation of the charge storage structure 108 and the vertical channel column CP. The plurality of supporting structures PIC respectively have the same structure as the structure in which the charge storage structure 108 and the vertical channel column CP are combined, but the present invention is not limited thereto. The perforated TV will be connected to the internal wiring in the subsequent manufacturing process, so it can also be called a signal contact window.

Referring to FIG. 1G , a dielectric layer 128 is formed on the dielectric layer 115. The dielectric layer 128 is, for example, silicon oxide. Thereafter, a patterning process is performed to form a plurality of separation trenches 116. The separation trenches 116 extend through the dielectric layer 128, the dielectric layer 115, and the stacked structure SK1, and divide the stacked structure SK1 into a plurality of blocks (not shown). The separation trenches 116 may have vertical sidewalls (not shown) or slightly inclined sidewalls (not shown).

Referring to FIG. 1G , a replacement process is performed to replace part of the middle layer 104 with the conductive layer 126. First, a selective etching process is performed so that the etchant contacts the middle layer 104 of the stacked structure SK1 on both sides through the separation trenches 116. Thereby, part of the middle layer 104 is removed to form a plurality of horizontal openings (not shown), leaving the middle layer 104 around the through hole TV. The selective etching process may be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process may be, for example, hot phosphoric acid. Then, a conductive layer 126 is formed in the separation trenches 116 and the horizontal openings. The conductive layer 126 may serve as a gate layer. The conductor layer 126 includes, for example, a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Part of the middle layer 104 is replaced by the conductor layer 126, thereby forming a stacked structure SK2.

The stacking structure SK2 includes a first part P1 and a second part P2. The first part P1 of the stacking structure SK2 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked alternately. The second part P2 of the stacking structure SK2 includes a plurality of insulating layers 102 and a plurality of conductive layers 126 stacked alternately. A plurality of vertical channel columns CP extend through the second part P2 of the stacking structure SK2. A plurality of through holes TV extend through the first part P1 of the stacking structure SK2. A portion of the plurality of supporting structures PIC extend through the second part P2 of the stacking structure SK2. Another portion of the plurality of supporting structures PIC extend through the first part P1 of the stacking structure SK2.

Referring to FIG. 1G , the conductive layer 126 formed in the separation trench 116 is then removed, and a spacer 117 is formed on the sidewall of the separation trench 116. The spacer 117 includes a dielectric material different from the insulating layer 102, such as silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite layer. Thereafter, a conductive layer 93, such as a doped polysilicon layer, is filled in the remaining space of the separation trench 116. The conductive layer 93 in the separation trench 116 and the spacer 117 together form a slit SLIT. The conductive layer 93 of the slit SLIT is isolated by the spacer 117 to avoid contact with the conductive layer 126. Thereafter, a stop layer 129 is formed on the dielectric layer 128 to cover the top surface of the separation wall SLIT. The stop layer 129 is, for example, silicon nitride.

Referring to FIG. 1H , a dielectric layer 130 is formed on the stop layer 129. The dielectric layer 130 is, for example, silicon oxide. Then, a plurality of contact windows COA are formed from the dielectric layer 130 to the dielectric layer 107 to electrically connect the conductive layer 126, the vertical channel column CP, and the through hole TV. The contact window COA can be formed by first forming a contact window hole, and then forming a conductive material on the dielectric layer 130, and the conductive material is also filled in the contact window hole. Afterwards, an etch back or chemical mechanical polishing process is performed to remove the conductive material on the dielectric layer 130.

Referring to FIG. 1H , a second portion 30b of the interconnect structure 30 is formed above the substrate 100. The second portion 30b of the interconnect structure 30 may include multiple dielectric layers (not shown) and interconnects (not shown) formed in the multiple dielectric layers. The interconnects include multiple plugs (not shown) and multiple wires (not shown). The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the contact window COA by plugs. The second portion 30b of the interconnect structure 30 may be formed by a single metal inlay, a double metal inlay process, or any known method.

Referring to FIG. 1H , a second portion 32b of a bonding structure 32 (shown in FIG. 1J ) is formed on a second portion 30b of an inner connection structure 30. The second portion 32b of the bonding structure 32 includes a bonding layer 34b, a bonding plug 36b, and a bonding pad 38b. The bonding pad 38b is connected to the topmost wire 31b of the second portion 30b of the inner connection structure 30 via the bonding plug 36b. The materials and forming methods of the bonding layer 34b, the bonding plug 36b, and the bonding pad 38b may be the same or similar to the materials and forming methods of the bonding layer 34a, the bonding plug 36a, and the bonding pad 38a. The bonding structure 32, the first portion 30a of the inner connection structure, and the second portion 30b of the inner connection structure form the inner connection structure 30.

Referring to FIG. 1I , the substrate 100 is flipped. The step structure SC on the flipped substrate 100 becomes a reverse step structure RSC. The contact window COA is below the reverse step structure RSC. Next, referring to FIG. 1I and FIG. 1J , the second portion 32b of the bonding structure 32 is bonded to the first portion 32a of the bonding structure 32 to form the bonding structure 32. In the bonding structure 32, the bonding layer 34b is bonded to the bonding layer 34a, and the bonding pad 38b is bonded to the bonding pad 38a. The bonding layer 34b and the bonding layer 34a can be bonded by dielectric-to-dielectric. The bonding pad 38b and the bonding pad 38a can be bonded by metal-to-metal. The bonding structure 32 is located in the inner connection structure 30, between the first portion 32a and the second portion 32b of the inner connection structure 30. The bonding structure 32, the first portion 32a and the second portion 32b form the inner connection structure 30.

Referring to FIG. 1K , the substrate 100 is then removed to expose the insulating layer 101. The substrate 100 can be removed by grinding, polishing or etching.

Referring to FIG. 1L , the stop layer 103 is used as an etching stop layer to perform an etching process to remove the insulating layer 101, part of the charge storage structure 108, and part of the channel layer 110, exposing the top surface of the insulating column 112 of the vertical channel column CP and the surface S2 of the stop layer 103. Here, the channel layer 110 may also be referred to as the channel column 110.

Referring to FIG. 1M , an etching process, such as a wet etching process, is performed to remove a portion of the insulating pillar 112 to form a plurality of grooves R1. Since the material of the stop layer 103 is different from that of the insulating pillar 112, the stop layer 103 can protect the insulating layer 102 and the separation wall SLIT below during the etching process. The stop layer 103 can prevent the insulating layer 102 and the spacer 117 of the separation wall SLIT from being damaged by etching. In some embodiments, the groove R1 exposes the inner side wall of the channel pillar 110 and the top surface of the remaining insulating pillar 112. In other embodiments, part of the channel column 110 is also removed so that the groove R1 exposes the inner side wall (not shown) of the charge storage structure 108. The groove R1 extends through the stop layer 103, and the bottom surface of the groove R1 is lower than the bottom surface of the stop layer 103 (i.e., surface S1). In some embodiments, the bottom surface of the groove R1 is, for example, between the bottom surface of the stop layer 103 (i.e., surface S1) and the bottom surface S5 of the topmost conductor layer 126. The depth of the groove R1 can be controlled by the time mode during the etching process. The aspect ratio of the groove R1 is much smaller than the aspect ratio of the separation trench 116 of the separation wall SLIT. The aspect ratio of the groove R1 is, for example, 1 to 6.25. Since the aspect ratio of the groove R1 is small, the difficulty of etching can be reduced.

Referring to FIG. 1N , a channel material 60 is formed on the stop layer 103. The channel material 60 is also filled into the groove R1 and electrically connected to the channel column 110. Since the aspect ratio of the groove R1 is small, the channel material 60 can be easily backfilled. The channel material 60 may include a semiconductor material. The semiconductor material is, for example, a semiconductor element or a semiconductor compound. The semiconductor element is, for example, polycrystalline silicon. The semiconductor compound is, for example, germanium silicide or silicon carbide. The channel material 60 has a dopant. The dopant may be phosphorus or arsenic. The concentration of the dopant is between 10 ¹⁸ and 10 ²¹ atoms/cm3.

Referring to FIG. 10 and FIG. 2 , a planarization process is performed to remove the channel material 60 on the stop layer 103 and form a channel plug 60a electrically connected to the channel pillar 110 in the recess R1. In some embodiments, the doping of the channel material 60 can be formed by in-situ doping when depositing the channel material. The temperature of the deposition process can be lower than 450 degrees Celsius. In other embodiments, the doping of the channel material 60 can be formed by an ion implantation process and then activated by an annealing process. The annealing process is, for example, laser annealing. The temperature of the annealing process is lower than 450 degrees Celsius. After annealing, the junction JS (shown in FIG. 2 ) formed by dopant diffusion may completely overlap or partially overlap the topmost conductor layer 126 laterally.

1O and 2, the channel plug 60a, the channel pillar 110, the insulating pillar 112 and the channel plug 114 can be collectively referred to as a channel pillar structure CP1. The channel pillar structure CP1 extends through the multiple insulating layers 102 and the multiple conductive layers 126 of the stacked structure SK2. The two ends (top and bottom) E2 and E1 of the channel pillar structure CP1 are the channel plugs 60a and 114, respectively, which can be electrically connected to other conductive features, such as the conductive pad 44a (shown in FIG. 1P and FIG. 2) and the contact window COA. Therefore, the channel pillar structure CP1 can also be called a double-ended vertical channel pillar. The charge storage structure 108 surrounds the channel plug 60a, the channel column 110 and the outer wall of the channel plug 114 of the channel column structure CP1, and is located between the channel column structure CP1 and the conductive layer 126, and between the channel column structure CP1 and the insulating layer 102.

Referring to FIG1P , a dielectric layer 42, a contact window 46 and a conductive pad 44a of an internal connection structure 40 (shown in FIG1Q ) are formed on the stop layer 103. The contact window 46 is electrically connected to the through hole TV. The channel plugs 60a of the multiple channel column structures CP1 are electrically connected to the same conductive pad 44a. The dielectric layer 42 can be a single layer or multiple layers. The material of the dielectric layer 42 can be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The contact window 46 and the conductive pad 44a are formed in the dielectric layer 42. The method for forming the contact window 46 and the conductive pad 44a is described as follows. First, a contact window hole (not shown) and a conductive pad opening (not shown) are formed in the dielectric layer 42 by lithography and etching processes. Then, a conductive material is formed on the dielectric layer 42, and the conductive material is filled into the contact window hole and the conductive pad opening. Afterwards, the excess conductive material on the dielectric layer 42 is removed by a planarization process, such as a chemical mechanical polishing process, to form a contact window 46 and a conductive pad 44a in the contact window hole and the conductive pad opening.

Referring to FIG. 1Q , other parts of the internal connection structure 40, such as a plurality of wires 48 and a dielectric layer 50, are formed on the dielectric layer 42, the conductive pad 44a, and the contact window 46. The plurality of wires 48 may include wires 48a and 48b. The wire 48a may serve as a common source line to connect the conductive pad 44a. Adjacent conductive pads 44a may be electrically connected to the same wire 48a. The wire 48b may be connected to the contact window 46. The material of the wire 48 may be copper or tungsten, for example. The dielectric layer 50 may be a single layer or multiple layers. The material of the dielectric layer 42 may be silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. The internal connection structure 40 may be electrically connected to the internal connection structure 30 via a through-hole TV. The internal connection structure 40 can be electrically connected to the internal connection structure 30 via the contact window COA. The internal connection structure 40 can be electrically connected to the internal connection structure 30 via the channel pillar structure CP1.

FIG2 is an enlarged view of the local area 200 of FIG1Q.

Referring to FIG. 2 , the charge storage structure 108 is on the outer surface of the channel column structure CP1. The multiple channel plugs 60a of the multiple channel column structures CP1 extend through the stop layer 103 and at least a portion of the topmost insulating layer 102. The height H1 of the multiple channel plugs 60a is greater than the thickness T1 of the stop layer 103. The bottom surface S3 of the channel plug 60a is closer to the substrate 10 (shown in FIG. 1Q ) than the bottom surface (i.e., surface S1) of the stop layer 103. That is, the bottom surface S3 of the channel plug 60a can be lower than the bottom surface (i.e., surface S1) of the stop layer 103. The bottom surface S3 of the channel plug 60a can be higher than the top surface S4 of the topmost conductive layer 126. Alternatively, the bottom surface S3 of the channel plug 60a may be lower than the bottom surface (i.e., surface S1) of the stop layer 103 and lower than the top surface S4 of the topmost conductive layer 126. In some embodiments, the bottom surface S3 of the channel plug 60a is between the top surface S4 and the bottom surface of the topmost conductive layer 126. Since the channel plug 60a has doping, the junction may partially overlap or completely overlap with the topmost conductive layer 126 laterally, thereby reducing the gate induced drain leakage (GIDL) when erasing. In some embodiments, the height H1 of the channel plug 60a from the surface S2 of the stop layer 103 to the bottom surface S3 of the channel plug 60a ranges from 500 angstroms to 1500 angstroms, for example. The range of the aspect ratio of the channel plug 60a is, for example, 0.5 to 3.75. The range of the distance D1 between the bottom surface S3 of the channel plug 60a and the top surface S4 of the topmost conductive layer 126 is, for example, -300 angstroms to 300 angstroms.

Referring to FIG. 1Q and FIG. 2 , in the above-mentioned embodiment, multiple channel plugs 60a of multiple channel column structures CP1 are formed in the stop layer 103 and separated from each other by the stop layer 103. Multiple adjacent channel plugs 60a are then partially electrically connected to each other via a conductive pad 44a (conductive feature) formed in the dielectric layer 42. The conductive pads 44a on opposite sides of the separation wall SLIT are then electrically connected via a wire (common source line) 48a. However, the present invention is not limited thereto. The conductive feature connecting the multiple adjacent channel plugs 60a can be formed before or after the dielectric layer 42 is formed, and its position can be in, below or above the dielectric layer 42.

Figures 3 to 5 are cross-sectional schematic diagrams of several memory elements according to other embodiments of the present invention.

Referring to FIG. 1N and FIG. 3 , after forming the channel material 60 on the stop layer 103 and in the recess R1 (shown in FIG. 1M ), before forming the dielectric layer 42 , a patterning process is performed on the channel material 60 to replace the planarization process. The patterning process of the channel material 60 can be performed by lithography and etching processes. The channel material 60 on the multiple supporting structures PIC and the multiple through-holes TV is removed. The channel material 60 is patterned into a semiconductor pad 60b (conductive feature) on the stop layer 103 and a channel plug 60a filled in the recess R1. Adjacent channel plugs 60a are electrically connected to each other via the semiconductor pad 60b. The semiconductor pad 60b (conductive feature) also connects multiple channel plugs 60a on both sides of the separation wall SLIT. Thereafter, referring to the above-mentioned embodiment, the dielectric layer 42, the conductive pad 44a, the conductive line 48 and the dielectric layer 50 of the interconnect structure 40 are formed.

Referring to FIG. 1P and FIG. 4 , after a dielectric layer 42 is formed on the stop layer 103 , multiple contact windows 46 and multiple vias 44b separated from each other are formed in the dielectric layer 42 . The contact window 46 is connected to the through hole TV. Each via 44b is connected to a single channel plug 60a. Multiple vias 44b are electrically connected through a subsequently formed conductor (common source line) 48a. Multiple adjacent vias 44b can be electrically connected to the same conductor 48a.

Referring to FIG. 1Q to FIG. 4 , the above-mentioned stop layer 103 is an insulating continuous layer, however, the present invention is not limited thereto. The stop layer 103 can also be a discontinuous patterned conductive layer as shown in FIG. 5 .

Referring to FIG. 5 , the patterned conductive layers are separated by a dielectric layer 105. The stop layer 103 and the dielectric layer 105 may be formed by a metal embedding method in which the dielectric layer 105 is first formed and then the stop layer 103 is formed. The metal embedding method may first form the dielectric layer 105 and then pattern the dielectric layer 105 to form a plurality of openings. Then, a stop material is filled on the dielectric layer 105 and in the plurality of openings. Then, a planarization process, such as a chemical mechanical polishing process, is performed to remove excess stop material on the dielectric layer 105 to form the stop layer 103. Alternatively, the stop layer 103 and the dielectric layer 105 may be formed by first forming a stop material and then patterning the stop material to form the stop layer 103. Afterwards, a dielectric material is formed on and around the stop layer 103. Then, a planarization process, such as a chemical mechanical polishing process, is performed to remove the dielectric material on the stop layer 103 to form a dielectric layer 105.

Referring to FIG. 5 , in some embodiments, the stop layer 103 is a discontinuous patterned conductive layer. The material of the patterned conductive layer is, for example, a polysilicon layer or tungsten. The stop layer 103 may include conductive patterns 103a, 103b, and 103c. The conductive patterns 103a, 103b, and 103c are electrically insulated from each other by a dielectric layer 105. Each conductive pattern 103a surrounds a through hole TV. The conductive pattern 103b surrounds a plurality of supporting structures PIC. Each conductive pattern 103c surrounds one of a plurality of channel plugs 60a.

In this embodiment, the plurality of through-holes TV are electrically connected to the stop layer 103 (conductive pattern 103a) respectively, and are electrically insulated from each other by the dielectric layer 105. The plurality of supporting structures PIC can be connected to the same stop layer 103 (conductive pattern 103b). The plurality of supporting structures PIC are electrically insulated from the adjacent through-holes TV by the dielectric layer 105. The plurality of supporting structures PIC are electrically insulated from the adjacent channel plugs 60a by the dielectric layer 105. The stop layer 103 (conductive pattern 103c) around the plurality of channel plugs 60a extends continuously from one side of the partition wall SLIT to the other side in the horizontal direction. Therefore, the multiple channel plugs 60a on opposite sides of the separation wall SLIT are electrically connected to each other through the conductive pad 44a and the stop layer 103 below it, and can also be electrically connected to each other through the conductive pad 44a and the wire 48 above it.

In summary, the embodiment of the present invention forms a memory element by bonding two chips. Since one of the chips is provided with a stop layer, the stacked structure below the stop layer can be protected during the etching process. Therefore, the channel plug provided at the top of the vertical channel column can be formed by etching a groove and then backfilling the channel material. Afterwards, a conductive feature is formed on the channel plug to electrically connect multiple channel plugs to each other. Since the aspect ratio of the groove is small, it can be easily etched and the channel material can be easily backfilled. Therefore, the method of the embodiment of the present invention can reduce the difficulty of the process. Because the channel plug is doped, the junction can partially or completely overlap laterally with the topmost conductive layer, thereby reducing the gate-induced drain leakage (GIDL) during erase.

50: Dielectric layer

48: Conductor wire

42: Dielectric layer

40:Internal connection structure

SLIT:Separation wall

103: Stop layer

102: Insulation layer

S1: Surface/bottom

S1, S2: surface

S3, S5: bottom surface

S4: Top

60a: Channel plug

110: Channel layer/channel column

108: Charge storage structure

114: Channel plug

CP1: Channel column structure

E1, E2: end

200: Area

44a: Conductor pad

H1: Height

JS: Interview

D1: Distance

126: Conductor layer

Claims (20)

A memory element includes: a first interconnect structure located above a substrate; a second interconnect structure located above the first interconnect structure; a stacking structure located between the first interconnect structure and the second interconnect structure, wherein the stacking structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately; a stop layer located between the stacking structure and the second interconnect structure; and a plurality of channel pillar structures extending through the stacking structure, each channel pillar structure including: a channel pillar extending through the stacking structure and the stop layer; a first channel plug located at a first end of the channel pillar and connected to the first interconnect structure; and a second channel plug located at a second end of the channel pillar and connected to the second interconnect structure, wherein a bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer. A memory element as described in claim 1, wherein the second channel plug extends through the stop layer and at least a portion of the topmost insulating layer of the plurality of insulating layers. A memory element as described in claim 1, wherein the bottom surface of the second channel plug is between the bottom surface of the stop layer and the bottom surface of the topmost conductive layer of the multiple conductive layers. A memory element as described in claim 1, wherein the first channel plug and the second channel plug include a semiconductor material with an impurity. A memory element as described in claim 1, wherein adjacent second channel plugs are electrically connected to each other via semiconductor pads. A memory element as described in claim 1, wherein the adjacent second channel plugs are connected to the same conductive pad of the second internal connection structure and then connected to a common source line. A memory element as described in claim 1, wherein adjacent second channel plugs are connected to a common source line via multiple vias of the second internal connection structure. The memory element as described in claim 1 further includes: a bonding structure located in the first internal connection structure. A memory device as described in claim 1, wherein the height of the second channel plug from the top surface of the stop layer ranges from 500 angstroms to 1500 angstroms. A memory element as described in claim 1, wherein the aspect ratio of the second channel plug ranges from 0.5 to 3.75. A memory element as described in claim 1, wherein the distance between the bottom surface of the second channel plug and the top surface of the topmost conductive layer of the plurality of conductive layers ranges from -300 angstroms to 300 angstroms. The memory element as described in claim 1 further includes: A plurality of through holes extending through the stop layer and the plurality of alternately stacked middle layers and the plurality of insulating layers of the stacking structure, connecting the first internal connection structure and the second internal connection structure. A memory element as described in claim 1, wherein the stop layer comprises an insulating material or a patterned conductive layer. A method for manufacturing a memory element comprises: forming a stacked structure on a first surface of a stop layer, wherein the stacked structure comprises a plurality of middle layers and a plurality of insulating layers stacked alternately; replacing a portion of the plurality of middle layers with a plurality of conductive layers; forming a plurality of channel pillar structures extending through the stacked structure, wherein forming each channel pillar structure comprises: forming a channel pillar extending through the stacked structure and the stop layer; forming an insulating pillar on an inner surface of the channel pillar; forming a first channel plug located at a first end of the channel pillar; removing the conductive layer; and removing the conductive layer from the first end of the channel pillar. The insulating column at the second end of each channel column is partially connected to form a groove; and a second channel plug of each channel column structure is formed in the groove; a charge storage structure is formed on the outer surface of the plurality of channel column structures, and a first inner connection structure and a second inner connection structure are formed, so that the stacking structure is located between the first inner connection structure and the second inner connection structure, wherein the first inner connection structure is electrically connected to the first end of the channel column, and the second inner connection structure is electrically connected to the second end of the channel column. The method for manufacturing a memory element as described in claim 14 further includes: performing an ion implantation process to implant the dopant into the second channel plug; and performing an annealing process to activate the dopant. The manufacturing method of the memory element as described in claim 14 further includes: forming a first portion of the first internal connection structure on the first substrate; forming a first portion of the bonding structure on the first portion of the first internal connection structure; forming a second portion of the first internal connection structure on the stacking structure to connect the first channel plug; forming a second portion of the bonding structure on the second portion of the first internal connection structure; and bonding the first portion of the bonding structure and the second portion of the bonding structure. The manufacturing method of the memory element as described in claim 16 further includes: forming the stop layer on the second substrate; removing the second substrate and exposing the second end of each channel column; and forming the second internal connection structure on the second surface of the stop layer to connect the second channel plug, wherein the bottom surface of the second channel plug is closer to the first substrate than the first surface of the stop layer. A method for manufacturing a memory device as described in claim 17, wherein the method for forming the second channel plug of each channel pillar structure comprises: forming a channel material on the second surface of the stop layer and in the groove; and removing the channel material on the second surface of the stop layer to form the second channel plug in the groove. A method for manufacturing a memory device as described in claim 18, wherein forming the second internal connection structure includes forming a conductive pad or a via window to connect the second channel plug. A method for manufacturing a memory device as described in claim 17, wherein the method for forming the second channel plug of each channel pillar structure in the groove comprises: forming a channel material on the second surface of the stop layer and in the groove; and patterning the channel material on the second surface of the stop layer to form a semiconductor layer and forming the second channel plug in the groove.