TWI590419B - Dynamic random access memory structure and manufacturing method thereof - Google Patents

Description

Dynamic random access memory structure and manufacturing method thereof

The present invention relates to a memory structure and a method of fabricating the same, and more particularly to a dynamic random access memory structure and a method of fabricating the same.

In the peripheral circuit region of the conventional dynamic random access memory structure, the gate material of the transistor component is doped with polysilicon, so that a poly depletion effect is easily generated and the component performance is lowered.

Therefore, a transistor element having a metal gate structure instead of a doped polysilicon gate has been developed, which can effectively prevent the occurrence of polycrystalline germanium depletion.

However, how to effectively integrate the process of the dynamic random access memory and the process of the transistor structure having the metal gate structure has become an urgent problem to be solved in the industry. In addition, how to effectively reduce the process complexity of dynamic random access memory is also the goal of the industry.

The invention provides a manufacturing method of a dynamic random access memory structure, which can effectively integrate the process of the dynamic random access memory with the process of the transistor structure having the metal gate structure.

The present invention provides a dynamic random access memory structure which can effectively prevent components in a memory cell region from being damaged by a crystal structure of a peripheral circuit region during formation.

The invention provides a method for fabricating a dynamic random access memory structure, comprising the following steps. A substrate is provided, wherein the substrate includes a memory cell region and a peripheral circuit region. A dynamic random access memory is formed in the memory cell region. The DRAM includes a capacitive contact window coupled to the capacitive structure. A transistor structure having a metal gate structure is formed in the peripheral circuit region. The metal gate structure is formed by a process using a dummy gate. The capacitive contact window and the virtual gate are formed by the same layer of conductors.

The invention provides a dynamic random access memory structure, comprising a substrate, a dynamic random access memory and a guard ring structure. The substrate includes a memory cell region. The dynamic random access memory is located in the memory cell area. The DRAM includes a capacitive contact window coupled to the capacitive structure. The guard ring structure surrounds the boundary of the memory cell. The capacitive contact window and guard ring structure are derived from the same layer of conductor layers.

Based on the above, in the manufacturing method of the dynamic random access memory structure proposed by the present invention, since the capacitive contact window and the dummy gate are formed by the same layer of conductor layers, the dynamic random access memory can be effectively The process is integrated with the process of a transistor structure having a metal gate structure, and the process complexity can be effectively reduced.

In addition, since the dynamic random access memory structure proposed by the present invention has a guard ring structure surrounding the boundary of the memory cell region, the member in the memory cell region can be effectively prevented from being subjected to the process of forming the transistor structure of the peripheral circuit region. damage. In addition, since the capacitive contact window and the guard ring structure are derived from the same layer of conductor layers, the process complexity can be effectively reduced.

The above described features and advantages of the invention will be apparent from the following description.

1A through 1H are cross-sectional views showing a manufacturing process of a dynamic random access memory structure according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided in which a substrate 100 includes a memory cell region R1 and a peripheral circuit region R2. Additionally, isolation structures 102 can be formed in substrate 100. The isolation structure 102 is, for example, a shallow trench isolation structure (STI).

A buried wire 104 is formed in the substrate 100. The buried wire 104 can be used as a word line for dynamic random access memory. In the cross-sectional view of FIG. 1, buried conductors 104 located in memory cell region R1 may be located between isolation structures 102. The method of forming the buried wiring 104 is, for example, a combination of a deposition process, a lithography process, and an etching process. The buried conductor 104 includes a buried conductor layer 104a and may further include a cap layer 104b and a dielectric layer 104c. The buried conductor layer 104a is disposed in the substrate 100. The material of the buried conductor layer 104a is, for example, a metal material such as tungsten. The cap layer 104b is disposed on the buried conductor layer 104a. The material of the cap layer 104b is, for example, tantalum nitride. The dielectric layer 104c is disposed between the buried conductor layer 104a and the substrate 100. The material of the dielectric layer 104c is, for example, ruthenium oxide.

Part of the buried conductor 104 can be located in the peripheral circuit region R2. For example, the conductor layer 104a and the cap layer 104b of the buried wire 104 may be disposed in the isolation structure 102 of the peripheral circuit region R2.

A dielectric layer 106a can be formed on the substrate 100 of the memory cell region R1. The material of the dielectric layer 106a is, for example, ruthenium oxide. A dielectric layer 106b can be formed on the substrate 100 of the peripheral circuit region R2. The material of the dielectric layer 106b is, for example, ruthenium oxide. The method of forming the dielectric layer 106a and the dielectric layer 106b is, for example, a thermal oxidation method or a chemical vapor deposition method. The thickness of the dielectric layer 106a is, for example, greater than the thickness of the dielectric layer 106b, but the invention is not limited thereto.

A wire structure 108 is formed on the substrate 100 of the memory cell region R1. The wire structure 108 can be used as a bit line of a dynamic random access memory. In the cross-sectional view of FIG. 1, the wire structure 108 can be positioned between the buried wires 104 and a portion of the wire structures 108 can be located in the dielectric layer 106a. The method of forming the wire structure 108 is, for example, a combination of a deposition process and a patterning process. The wire structure 108 can be a multilayer structure or a single layer structure. In this embodiment, the wire structure 108 is illustrated by taking a multilayer structure as an example, but the invention is not limited thereto. The wire structure 108 can include a conductor layer 108a, a conductor layer 108b, and a barrier layer 108c. The conductor layer 108a is disposed on the substrate 100 and may be located in the dielectric layer 106a. The material of the conductor layer 108a is, for example, doped polysilicon. The conductor layer 108b is disposed on the conductor layer 108a. The material of the conductor layer 108b is, for example, a metal material such as tungsten. The barrier layer 108c is disposed between the conductor layer 108a and the conductor layer 108b. The material of the barrier layer 108c is, for example, Ti/TiN.

Additionally, a cap layer 110 can be formed on the wire structure 108. The material of the cap layer 110 is, for example, tantalum nitride. The method of forming the cap layer 110 is, for example, a combination of a deposition process and a patterning process.

Referring to FIG. 1B, a blocking layer 112 may be conformally formed on the dielectric layer 106a, the dielectric layer 106b, and the cap layer 110. The material of the barrier layer 112 is, for example, tantalum nitride. The formation method of the barrier layer 112 is, for example, a chemical vapor deposition method.

A dielectric layer 114 may be formed on the barrier layer 112, a dielectric layer structure 116a is formed on the substrate 100 of the memory cell region R1, and a dielectric layer structure 116b is formed on the substrate 100 of the peripheral circuit region R2. The dielectric layer structure 116a includes a dielectric layer 106a, a barrier layer 112, and a dielectric layer 114 that are sequentially disposed on the substrate 100. The dielectric layer structure 116b includes a dielectric layer 106b, a barrier layer 112, and a dielectric layer 114 that are sequentially disposed on the substrate 100. In the memory cell region R1, the dielectric layer 114 exposes the barrier layer 112 above the cap layer 110. The material of the dielectric layer 114 is, for example, ruthenium oxide. The dielectric layer 114 is formed by, for example, forming a dielectric material layer on the barrier layer 112 and then planarizing the dielectric material layer (eg, a chemical mechanical polishing process).

Fig. 2 is a top view of Fig. 1C, wherein Fig. 1C is a cross-sectional view taken along line I-I' of Fig. 2 (memory cell region R1) and II-II' hatching (peripheral circuit region R2). In addition, in FIG. 2, for the sake of clarity, the dielectric layer structure 116a, the cap layer 110, and the memory cell region R1 in the memory cell region R1 and the cap layer 104b in the peripheral circuit region R2 are omitted.

Referring to FIG. 1C and FIG. 2, a portion of the dielectric layer structure 116a and a portion of the dielectric layer structure 116b are removed, and an opening 118a exposing the substrate 100 is formed in the dielectric layer structure 116a in the memory cell region R1. An opening 118b exposing the barrier layer 112 is formed in the dielectric layer structure 116b in the peripheral circuit region R2. In addition, a portion of the dielectric layer structure 116a is removed, and an opening 118c exposing the substrate 100 is formed in the dielectric layer structure 116a in the memory cell region R1, wherein the opening 118c surrounds the boundary of the memory cell region R1. The method of forming the opening 118a, the opening 118b and the opening 118c is, for example, a patterning process for the dielectric layer structure 116a and the dielectric layer structure 116b.

A capacitive contact window 120a and a dummy gate 120b are formed in the opening 118a and the opening 118b, respectively. The capacitive contact window 120a and the wire structure 108 are located on one side and the other side of the buried conductor layer 104a, respectively. Further, a grommet structure 120c may be formed in the opening 118c. The guard ring structure 120c surrounds the boundary of the memory cell region R1. For example, the capacitor contact window 120a, the dummy gate 120b and the guard ring structure 120c are formed by first forming a conductor layer filling the opening 118a, the opening 118b and the opening 118c, and then planarizing the conductor layer (for example, a chemical mechanical polishing process). ).

It can be seen that the capacitive contact window 120a and the dummy gate 120b are formed by the same layer of conductor layers, so that the process of the dynamic random access memory can be effectively integrated with the process of the transistor structure having the metal gate structure. And can effectively reduce the process complexity. In addition, the capacitive contact window 120a and the guard ring structure 120c can be formed by the same layer of conductor layers, thereby effectively reducing process complexity.

Referring to FIG. 1D, a stopper layer 122 covering the capacitive contact window 120a, the guard ring structure 120c, and the dielectric layer structure 116a is formed in the memory cell region R1. The material of the blocking layer 122 is, for example, different from the material of the dielectric layer 114. For example, the material of the dielectric layer 114 is, for example, yttrium oxide, and the material of the blocking layer 122 is, for example, tantalum nitride. The forming method of the blocking layer 122 is, for example, comprehensively forming a blocking material layer (not shown) in the memory cell region R1 and the peripheral circuit region R2, and then patterning the blocking material layer to remove the peripheral circuit region R2. Block the layer of material.

The dielectric layer 114 in the peripheral circuit region R2 is removed to form an opening 126. The removal method of the dielectric layer 114 is, for example, a wet etching method. At this time, the guard ring structure 120c and the blocking layer 122 can be used to protect the dielectric layer 114 in the memory cell region R1 to prevent the dielectric layer 114 in the memory cell region R1 from being damaged.

Referring to FIG. 1E, a spacer 128 may be formed on the sidewall of the dummy gate 120b. The material of the spacer 128 is, for example, ruthenium oxide. The spacer 128 is formed by, for example, forming a conformal layer of spacer material (not shown) on the dummy gate 120b, and then performing an etch-back process on the spacer material layer.

Lightly doped regions 130 may be formed in the substrate 100 on either side of the dummy gate 120b. The method of forming the lightly doped region 130 is, for example, an ion implantation method.

A spacer 132 is formed on the spacer 128. The material of the spacer 132 is, for example, ruthenium oxide. The spacer 132 is formed by, for example, forming a conformal layer of spacer material (not shown) on the dummy gate 120b and the spacer 128, and then performing an etch-back process on the spacer material layer.

In addition, during formation of the spacers 128 and the spacers 132, the barrier layer 112 and the dielectric layer 106b that are not covered by the dummy gates 120b, the spacers 128, and the spacers 132 are removed.

A doped region 134 is formed in the substrate 100 on both sides of the dummy gate 120b, wherein the lightly doped region 130 is located between the dummy gate 120b and the doped region 134. The method of forming the doping region 134 is, for example, an ion implantation method.

A dielectric layer 136 is formed in the opening 126. The material of the dielectric layer 136 is, for example, ruthenium oxide. The dielectric layer 136 is formed by, for example, forming a dielectric material layer (not shown) filling the opening 126, and then performing a planarization process (eg, a chemical mechanical polishing process) on the dielectric material layer. In addition, during the planarization process of the dielectric material layer, a portion of the blocking layer 122 may be removed, so that the thickness of the blocking layer 122 is thinned.

Referring to FIG. 1F, the dummy gate 120b in the dielectric layer 136 is removed, and the opening 138 is formed in the dielectric layer 136. The dummy gate 120b can be removed by self-alignment. The method of removing the dummy gate 120b is, for example, a dry etching method.

The barrier layer 112 and the dielectric layer 106b exposed by the opening 138 are removed. The method of removing the barrier layer 112 and the dielectric layer 106b exposed by the opening 138 is, for example, a dry etching method.

Referring to FIG. 1G, a metal gate structure 140 is formed in the opening 138. The metal gate structure 140 includes a gate dielectric layer 142, a high-k dielectric layer 144, a work function metal layer 146, and a metal gate 148 sequentially disposed on the substrate 100. The material of the gate dielectric layer 142 is, for example, hafnium oxide. The material of the high-k dielectric layer 144 is, for example, hafnium oxide (HfO _x ). The work function metal layer 146 may be a P-type work function metal layer or an N-type work function metal layer, depending on whether the transistor element to be formed is P-type or N-type. The material of the P-type work function metal layer is, for example, TiN. The material of the N-type work function metal layer is, for example, TiAlN or lanthanum oxide (La ₂ O ₃ ). The material of the metal gate 148 is, for example, a composite layer of tungsten, TiAl/TiN/W or a composite layer doped with polysilicon/TiN/W.

The metal gate structure 140 is formed by, for example, forming a gate dielectric material layer, a high-k dielectric material layer, a work function metal material layer, and a metal gate material layer (not shown) in the opening 138. The gate dielectric material layer, the high-k dielectric material layer, the work function metal material layer, and the metal gate material layer other than the opening 138 are removed by a planarization process (eg, a chemical mechanical polishing process). The method of forming the gate dielectric material layer is, for example, a thermal oxidation method. The method of forming the high-k dielectric material layer is, for example, atomic layer deposition (ALD). The method of forming the work function metal material layer is, for example, an atomic layer deposition method. The method of forming the metal gate material layer is, for example, a physical vapor deposition method or a chemical vapor deposition method.

As can be seen from the above, the metal gate structure 140 is formed by a gate last process using the dummy gate 120b. In addition, although the metal gate structure 140 is formed by the gate post-fabrication process of the above embodiment, the process for forming the metal gate structure 140 is not limited to the method exemplified in the above embodiments.

Referring to FIG. 1H, a dielectric layer 150 and a dielectric layer 152 are formed in the memory cell region R1 and the peripheral circuit region R2, and a capacitor structure 154 is formed in the dielectric layer 150 and the dielectric layer 152 of the memory cell region R1. The interconnect layers 156a-156d are formed in the dielectric layer 150 of the peripheral circuit region R2 and the dielectric layer 152. The capacitor structure 154 is coupled to the capacitor contact window 120a. In addition, the capacitor structure 154 can be coupled to the grommet structure 120c. The material of the dielectric layer 150 is, for example, tantalum nitride. The material of the dielectric layer 152 is, for example, ruthenium oxide. In FIG. 1H, the capacitor structure 154 is only schematic, and the invention is not limited thereto. Those skilled in the art can design and adjust the capacitor structure 154 according to actual needs.

The interconnect structure 156a is connected to the buried conductor layer 104a through the dielectric layer 136 and the cap layer 104b. The interconnect structures 156b, 156c pass through the dielectric layer 136 to be respectively connected to the corresponding doped regions 134. The interconnect structure 156d is connected to the leftmost metal gate structure 140 of FIG. 1H. The interconnect structures 156a-156d respectively include contact windows 160 and wires 162 that are connected to each other. The contact window 160 includes a barrier layer 160a and a conductor layer 160b, wherein the conductor layer 160b is disposed on the barrier layer 160a. In the cross-sectional view of FIG. 1H, only the interconnect structures 156a-156d in this cross-sectional view are shown. However, those skilled in the art should understand that the present embodiment may further include other interconnect structures.

The dynamic random access memory 200 can be formed in the memory cell region R1 by the method of the above embodiment, and the transistor structure 300 having the metal gate structure 140 can be formed in the peripheral circuit region R2. The DRAM 200 includes a capacitive contact window 120a coupled to a capacitive structure 154. The metal gate structure 140 is formed by a process using a dummy gate 120b. In addition, although the dynamic random access memory 200 and the transistor structure 300 are formed by the method of the above embodiment, the invention is not limited thereto.

Based on the above embodiments, since the capacitive contact window 120a and the dummy gate 120b are formed by the same layer of conductor layers, the process of the dynamic random access memory 200 and the transistor structure having the metal gate structure 140 can be effectively performed. The 300 process is integrated and can effectively reduce process complexity.

Hereinafter, the dynamic random access memory structure of this embodiment will be described with reference to Fig. 1H.

Referring to FIG. 1H and FIG. 2, the dynamic random access memory structure includes a substrate 100, a dynamic random access memory 200, and a guard ring structure 120c. The substrate 100 includes a memory cell region R1. The DRAM 200 is located in the memory cell region R1, wherein the DRAM memory 200 includes a capacitive contact window 120a coupled to the capacitor structure 154. The guard ring structure 120c surrounds the boundary of the memory cell region R1, and thus can effectively prevent members (e.g., dielectric layer 114) in the memory cell region R1 from being damaged during the formation of the transistor structure 300 of the peripheral circuit region R2. The capacitive contact window 120a and the guard ring structure 120c are derived from the same layer of conductor layers, thereby effectively reducing process complexity.

In this embodiment, the DRAM 200 can include a buried wire 104, a dielectric layer structure 116a, a wire structure 108, a capacitive contact window 120a, a capacitor structure 154, and a blocking layer 122. The buried wire 104 is disposed in the substrate 100. The buried conductor 104 may include a buried conductor layer 104a, and may further include a cap layer 104b and a dielectric layer 104c. The buried conductor layer 104a is disposed in the substrate 100. The cap layer 104b is disposed on the buried conductor layer 104a. The dielectric layer 104c is disposed between the buried conductor layer 104a and the substrate 100. The dielectric layer structure 116a is disposed on the substrate 100. The dielectric layer structure 116a includes a dielectric layer 106a, a barrier layer 112, and a dielectric layer 114 that are sequentially disposed on the substrate 100. The wire structure 108 is disposed on the substrate 100 and is located in the dielectric layer structure 116a. The wire structure 108 can include a conductor layer 108a, a conductor layer 108b, and a barrier layer 108c. The conductor layer 108a is disposed on the substrate 100 and may be located in the dielectric layer 106a. The conductor layer 108b is disposed on the conductor layer 108a. The barrier layer 108c is disposed between the conductor layer 108a and the conductor layer 108b. The capacitive contact window 120a is disposed in the dielectric layer structure 116a and is connected to the substrate 100. The capacitor structure 154 is disposed on the capacitor contact window 120a. The blocking layer 122 is disposed on the guard ring structure 120c and covers the memory cell region R1. The guard ring structure 120c and the blocking layer 122 can be used to protect the dielectric layer 114 in the memory cell region R1 to prevent the dielectric layer 114 from being damaged during the formation of the transistor structure 300 of the peripheral circuit region R2.

Further, the substrate 100 further includes a peripheral circuit region R2. The DRAM structure further includes a transistor structure 300 located in the peripheral circuit region R2. The transistor structure 300 can be a P-type transistor structure or an N-type transistor structure. In this embodiment, the transistor structure 300 is described by taking a P-type transistor structure as an example.

The transistor structure 300 includes a metal gate structure 140 and two doped regions 134. The metal gate structure 140 is disposed on the substrate 100. The metal gate structure 140 includes a gate dielectric layer 142, a high-k dielectric layer 144, a work function metal layer 146, and a metal gate 148 sequentially disposed on the substrate 100. The doped regions 134 are disposed in the substrate 100 on both sides of the metal gate structure 140. Additionally, the transistor structure 300 can further include at least one of the spacer 128, the lightly doped region 130, and the spacer 132. The spacers 128 and the spacers 132 are sequentially disposed on the sidewalls of the metal gate structure 140. The lightly doped region 130 is disposed in the substrate 100 and between the metal gate structure 140 and the doped region 134.

In addition, in the dynamic random access memory structure, the materials, setting manners, forming methods and effects of the components of the dynamic random access memory 200 and the transistor structure 300 have been described in detail in the foregoing, so Repeat the explanation.

According to the above embodiment, since the dynamic random access memory structure has the guard ring structure 120c surrounding the boundary of the memory cell region R1, the structure of the transistor in the memory cell region R1 in forming the peripheral circuit region R2 can be effectively prevented. The process of 140 was damaged. In addition, since the capacitive contact window 120a and the guard ring structure 120c are derived from the same layer of conductor layers, the process complexity can be effectively reduced.

3 is a cross-sectional view showing the structure of a dynamic random access memory according to another embodiment of the present invention.

Please refer to FIG. 1H and FIG. 3 simultaneously, and the difference of the dynamic random access memory structure in FIG. 3 and FIG. 1H is as follows. In the dynamic random access memory structure of FIG. 3, the peripheral circuit region R2 of the substrate 100 may include a first conductive type transistor region R21 and a second conductive type transistor region R22. The first conductive type transistor region R21 and the second conductive type transistor region R22 are one and the other of a P-type transistor region and an N-type transistor region, respectively. In addition, the dynamic random access memory structure includes a transistor structure 300 and a transistor structure 300a having different conductivity types. The transistor structure 300 and the transistor structure 300a are respectively located in the first conductive type transistor region R21 and the second conductive type transistor region R22. The difference between the transistor structure 300 and the transistor structure 300a is that the transistor structure 300a further includes a work function metal layer 146a. The work function metal layer 146a is disposed between the high-k dielectric layer 144 and the work function metal layer 146. In addition, the other components in FIG. 3 and FIG. 1H are denoted by the same reference numerals and the description thereof will be omitted.

In this embodiment, the first conductive type transistor region R21 and the second conductive type transistor region R22 are respectively exemplified by a P-type transistor region and an N-type transistor region, but the present invention does not Limited. In this case, the transistor structure 300 and the transistor structure 300a are respectively a P-type transistor structure and an N-type transistor structure, and the work function metal layer 146 and the work function metal layer 146a are respectively a P-type work function metal layer and N. Type work function metal layer.

In summary, the manufacturing method of the dynamic random access memory structure proposed in the above embodiments can effectively integrate the process of the dynamic random access memory with the process of the transistor structure having the metal gate structure, and can be integrated. Effectively reduce process complexity. In addition, the dynamic random access memory structure proposed in the above embodiments can effectively prevent components in the memory cell region from being damaged in the process of forming the transistor structure of the peripheral circuit region, and can effectively reduce the process complexity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧Isolation structure

104‧‧‧Buried wire

104a‧‧‧Buried conductor layer

104b‧‧‧Top cover

104c, 106a, 106b, 114, 136, 150, 152‧‧ dielectric layers

108‧‧‧Wire structure

108a, 108b, 160b‧‧‧ conductor layer

108c, 160a‧‧‧ barrier layer

110‧‧‧Top cover

112‧‧‧Block

116a, 116b‧‧‧ dielectric layer structure

118a, 118b, 118c, 126, 138‧‧

120a‧‧‧ Capacitive contact window

120b‧‧‧virtual gate

120c‧‧‧ guard ring structure

122‧‧‧blocking layer

128, 132‧‧‧ spacers

130‧‧‧Lightly doped area

134‧‧‧Doped area

140‧‧‧Metal gate structure

142‧‧‧gate dielectric layer

144‧‧‧High dielectric constant dielectric layer

146, 146a‧‧‧ work function metal layer

148‧‧‧Metal gate

154‧‧‧Capacitor structure

156a~156d‧‧‧Interconnection structure

160‧‧‧Contact window

162‧‧‧ wire

R1‧‧‧ memory area

R2‧‧‧ peripheral circuit area

R21‧‧‧First Conductive Oxygen Crystal Zone

R22‧‧‧Second conductive transistor area

1A through 1H are cross-sectional views showing a manufacturing process of a dynamic random access memory structure according to an embodiment of the present invention. Figure 2 is a top view of Figure 1C. 3 is a cross-sectional view showing the structure of a dynamic random access memory according to another embodiment of the present invention.

100‧‧‧Base

102‧‧‧Isolation structure

104‧‧‧Buried wire

104a‧‧‧Buried conductor layer

104b‧‧‧Top cover

104c, 106a, 106b, 114‧‧‧ dielectric layer

108‧‧‧Wire structure

108a, 108b‧‧‧ conductor layer

108c‧‧‧Barrier layer

110‧‧‧Top cover

112‧‧‧Block

116a, 116b‧‧‧ dielectric layer structure

118a, 118b, 118c‧‧‧ openings

120a‧‧‧ Capacitive contact window

120b‧‧‧virtual gate

120c‧‧‧ guard ring structure

R1‧‧‧ memory area

R2‧‧‧ peripheral circuit area

Claims (10)

A method for fabricating a dynamic random access memory structure, comprising: providing a substrate, wherein the substrate comprises a memory cell region and a peripheral circuit region; forming a dynamic random access memory in the memory cell region, wherein the dynamic random access memory The access memory includes a capacitive contact window coupled to the capacitor structure; and a transistor structure having a metal gate structure formed in the peripheral circuit region, wherein the metal gate structure is processed by using a dummy gate Formed wherein the capacitive contact window and the dummy gate are formed by the same layer of conductor layers. The method for fabricating a dynamic random access memory structure according to claim 1, further comprising forming a buried wire in the substrate, and the capacitive contact window is located at one side of the buried wire . The method of fabricating a dynamic random access memory structure according to claim 2, further comprising forming a wire structure on the substrate, wherein the wire structure is located on the other side of the buried wire. The method for fabricating a dynamic random access memory structure according to claim 1, wherein the method of forming the capacitive contact window and the dummy gate comprises: forming a dielectric layer structure on the substrate; Forming, in a portion of the dielectric layer structure in the memory cell region, a first opening exposing the substrate, and the dielectric layer in the peripheral circuit region, except for a portion of the dielectric layer structure Forming a second opening in the structure; The capacitive contact window and the dummy gate are formed in the first opening and the second opening, respectively. The method for fabricating a dynamic random access memory structure according to claim 4, further comprising: removing a portion of the dielectric layer structure, and in the dielectric layer structure in the memory cell region Forming a third opening exposing the substrate, wherein the third opening surrounds a boundary of the memory cell region; and forming a guard ring structure in the third opening, wherein the capacitive contact window and the guard ring The structure is formed by the same layer of conductors. The method of fabricating a dynamic random access memory structure according to claim 1, wherein the method of forming the metal gate structure comprises: removing the dummy gate located in the dielectric layer; Forming a fourth opening in the dielectric layer; and forming the metal gate structure in the fourth opening. A dynamic random access memory structure includes: a substrate including a memory cell; a dynamic random access memory located in the memory cell, wherein the dynamic random access memory includes a capacitor coupled to the capacitor structure a contact window; and a guard ring structure surrounding a boundary of the memory cell region, wherein the capacitive contact window and the guard ring structure are derived from the same layer of conductor layers. The dynamic random access memory structure of claim 7, further comprising a blocking layer, wherein the blocking layer is disposed on the guard ring structure and covers the memory cell region. The dynamic random access memory structure of claim 7, wherein the dynamic random access memory comprises: a buried wire disposed in the substrate; a dielectric layer structure disposed on the a substrate structure disposed on the substrate and located in the dielectric layer structure; the capacitive contact window disposed in the dielectric layer structure and connected to the substrate; and the capacitor The structure is disposed on the capacitive contact window. The dynamic random access memory structure of claim 7, wherein the substrate further comprises a peripheral circuit region, and the dynamic random access memory structure further comprises a transistor located in the peripheral circuit region. The structure, wherein the transistor structure comprises: a metal gate structure disposed on the substrate; and two doped regions disposed in the substrate on both sides of the metal gate structure.