TWI452309B - Package test method - Google Patents

Description

Package inspection method

The present invention relates to a test method, and more particularly to a package test method for a semiconductor device.

In order to obtain the advantages and disadvantages of the process in the manufacturing process of the semiconductor package component, a plurality of test keys are specially designed on the semiconductor package component, and the test keys are then connected through the test terminal and subjected to various tests to Monitor the pros and cons of each stage of the process.

After the semiconductor component covers the encapsulant and before the electroless plating, the wafers on the lead frame are electrically short-circuited. Therefore, if the semiconductor package unit is not tested, it must be completed first. Electrical isolation between the wafers.

The test method of the semiconductor package unit has a cost advantage over the test method of the singulated wafer, but a dedicated test system must be used at present. Existing test systems are mostly suitable for leaded package structures, such as: Small Outline Package and Quad Flat Package (QFP), but for leadless package structures, for example: none Small outline No-Lead (SON) and Quad Flat No-lead (QFN) have difficulties in the process of electrically isolating the wafer. In addition, in traditional package testing, the test system needs to prepare corresponding picking equipment and bearing fixtures for different package structure sizes, which require additional processes or purchase expensive equipment. And fixtures, which are a waste of production costs and time.

The present invention provides a package test method that can save production costs and process time.

The invention provides a package test method suitable for testing a semiconductor package unit. The package test method includes the following steps. A semiconductor package unit is provided that includes an encapsulant, a leadframe, and a plurality of dicing streets. The scribe line defines a plurality of semiconductor package components on the semiconductor package unit. Each of the semiconductor package components has a plurality of external connection terminals. The lead frame on the scribe line is cut to electrically insulate the semiconductor package components from each other. The semiconductor package unit is placed on the carrier wafer. The carrier wafer transfers the semiconductor package unit to a test machine. The test machine has a probe card. The probe card is placed adjacent to the semiconductor package unit mounted on the carrier wafer, and the plurality of probe terminals of the probe card are respectively brought into contact with the external connection terminals to test the semiconductor package components. Mark the test results as abnormal semiconductor package components. The semiconductor package component is singulated and the semiconductor package component marked as abnormal is removed.

Based on the above, the present invention utilizes cutting the lead frame along the dicing street to electrically insulate the semiconductor package components of the semiconductor package unit from each other, but does not completely singulate the semiconductor package components, thereby making the entire semiconductor The package unit is placed on the carrier wafer, and the semiconductor package unit is tested by using the probe card of the test wafer to know the address of the semiconductor package component whose test result is abnormal and is removed. Therefore, this embodiment It not only simplifies the packaging test process, reduces the cost of package testing, but also tests the test structure of other leadless small-size packages and small-size packages by testing the test bench of the test wafer, thus improving the use of the test machine. elasticity.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a flow chart of a package testing method in accordance with an embodiment of the present invention. 2 is a partial schematic view of a semiconductor package unit in accordance with an embodiment of the present invention. 3 is a cross-sectional view of a semiconductor package unit in accordance with an embodiment of the present invention. Referring to FIG. 1 , FIG. 2 and FIG. 3 , the package test method of the embodiment is suitable for performing a yield test on a semiconductor package unit 100. The package test method includes the following steps: First, step S110 is performed, and FIG. 2 is provided. And a semiconductor package unit 100 shown in FIG. 3, comprising an encapsulant 110, a lead frame 120 and a plurality of dicing streets 130. The dicing street 130 defines a plurality of semiconductor package components 140 on the semiconductor package unit 100. Each of the semiconductor package components 140 has a plurality of external connection terminals 122, and the external connection terminals 122 are located on the lead frame 120. In this embodiment, the semiconductor package component 140 is a small outline No-Lead package (SON package), and the external connection terminal 122 is a pad for electrical testing.

4 is a cross-sectional view of a semiconductor package unit after electrical insulation in accordance with an embodiment of the present invention. Figure 5 is an implementation in accordance with the present invention A top view of a semiconductor package unit disposed on a carrier wafer. Next, step S120 is performed. As shown in FIG. 4, the lead frame 120 is cut along the dicing street 130 to electrically insulate the semiconductor package components 140 from each other. The semiconductor package components 140 after the lead frame 120 is cut along the dicing streets 130 are connected to each other by the encapsulants 110 on the dicing streets 130. Next, step S130 is performed. As shown in FIG. 5, the semiconductor package unit 100 is placed on a carrier wafer 200. In the present embodiment, the carrier wafer 200 carries only one semiconductor package unit 100. However, in other embodiments of the present invention, the carrier wafer 200 may also carry a plurality of semiconductor package units 100 at a time. The number of semiconductor package units 100 that can be carried by the carrier wafer 200 depends on the actual size of the carrier wafer 200 and the semiconductor package unit 100, and the invention is not limited thereto.

In this embodiment, the semiconductor package unit 100 has at least one positioning hole 150, and the carrier wafer 200 has at least one positioning post 210 corresponding to the positioning hole 150. When the semiconductor package unit 100 is placed on the carrier wafer 200, the positioning post 210 enters the corresponding positioning hole 150 to position the semiconductor package unit 100 on the carrier wafer 200. In this embodiment, the positioning hole 150 and the positioning post 210 respectively have corresponding anti-dwelling structures, that is, the fitting of the positioning hole 150 and the positioning hole 150 has directivity for fixing the semiconductor package unit 100 to be placed on the bearing. One of the wafers 200 is placed in a direction to prevent manual loading in the wrong direction. For example, the positioning hole 150 may be a D-shaped through hole, and the positioning post 210 may be a D-shaped column corresponding thereto. Alternatively, the carrier wafer 200 may have a plurality of positioning posts 210 arranged in a directional manner to directionally correspond to the positioning holes 150 corresponding to the semiconductor package unit 100. The mounting is performed in a mounting direction in which the fixed semiconductor package unit 100 is placed on the carrier wafer 200. The above embodiments are merely illustrative, and the present invention does not limit the design of the anchoring structure of the positioning hole 150 and the positioning post 210.

6 is a schematic cross-sectional view showing electrical testing of a semiconductor package unit in accordance with an embodiment of the present invention. Next, step S140 is performed to transport the semiconductor package unit 100 to the test machine by the carrier wafer 200. As shown in FIG. 6, the test machine has a probe card 300, wherein the probe card 300 has a plurality of probe terminals 310. In this embodiment, the test machine is a wafer test machine. When the test is performed, the probe card 300 is moved in the direction of the semiconductor package unit 100, so that the probe card 300 is brought close to the semiconductor package unit 100 placed on the carrier wafer 200, and, as shown in FIG. 6, the probe card is made. The probe terminals 310 of 300 are respectively in contact with the external connection terminals 122 to test the respective semiconductor package components 140 (step S160).

In addition, since the thermal expansion coefficient mismatch of the encapsulant 110 and the lead frame 120 is large, when the semiconductor package unit 100 is subjected to different high-temperature processes, the semiconductor package unit 100 is often caused by an increase in operating temperature. Warpage is generated, which in turn causes the probe card 300 to be in poor contact with its external connection terminal 122. In view of this, in the embodiment, the probe card 300 may further have a plurality of pressing columns 320 respectively located at the center of the semiconductor package component 140, and the probe terminal 310 is pressed against the external connection terminal 122. The pillars 320 can press against the center of each of the semiconductor package components 140 to reduce the degree of warpage thereof to avoid a situation in which the probe card 300 and its external connection terminals 122 may be in poor contact.

7 is a semiconductor package unit in accordance with an embodiment of the present invention Schematic diagram of the cross section after singulation. Step S160 is performed to mark the semiconductor package component 140 whose test result is abnormal. Next, as shown in FIG. 7, step S170 is performed to singulate the semiconductor package component 140, and step S180 is performed to remove the semiconductor package component 140 marked as abnormal. Since the semiconductor package component 140 is a SON package, the electrically insulated semiconductor package components 140 are connected to each other by the encapsulant 110 on the scribe line 130. Therefore, in the present embodiment, the method of singulating the semiconductor package component 140 is to cut the encapsulant 110 on the dicing street 130 to separate the semiconductor package components 140.

Since the present embodiment uses the carrier wafer 200 and the probe card 300 to test the semiconductor package unit 100, the test machine divides the semiconductor package component 140 into a normal group and an abnormal group after performing the measurement. And reading the coordinate address of each semiconductor package component 140 on the carrier wafer 200 to draw it into a wafer map. Next, the semiconductor package component 140 belonging to the abnormal group on the wafer map is marked according to the coordinate address of the semiconductor package component 140 belonging to the abnormal group on the wafer map. In another embodiment of the present invention, after drawing the wafer map, the wafer map may be transferred to another machine to remove the semiconductor package component 140 belonging to the abnormal group.

In view of the above, a method of marking the semiconductor package component 140 whose test result is abnormal is, for example, an ink annotation. In the present embodiment, the ink used for the ink annotation is a general ink. However, in other embodiments of the present invention, the semiconductor package component 140 belonging to the abnormal group may also be marked by a hardening type ink, for example, a thermosetting ink (thermal Curing ink) or ultraviolet curing ink (UV curing ink). However, the use of such an ink requires an increase in the process of feeding the labeled semiconductor package component 140 into the oven to cure the hardened ink to the semiconductor package component 140.

In the above-described package test method, the lead frame 120 on the dicing street 130 is first cut off to electrically insulate the semiconductor package components 140 of the semiconductor package unit 100 from each other, but not completely singulated. The semiconductor package component 140 can thus mount the entire semiconductor package unit 100 on the carrier wafer 200 and test the semiconductor package unit 100 using the probe card 300 of the test wafer. In this way, after the conventional semiconductor package component 140 is omitted, it is necessary to pick up each semiconductor package component 140 onto the tray by a special pick-up device and then perform the test, and the conventional semiconductor package can be omitted. Component 140 purchases the cost of picking equipment and trays that match its size. Therefore, the embodiment can not only simplify the process of the package test, but also reduce the cost of the package test, and can also test the leadless small-size package structure by using the probe card of the test wafer, thereby improving the flexibility of the test machine.

8 through 11 are schematic views of a package test method in accordance with another embodiment of the present invention. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description is not repeated herein.

FIG. 8 is a partial schematic view of a semiconductor package unit in accordance with another embodiment of the present invention. Figure 9 is a half of another embodiment of the present invention. Schematic diagram of a conductor package unit. FIG. 10 is a cross-sectional view showing a semiconductor package unit after electrical insulation in accordance with another embodiment of the present invention. Referring to FIG. 8 and FIG. 9 at the same time, the package test method of this embodiment can be substantially the same as the process of the package test method of the foregoing embodiment. However, in this embodiment, each semiconductor package component 140a is a small one. The outline package (SOP) is such that each of the external connection terminals 122a is a pin, and the semiconductor package component 140a is connected in the direction of the dicing street 130 as shown in FIG. As shown in FIG. 8, the lead frame of the semiconductor package unit 100a further has a plurality of connecting rods 124 for connecting the semiconductor package components 140a in the direction parallel to the dicing streets 130.

Therefore, when the semiconductor package unit 100a of the present embodiment is electrically insulated, as shown in FIG. 10, the external connection terminals 122a on the dicing streets 130 are cut to electrically insulate the semiconductor package components 140 from each other. The electrically insulating semiconductor package components 140a are connected to each other in a direction parallel to the dicing streets 130 by connecting rods 124, respectively. Therefore, the step of singulating the semiconductor package component 140a of the present embodiment is to cut the connecting rod 124 in a direction perpendicular to the dicing street 130, so that the semiconductor package component 140a can be singulated.

11 is a cross-sectional view showing electrical testing of a semiconductor package unit in accordance with another embodiment of the present invention. Referring to FIG. 11 again, since the external connection terminal 122a of the present embodiment is a pin and there is no support underneath, the carrier wafer 200a for carrying the semiconductor package unit 100a in this embodiment has more a plurality of support portions 210a for supporting the external connection terminals 122a on the dicing streets 130, respectively, for the probes The terminal 310 provides support to the external connection terminal 122a when it comes into contact with the external connection terminal 122a.

In summary, the present invention utilizes the lead frame on the scribe line to electrically insulate the semiconductor package components of the semiconductor package unit from each other, but does not completely singulate the semiconductor package components, thereby The semiconductor package unit is placed on the carrier wafer, and the semiconductor package unit is tested using the probe card of the test wafer. Finally, a wafer map is drawn according to the test results to further mark the address of the semiconductor package component whose test result is abnormal and remove it.

Thus, the present invention eliminates the need for a conventional pick-up device to pick up each semiconductor package component onto a tray and then test it after singulating the semiconductor package component, and can eliminate the need for various semiconductor package components. The cost of purchasing pick-up equipment and pallets that match their size. Therefore, this embodiment not only simplifies the process of package testing, reduces the cost of package testing, but also tests the package structure of other leadless small-size packages and small-sized packages by testing the test bench of the test wafer, thereby improving its The flexibility of the test machine.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a‧‧‧ semiconductor package unit

110‧‧‧Package colloid

120‧‧‧ lead frame

122, 122a‧‧‧ external connection terminals

124‧‧‧ Connecting rod

130‧‧‧ cutting road

140, 140a‧‧‧ semiconductor package components

150‧‧‧Positioning holes

200, 200a‧‧‧ carrying wafer

210‧‧‧Positioning column

300‧‧‧ probe card

310‧‧‧ probe terminal

320‧‧‧Resistance column

1 is a flow chart of a package testing method in accordance with an embodiment of the present invention.

2 is a partial schematic view of a semiconductor package unit in accordance with an embodiment of the present invention.

3 is a cross-sectional view of a semiconductor package unit in accordance with an embodiment of the present invention.

4 is a cross-sectional view of a semiconductor package unit after electrical insulation in accordance with an embodiment of the present invention.

FIG. 5 is a top plan view showing a semiconductor package unit disposed on a carrier wafer in accordance with an embodiment of the invention.

6 is a schematic cross-sectional view showing electrical testing of a semiconductor package unit in accordance with an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a semiconductor package unit after singulation according to an embodiment of the invention.

FIG. 8 is a partial schematic view of a semiconductor package unit in accordance with another embodiment of the present invention.

9 is a cross-sectional view of a semiconductor package unit in accordance with another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a semiconductor package unit after electrical insulation in accordance with another embodiment of the present invention.

11 is a cross-sectional view showing electrical testing of a semiconductor package unit in accordance with another embodiment of the present invention.

S110~S180‧‧‧Steps

Claims (15)

A package test method, suitable for testing a semiconductor package unit, comprising: providing the semiconductor package unit, the semiconductor package unit comprising a package body, a lead frame and a plurality of dicing streets, the dicing lines on the semiconductor package unit Defining a plurality of semiconductor package components, each semiconductor package component having a plurality of external connection terminals on the lead frame; cutting the lead frame along the scribe lines to electrically insulate the semiconductor package components from each other; The semiconductor package unit is mounted on a carrier wafer; the semiconductor package unit is transferred to a wafer test machine by the carrier wafer, the wafer test machine has a probe card; and the probe card is brought close to the load The semiconductor package unit disposed on the carrier wafer, the plurality of probe terminals of the probe card are respectively in contact with the external connection terminal to test each of the semiconductor package components; the mark test result is abnormal The semiconductor package components; singulating the semiconductor package components; and removing the semiconductor package components marked as abnormal . The package test method of claim 1, wherein each of the semiconductor package components is a small outline No-Lead (SON). The package test method according to claim 2, wherein each of the external connection terminals is a pad. For example, the package test method described in claim 2, wherein After the lead frame is cut along the scribe lines, the semiconductor package components are connected to each other by the encapsulant located on the scribe line. The package test method of claim 4, wherein the step of singulating the semiconductor package components comprises: cutting the package paste on the scribe lines to singulate the semiconductor package components. The package test method according to claim 1, wherein each of the semiconductor package components is a Small Outline Package (SOP). The package test method according to claim 6, wherein each of the external connection terminals is a pin. The package test method of claim 7, wherein the step of cutting the lead frame along the scribe lines comprises: cutting the leads of the lead frame along the scribe lines to electrically Each of the semiconductor package components is insulated. The package test method of claim 6, wherein the lead frame of the semiconductor package unit further has a plurality of connecting rods for connecting the semiconductor package components in a direction parallel to the scribe line, and electrically insulating The semiconductor package components are connected to each other by the connecting rods. The package test method of claim 9, wherein the step of singulating the semiconductor package components comprises: cutting the connecting rods in a direction perpendicular to the scribe line to singulate the semiconductors Package components. The packaging test method described in claim 7 of the patent application, The carrier wafer has a plurality of support portions respectively supporting the pins on the scribe lines to provide support when the probe terminals are respectively in contact with the pins. The package test method of claim 1, wherein the probe card further has a plurality of pressing columns, and when the probe terminals are respectively in contact with the external connection terminals, the pressing columns respectively pressurize The center of each of the semiconductor package components. The package test method of claim 1, further comprising: after testing each of the semiconductor package components, drawing a wafer map to divide the semiconductor package components into a normal group. And an abnormal group; and marking the semiconductor package components belonging to the abnormal group on the wafer map. The package test method of claim 1, further comprising: after testing each of the semiconductor package components, drawing a wafer map to divide the semiconductor package components into a normal group. And an abnormal group; and transmitting the wafer map to a machine to remove the semiconductor package components belonging to the abnormal group. The package test method according to claim 1, wherein the method of marking the semiconductor package components with abnormal test results includes general ink annotation.