TWI394247B - Metal post chip connecting device and method free to use soldering material - Google Patents

Metal post chip connecting device and method free to use soldering material Download PDF

Info

Publication number
TWI394247B
TWI394247B TW099102171A TW99102171A TWI394247B TW I394247 B TWI394247 B TW I394247B TW 099102171 A TW099102171 A TW 099102171A TW 99102171 A TW99102171 A TW 99102171A TW I394247 B TWI394247 B TW I394247B
Authority
TW
Taiwan
Prior art keywords
metal
wafer
solder
pads
free
Prior art date
Application number
TW099102171A
Other languages
Chinese (zh)
Other versions
TW201126664A (en
Inventor
Hung Hsin Hsu
Chih Ming Ko
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW099102171A priority Critical patent/TWI394247B/en
Publication of TW201126664A publication Critical patent/TW201126664A/en
Application granted granted Critical
Publication of TWI394247B publication Critical patent/TWI394247B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

免用焊料之金屬柱晶片連接構造與方法Metal pillar wafer connection structure and method without solder

本發明係有關於半導體裝置,特別係有關於一種免用焊料之金屬柱晶片連接構造與方法。The present invention relates to semiconductor devices, and more particularly to a metal pillar wafer connection structure and method that is free of solder.

按,覆晶封裝技術(Flip-Chip)是一種先進的晶片封裝技術,能縮短了晶片與基板之間的傳輸距離,具有更優於打線連接的電性性能而逐漸普及。特別是,IBM公司之後更發展出一種創新的覆晶封裝技術,將晶片上凸塊採用金屬柱取代以往的銲球,另以焊料連接晶片上的金屬柱與基板上的接墊,在迴焊時不會有以往銲球成球的形狀改變,故金屬柱的間距可容許縮小的更為密集(凸塊間距可達到小於50微米,例如30微米),達到更高密度或是省略RDL(重配置線路層)的凸塊配置,這種技術便稱之為「金屬柱焊接的晶片連接」,也就是所謂的MPS-C2(Metal Post Solder-Chip Connection)技術。此一MPS-C2相關技術已可見於美國專利US 6,229,220 B1號「Bump structure,bump forming method and package connecting body」。According to Flip-Chip, an advanced chip packaging technology can shorten the transmission distance between the wafer and the substrate, and has become more popular than the electrical performance of the wire connection. In particular, IBM has developed an innovative flip chip packaging technology that replaces the solder balls on the wafer with metal posts and solders the metal posts on the wafer to the pads on the substrate. There is no change in the shape of the ball into the ball in the past, so the spacing of the metal columns can be allowed to shrink more densely (the bump spacing can reach less than 50 microns, such as 30 microns), to achieve higher density or to omit RDL (heavy The bump configuration of the configuration circuit layer is called "metal pillar soldered wafer connection", which is called the MPS-C2 (Metal Post Solder-Chip Connection) technology. This MPS-C2 related art is described in U.S. Patent No. 6,229,220 B1, "Bump structure, bump forming method and package connecting body".

如第1圖所示,一種習知MPS-C2架構的金屬柱晶片連接構造100主要包含一晶片110與一基板120。該晶片110係設有複數個金屬柱112,並突出於該晶片110之一表面111。該基板120之一上表面121係具有複數個接墊122,並且分別對應於該些金屬柱112。詳細而言,該些金屬柱112係藉由複數個焊料150焊接於該些接墊122上,另形成有一底部填充膠140,用以包覆該些金屬柱112、該些接墊122與該些焊料150。而達成該晶片110與該基板120之電性連接關係是以該些焊料150作為焊接界面,在材質與熔點上皆不同於該些金屬柱112與該些接墊122,易有銲點斷裂與阻抗增加的風險。As shown in FIG. 1 , a conventional metal pillar wafer connection structure 100 of the MPS-C2 architecture mainly includes a wafer 110 and a substrate 120 . The wafer 110 is provided with a plurality of metal pillars 112 and protrudes from a surface 111 of the wafer 110. One of the upper surfaces 121 of the substrate 120 has a plurality of pads 122 and corresponding to the metal pillars 112, respectively. In detail, the metal pillars 112 are soldered to the pads 122 by a plurality of solders 150, and an underfill layer 140 is formed to cover the metal pillars 112, the pads 122, and the Some solder 150. The electrical connection between the wafer 110 and the substrate 120 is achieved by using the solders 150 as soldering interfaces, which are different from the metal pillars 112 and the pads 122 in material and melting point, and are susceptible to solder joint breakage. The risk of increased impedance.

因此,傳統的MPS-C2技術在該晶片110與該基板120結合會使用該些焊料150去做晶片連接。其中,該些焊料150係可選用錫球(solder ball)或其它不同於凸塊成份的焊接劑,故在晶片連接時又需要考慮到不同材質間的金屬擴散與溼潤性,常使用到鎳(Ni)/金(Au)等作為凸塊表面鍍層,增加不少的焊接成本。此外,在後續迴焊步驟中,該些焊料150在加熱至迴焊溫度時,該些焊料150會熔化而具有流動性,當該些焊料150受到擠壓或震動會發生溢流之情況,更可能造成該些金屬柱112焊接到錯誤之接墊122,則將導致電性連接失敗。Therefore, the conventional MPS-C2 technology uses the solder 150 to make a wafer connection when the wafer 110 is combined with the substrate 120. Among them, the solder 150 can be selected from a solder ball or other solder different from the bump component, so that the diffusion and wettability of the metal between different materials need to be considered when the wafer is connected, and nickel is often used. Ni)/gold (Au) and the like are used as the surface plating of the bumps, which increases the welding cost. In addition, in the subsequent reflowing step, when the solders 150 are heated to the reflow temperature, the solders 150 are melted to have fluidity, and when the solders 150 are squeezed or vibrated, overflow may occur, and It may cause the metal posts 112 to be soldered to the wrong pads 122, which will result in failure of the electrical connection.

為了解決上述之問題,本發明之主要目的係在於一種免用焊料之金屬柱晶片連接構造與方法,不需要使用以往的焊料做晶片連接,以提升銲點的導電性,特別應用於MPS-C2(金屬柱焊接的晶片連接)產品能夠節省使用焊料接合的成本。In order to solve the above problems, the main object of the present invention is to provide a solder-free metal pillar wafer connection structure and method, which does not require the use of conventional solder for wafer connection, thereby improving the conductivity of the solder joint, especially for MPS-C2. The (metal post soldered wafer connection) product can save the cost of using solder joints.

本發明之主要目的係在於一種免用焊料之金屬柱晶片連接構造與方法,建立在金屬柱與接墊之間無焊料之U形金屬鍵合截面,大幅提升銲點的結合強度。The main object of the present invention is a solder-free metal pillar wafer connection structure and method, which establishes a U-shaped metal bonding cross section without solder between the metal pillar and the pad, and greatly improves the bonding strength of the solder joint.

本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種免用焊料之金屬柱晶片連接構造,主要包含一晶片以及一基板。該晶片係設有複數個金屬柱,係突出於該晶片之一表面,每一金屬柱係具有一頂面與兩平行側壁。該基板係具有一上表面以及複數個在該上表面之接墊,每一接墊係具有一凹穴底面與兩側凹穴側。其中,該晶片係接合於該基板之上表面,該些金屬柱之頂面係自我焊接至該些凹穴底面,該些金屬柱之兩平行側壁之局部係自我焊接至該些兩側凹穴側,以使該些金屬柱與該些接墊之間形成為無焊料之U形金屬鍵合截面。本發明另揭示上述免用焊料之金屬柱晶片連接構造之連接方法。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a solder-free metal pillar wafer connection structure, which mainly comprises a wafer and a substrate. The wafer is provided with a plurality of metal pillars protruding from one surface of the wafer, each metal pillar having a top surface and two parallel sidewalls. The substrate has an upper surface and a plurality of pads on the upper surface, each of the pads having a bottom surface of the recess and a side of the recess on both sides. Wherein, the wafer is bonded to the upper surface of the substrate, and the top surfaces of the metal pillars are self-welded to the bottom surfaces of the recesses, and the portions of the two parallel sidewalls of the metal pillars are self-welded to the two side recesses. The side is such that a U-shaped metal bonding cross section of the metal pillar and the pads is formed without solder. The present invention further discloses a method of connecting the above-described solder-free metal pillar wafer connection structure.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

在前述之金屬柱晶片連接構造中,該U形金屬鍵合截面係可為銅-銅界面。In the aforementioned metal pillar wafer connection structure, the U-shaped metal bonding cross section may be a copper-copper interface.

在前述之金屬柱晶片連接構造中,該晶片之該表面係可為一主動面。In the aforementioned metal pillar wafer connection structure, the surface of the wafer may be an active surface.

在前述之金屬柱晶片連接構造中,該些金屬柱係可更貫穿該晶片。In the aforementioned metal pillar wafer connection structure, the metal pillars may penetrate the wafer more.

在前述之金屬柱晶片連接構造中,可另包含一底部填充膠,係形成於該晶片與該基板之間,以密封該些金屬柱。In the foregoing metal pillar wafer connection structure, an underfill adhesive may be further included between the wafer and the substrate to seal the metal pillars.

在前述之金屬柱晶片連接構造中,該些接墊之凹穴深度係可不大於該些金屬柱之高度之三分之一。In the foregoing metal pillar wafer connection structure, the recess depth of the pads may be no more than one third of the height of the metal pillars.

由以上技術方案可以看出,本發明之免用焊料之金屬柱晶片連接構造與方法,有以下優點與功效:It can be seen from the above technical solutions that the solder-free metal pillar wafer connection structure and method of the present invention have the following advantages and effects:

一、可藉由金屬柱與接墊之特定組合關係作為其中一技術手段,由於每一金屬柱係具有一頂面與兩平行側壁,而每一接墊係具有一凹穴底面與兩側凹穴側,並且金屬柱之頂面係自我焊接至凹穴底面,金屬柱之兩平行側壁之局部係自我焊接至兩側凹穴側,以使金屬柱與接墊之間形成為無焊料之U形金屬鍵合截面。因此,不需要使用以往的焊料做晶片連接,以提升銲點的導電性,特別應用於MPS-C2(金屬柱焊接的晶片連接)產品時,能夠節省使用焊料接合的成本。1. A specific combination of metal pillars and pads can be used as one of the technical means, since each metal pillar has a top surface and two parallel side walls, and each of the pads has a concave bottom surface and two concave sides. The side of the hole, and the top surface of the metal post is self-welded to the bottom surface of the recess, and the portions of the two parallel side walls of the metal post are self-welded to the side of the recess on both sides, so that a solder-free U is formed between the metal post and the pad. Shaped metal bond cross section. Therefore, it is not necessary to use conventional solder as a wafer connection to improve the conductivity of the solder joint, and in particular, when it is applied to an MPS-C2 (metal pillar soldered wafer connection) product, the cost of using the solder joint can be saved.

二、可藉由金屬柱與接墊之特定組合關係作為其中一技術手段,由於每一金屬柱係具有一頂面與兩平行側壁,而每一接墊係具有一凹穴底面與兩側凹穴側,並,利用熱、壓力與超音波施加予晶片以建立在金屬柱與接墊之間的無焊料之U形金屬鍵合截面。因此,可大幅提升銲點的結合強度。Second, the specific combination relationship between the metal post and the pad can be used as one of the technical means, since each metal post has a top surface and two parallel side walls, and each of the pads has a concave bottom surface and two concave sides. The side of the hole is applied to the wafer by heat, pressure and ultrasonic waves to establish a solder-free U-shaped metal bond cross section between the metal post and the pad. Therefore, the bonding strength of the solder joint can be greatly improved.

以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

依據本發明之第一具體實施例,一種免用焊料之金屬柱晶片連接構造舉例說明於第2圖之截面示意圖以及第3A至3C圖在覆晶接合過程中元件截面示意圖。該免用焊料之金屬柱晶片連接構造200係主要包含一晶片210以及一基板220。According to a first embodiment of the present invention, a solder-free metal pillar wafer connection structure is illustrated in a cross-sectional view of FIG. 2 and a cross-sectional view of the elements in the flip-chip bonding process in FIGS. 3A to 3C. The solder-free metal pillar wafer connection structure 200 mainly includes a wafer 210 and a substrate 220.

請參閱第2圖所示,該晶片210係設有複數個金屬柱212,係突出於該晶片210之一表面211,每一金屬柱212係具有一頂面213與兩平行側壁214。詳細而言,該晶片210係已形成有積體電路(integrated circuit,IC)元件,例如記憶體、邏輯元件以及特殊應用積體電路(ASIC),可由一晶圓(wafer)分割成顆粒狀。在本實施例中,該晶片210之該表面211係可為一主動面,即積體電路的形成表面。詳細而言,在該表面211(即主動面)係可另形成有複數個銲墊(圖中未繪出),供該些金屬柱212之設置,在銲墊與金屬柱之間另可設置凸塊下金屬層(圖中未繪出),以避免金屬柱內成份的金屬擴散。該些金屬柱212之材質可包含金、銅、鋁或其合金,可利用電鍍方式以形成柱狀。較佳地,可利用研磨或表面平坦技術,使該頂面213為平坦並有相同之高度。As shown in FIG. 2, the wafer 210 is provided with a plurality of metal pillars 212 protruding from a surface 211 of the wafer 210. Each of the metal pillars 212 has a top surface 213 and two parallel sidewalls 214. In detail, the wafer 210 has formed an integrated circuit (IC) component such as a memory, a logic component, and an application specific integrated circuit (ASIC), which can be divided into a pellet by a wafer. In this embodiment, the surface 211 of the wafer 210 can be an active surface, that is, a forming surface of the integrated circuit. In detail, a plurality of solder pads (not shown) may be formed on the surface 211 (ie, the active surface) for the metal pillars 212 to be disposed between the solder pads and the metal pillars. A metal layer under the bump (not shown) to avoid metal diffusion of the components in the metal pillar. The material of the metal pillars 212 may include gold, copper, aluminum or an alloy thereof, and may be formed into a columnar shape by electroplating. Preferably, the top surface 213 is flat and has the same height using abrasive or surface flattening techniques.

該基板220係具有一上表面221以及複數個在該上表面221之接墊222,每一接墊222係具有一凹穴底面223與兩側凹穴側224。詳細而言,該基板220係可為一印刷電路板(printed circuit board,PCB),作為半導體封裝結構內晶片承載與電性連接之媒介物。在一較佳實施例中,每一接墊222之兩凹穴側224之距離係可不大於對應之每一金屬柱212之兩平行側壁214之距離,以確保在覆晶接合中該些平行側壁214能摩擦接觸該些凹穴側224。該些接墊222之材質可包含銅,該凹穴底面223與該兩側凹穴側224之形成可利用圖案化蝕刻或圖案化電鍍技術達成。在一較佳實施例中,該些接墊222之凹穴深度係可不大於該些金屬柱212之高度之三分之一,以避免該些金屬柱212過度嵌埋於該些接墊222內並保持該晶片210與該基板220之間不可摩擦接觸之間隙。此外,在本實施例中,該些金屬柱212與該些接墊222係可具有相同之材質,例如,該些金屬柱212可為銅柱(Cu post),而該些接墊222亦可為銅槽(Cu cave)。The substrate 220 has an upper surface 221 and a plurality of pads 222 on the upper surface 221. Each of the pads 222 has a recess bottom surface 223 and two side pocket sides 224. In detail, the substrate 220 can be a printed circuit board (PCB) as a medium for carrying and electrically connecting the wafers in the semiconductor package structure. In a preferred embodiment, the distance between the two pocket sides 224 of each pad 222 may be no greater than the distance between the two parallel sidewalls 214 of each of the corresponding metal posts 212 to ensure the parallel sidewalls in the flip chip bond. 214 can frictionally contact the pocket sides 224. The material of the pads 222 may comprise copper, and the formation of the recess bottom surface 223 and the two side pocket sides 224 may be achieved by pattern etching or pattern plating. In a preferred embodiment, the depth of the recesses of the pads 222 may be no more than one third of the height of the metal pillars 212 to prevent the metal pillars 212 from being excessively embedded in the pads 222. And maintaining a gap between the wafer 210 and the substrate 220 that is not in frictional contact. In addition, in the present embodiment, the metal pillars 212 and the pads 222 may have the same material. For example, the metal pillars 212 may be Cu posts, and the pads 222 may also be used. It is a copper cave.

此外,該晶片210係接合於該基板220之上表面221,該些金屬柱212之頂面213係自我焊接至該些凹穴底面223,該些金屬柱212之兩平行側壁214之局部係自我焊接至該些兩側凹穴側224,以使該些金屬柱212與該些接墊222之間形成為無焊料之U形金屬鍵合截面230。換言之,該U形金屬鍵合截面230係包含至少三個接合界面而呈非平面,上述的「接合界面」係位於該頂面213與該凹穴底面223之間以及兩平行側壁214與對應之兩凹穴側224之間。而「自我焊接」所指為利用該些金屬柱212表面的金屬原子活化擴散,而與該些接墊222形成相互金屬鍵結,不需要假借外加的焊料、凸塊鍍層或其它接合劑,基本上會在該U形金屬鍵合截面230產生斷續的金屬晶格界面,故在自我焊接之後在該些金屬柱212與該些接墊222之間的阻抗不會昇高,以「無焊料之U形金屬鍵合截面」作為銲點可達到較佳的導電性。在本實施例中,該U形金屬鍵合截面230係可為銅-銅界面或金-金界面,其中以銅-銅界面的成本較低。因此,該U形金屬鍵合截面230係不會有其它雜質、脆弱的鑄造結構或介金屬化合物的存在,而能形成較為平整無縫隙之接合面,不需要使用以往的焊料做晶片連接,以提升銲點的導電性。In addition, the wafer 210 is bonded to the upper surface 221 of the substrate 220. The top surface 213 of the metal pillars 212 is self-welded to the bottom surfaces 223 of the recesses. Solder to the two side pocket sides 224 to form a solder-free U-shaped metal bond cross section 230 between the metal posts 212 and the pads 222. In other words, the U-shaped metal bonding section 230 is at least three bonding interfaces and is non-planar. The above-mentioned "joining interface" is located between the top surface 213 and the bottom surface 223 of the recess and the two parallel sidewalls 214 and corresponding Between the two pocket sides 224. The term "self-welding" refers to the use of metal atoms on the surface of the metal pillars 212 to activate diffusion, and form a mutual metal bond with the pads 222, without the need for additional solder, bump plating or other bonding agents. The U-shaped metal bonding section 230 generates an intermittent metal lattice interface, so that the impedance between the metal pillars 212 and the pads 222 does not rise after self-welding, The U-shaped metal bonding cross section can achieve better conductivity as a solder joint. In this embodiment, the U-shaped metal bonding section 230 can be a copper-copper interface or a gold-gold interface, wherein the copper-copper interface is less expensive. Therefore, the U-shaped metal bonding section 230 does not have other impurities, a fragile cast structure or a metal-containing compound, and can form a relatively flat joint surface without using conventional solder for wafer bonding. Improve the electrical conductivity of the solder joints.

此外,該免用焊料之金屬柱晶片連接構造200可另包含一底部填充膠240(underfill material),係形成於該晶片210與該基板220之間,以密封該些金屬柱212。藉由該底部填充膠240在固化前的高流動性,用以避免該晶片210與該基板220之間形成空隙。在一較佳實施例中,該底部填充膠240係可選用硬度較高之材料,除了能保護該些金屬柱212之外,更可以補強整體的結構強度。In addition, the solder-free metal pillar wafer connection structure 200 may further include an underfill material formed between the wafer 210 and the substrate 220 to seal the metal pillars 212. The high fluidity of the underfill 240 prior to curing is used to avoid void formation between the wafer 210 and the substrate 220. In a preferred embodiment, the underfill 240 is selected from a higher hardness material, and in addition to protecting the metal posts 212, the overall structural strength can be enhanced.

因此,本發明藉由金屬柱與接墊之特定組合關係作為其中一技術手段,毋須以往的焊料做晶片連接特別應用於MPS-C2(金屬柱焊接的晶片連接)產品能夠節省使用焊料接合的成本。這是因為每一金屬柱212係具有一頂面213與兩平行側壁214,並且每一接墊222係具有一凹穴底面223與兩側凹穴側224,並且該些金屬柱212之頂面213係自我焊接至該些凹穴底面223,該些金屬柱212之兩平行側壁214之局部係自我焊接至對應之兩側凹穴側224,以使該些金屬柱212與該些接墊222之間形成為無焊料之U形金屬鍵合截面230。此外,更大幅提升銲點的結合強度與導電性,免除了傳統使用焊料接合時易有焊銲點斷裂與阻抗增加的風險。Therefore, the present invention utilizes a specific combination of metal pillars and pads as one of the technical means, and does not require conventional solder for wafer bonding, particularly for MPS-C2 (metal pillar soldered wafer bonding) products, which can save the cost of using solder joints. . This is because each of the metal posts 212 has a top surface 213 and two parallel side walls 214, and each of the pads 222 has a recess bottom surface 223 and two side pocket sides 224, and the top surfaces of the metal pillars 212 213 is self-welded to the bottom surface 223 of the recess, and the portions of the two parallel sidewalls 214 of the metal pillars 212 are self-welded to the corresponding side pockets 224 of the two sides, so that the metal pillars 212 and the pads 222 are 222. A U-shaped metal bond cross section 230 is formed between the solders. In addition, the bonding strength and conductivity of the solder joints are greatly improved, which eliminates the risk of solder joint breakage and impedance increase when solder joints are conventionally used.

本發明還揭示該免用焊料之金屬柱晶片連接構造200的一種可行但非限定的製造方法,舉例說明於第3A至3C圖在製程中元件截面示意圖,用以清楚彰顯本發明之其中一功效,其詳細步驟說明如下所示。The present invention also discloses a possible but non-limiting manufacturing method of the solder-free metal pillar wafer connection structure 200, illustrating a cross-sectional view of the components in the process of FIGS. 3A to 3C for clearly demonstrating one of the effects of the present invention. The detailed steps are as follows.

首先,請參閱第3A圖所示,提供該晶片210,係設有複數個金屬柱212,係突出於該晶片210之一表面211,每一金屬柱212係具有一頂面213與兩平行側壁214。該些頂面213係不需要沾附習知所使用的焊料,除了毋須擔心會有焊料汙染問題之外,更可節省不少焊料之設置成本。First, as shown in FIG. 3A, the wafer 210 is provided with a plurality of metal pillars 212 protruding from a surface 211 of the wafer 210. Each of the metal pillars 212 has a top surface 213 and two parallel sidewalls. 214. The top surfaces 213 do not need to adhere to the solder used in the prior art, and in addition to worrying about solder contamination problems, the installation cost of the solder can be saved.

請參閱第3B圖所示,提供該基板220,在該基板220之上表面221設有複數個接墊222,每一接墊222係具有一凹穴底面223與兩側凹穴側224。具體而言,每一凹穴底面223與對應之兩側凹穴側224係可形成猶如U形槽之結構。Referring to FIG. 3B, the substrate 220 is provided. The upper surface 221 of the substrate 220 is provided with a plurality of pads 222. Each of the pads 222 has a recess bottom surface 223 and two side pocket sides 224. Specifically, each of the pocket bottom surface 223 and the corresponding two side pocket sides 224 can form a structure like a U-shaped groove.

請參閱第3C圖所示,執行一覆晶接合之步驟,以接合該晶片210於該基板220之上表面221。經由一吸附式熱壓合治具(圖中未繪出)傳送熱、壓力與超音波並施加予該晶片210,以使該些金屬柱212之頂面213係自我焊接至該些凹穴底面223,該些金屬柱212之兩平行側壁214之局部係自我焊接至該些兩側凹穴側224,以使該些金屬柱212與該些接墊222之間形成為無焊料之U形金屬鍵合截面230。其中,所謂的「超音波」係指振動頻率不小於2萬赫茲(Hz),對該晶片210及其金屬柱212產生每秒2萬次至4萬次的高頻率橫向振動,使得該些金屬柱212與該些接墊222的接合面因高頻振動而表面熔接,誘發原子擴散以形成相互金屬的原子結合,故不需要助熔劑也不需要通電流與加熱到該些金屬柱212之熔點。利用適當加熱該晶片210但不需要到達該些金屬柱212之熔點,以使連接在該晶片210之金屬柱212同時受熱而膨脹,同一金屬柱212之兩平行側壁214之距離可略大於對應接墊222之兩平行側壁214之距離,藉以增加該些金屬柱212之兩平行側壁214之局部與該些兩側凹穴側224的摩擦接觸,以達到側邊垂直向的自我焊接。利用施壓予該晶片210,確保該些金屬柱212之頂面213與該些凹穴底面223的摩擦接觸,以達到中央水平向的自我焊接。因此,利用熱、壓力與超音波施加予該晶片210,能夠在該些金屬柱212與該些接墊222之間建立無焊料之U形金屬鍵合截面230,可大幅提升銲點的結合強度。Referring to FIG. 3C, a flip chip bonding step is performed to bond the wafer 210 to the upper surface 221 of the substrate 220. Heat, pressure and ultrasonic waves are transmitted to the wafer 210 via an adsorption thermocompression fixture (not shown) so that the top surfaces 213 of the metal pillars 212 are self-welded to the bottom surfaces of the recesses. 223, a portion of the two parallel sidewalls 214 of the metal pillars 212 are self-welded to the two side pocket sides 224, so that the metal pillars 212 and the pads 222 are formed as a solderless U-shaped metal. Bonding section 230. Here, the term "ultrasonic" means that the vibration frequency is not less than 20,000 Hz, and the wafer 210 and its metal pillar 212 are subjected to high-frequency lateral vibration of 20,000 to 40,000 times per second, so that the metals The joint surface of the pillar 212 and the pads 222 is surface-welded by high-frequency vibration, and the atom diffusion is induced to form atomic bonding of the mutual metal, so that no flux and no electric current and heating to the melting point of the metal pillars 212 are required. . By properly heating the wafer 210 but not reaching the melting points of the metal pillars 212, the metal pillars 212 connected to the wafer 210 are simultaneously heated and expanded, and the distance between the two parallel sidewalls 214 of the same metal pillar 212 may be slightly larger than the corresponding connection. The distance between the two parallel sidewalls 214 of the pad 222 is to increase the frictional contact between the portions of the two parallel sidewalls 214 of the metal posts 212 and the two side pocket sides 224 to achieve vertical self-welding of the sides. By applying pressure to the wafer 210, the top surface 213 of the metal pillars 212 is brought into frictional contact with the recessed bottom surfaces 223 to achieve a central horizontal self-welding. Therefore, by applying heat, pressure and ultrasonic waves to the wafer 210, a solder-free U-shaped metal bonding cross section 230 can be established between the metal pillars 212 and the pads 222, which can greatly improve the bonding strength of the solder joints. .

第4A至4C圖為該金屬柱晶片連接構造200繪示其金屬柱、接墊與在覆晶接合過程中結合之示意圖。如第4A圖所示,每一金屬柱212之該頂面213係可為矩形,而每一金屬柱212除了具有上述的兩平行側壁214之外,可另具有一對平行的壁面,故使得該些金屬柱212形成為長方體。此外,如第4B與4C圖所示,每一接墊222之該凹穴底面223之面積係可不大於對應之頂面213之面積。更具體地,當該些金屬柱212接合至該些接墊222時,利用熱、壓力與超音波施加予該晶片210,該些頂面213與對應之凹穴底面223以及該些平行側壁214與對應之凹穴側224之間快速地振動摩擦,以使該些金屬柱212之頂面213自我焊接至該些凹穴底面223,以及該些金屬柱212之兩平行側壁214之局部自我焊接至該些兩側凹穴側224。第4C圖中箭頭所指方向即為利用超音波之振動方向,其係平行於該些平行側壁214與該些凹穴側224。4A-4C are schematic views showing the metal post wafer connection structure 200 showing the combination of the metal post and the pad and the flip chip bonding process. As shown in FIG. 4A, the top surface 213 of each metal pillar 212 may be rectangular, and each metal pillar 212 may have a pair of parallel wall surfaces in addition to the two parallel sidewalls 214 described above, thereby The metal pillars 212 are formed in a rectangular parallelepiped shape. In addition, as shown in FIGS. 4B and 4C, the area of the bottom surface 223 of each of the pads 222 may not be larger than the area of the corresponding top surface 213. More specifically, when the metal pillars 212 are bonded to the pads 222, the wafers 210 are applied by heat, pressure and ultrasonic waves, the top surfaces 213 and the corresponding recess bottom surfaces 223 and the parallel sidewalls 214. Quickly vibrating friction with the corresponding pocket side 224 to self-weld the top surface 213 of the metal posts 212 to the bottom surfaces 223 of the recesses, and the partial self-welding of the two parallel sidewalls 214 of the metal posts 212 To the two side pocket sides 224. The direction indicated by the arrow in Fig. 4C is the direction of vibration using the ultrasonic waves, which is parallel to the parallel side walls 214 and the pocket sides 224.

第5A至5C圖為在一變化實施例中該金屬柱晶片連接構造200繪示其金屬柱、接墊與在覆晶接合過程中結合之示意圖,用以說明不限定金屬柱之頂面與接墊之凹穴底面之形狀。如第5A圖所示,每一金屬柱212之該頂面213a係可為正方形,而能具有兩對相互平行且相等之平行側壁214a。並且,如第5B圖所示,每一接墊222係凹陷而形成猶如一容置槽之形狀,除了具有兩側凹穴側224a之外,更形成有另一對平行的側壁。更進一步地,該些接墊222之凹穴底面223a之形狀係可為長方形,並且該些接墊222之凹穴底面223a之面積係可大於該些金屬柱212之頂面213a之面積,以利自我焊接該些金屬柱212之頂面213a至該些凹穴底面223a。此外,該些凹穴底面223a之較短邊(即接墊222之兩凹穴側224a的距離)係不大於對應金屬柱212之頂面213a之對應邊長(即金屬柱212之兩平行側壁214a的距離),故在該晶片210與該基板220接合時,依照第5C圖箭頭所指的超音波振動方向,該些金屬柱212之兩平行側壁214a能高頻振動摩擦至對應之該些接墊222之兩凹穴側224a,以利自我焊接該些金屬柱212之兩平行側壁214a至該些兩側凹穴側224a。5A to 5C are diagrams showing a metal pillar wafer connection structure 200 in a modified embodiment, illustrating a metal pillar, a pad and a combination in a flip chip bonding process, to illustrate that the top surface of the metal pillar is not limited. The shape of the bottom surface of the pad. As shown in FIG. 5A, the top surface 213a of each of the metal posts 212 can be square and can have two pairs of mutually parallel and equal parallel sidewalls 214a. Moreover, as shown in FIG. 5B, each of the pads 222 is recessed to form a shape like a receiving groove, and has two pairs of parallel side walls in addition to the side pocket sides 224a. Further, the shape of the bottom surface 223a of the pads 222 may be a rectangle, and the area of the bottom surface 223a of the pads 222 may be larger than the area of the top surface 213a of the metal pillars 212. The top surface 213a of the metal pillars 212 is self-welded to the recess bottom surfaces 223a. In addition, the shorter sides of the bottom surfaces 223a of the recesses (ie, the distances between the two recess sides 224a of the pads 222) are not greater than the corresponding side lengths of the top surfaces 213a of the corresponding metal pillars 212 (ie, the two parallel sidewalls of the metal pillars 212). 214a), when the wafer 210 is bonded to the substrate 220, according to the ultrasonic vibration direction indicated by the arrow in FIG. 5C, the two parallel sidewalls 214a of the metal pillars 212 can be ultrasonically vibrated to the corresponding ones. The two recess sides 224a of the pad 222 are used to self-weld the two parallel sidewalls 214a of the metal posts 212 to the two side recess sides 224a.

依據本發明之第二具體實施例,另一種免用焊料之金屬柱晶片連接構造300舉例說明於第6圖之截面示意圖。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。In accordance with a second embodiment of the present invention, another solder free metal pillar wafer connection configuration 300 is illustrated in cross-section in FIG. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described in detail.

請參閱第6圖所示,該免用焊料之金屬柱晶片連接構造300係主要包含一晶片210與一基板220。該晶片210係設有複數個金屬柱212,係突出於該晶片210之一表面211,每一金屬柱212係具有一頂面213與兩平行側壁214。該基板220係具有一上表面221以及複數個在該上表面221之接墊222,每一接墊222係具有一凹穴底面223與兩側凹穴側224。其中,該晶片210係接合於該基板220之上表面221,該些金屬柱212之頂面213係自我焊接至該些凹穴底面223,該些金屬柱212之兩平行側壁214之局部係自我焊接至該些兩側凹穴側224,以使該些金屬柱212與該些接墊222之間形成為無焊料之U形金屬鍵合截面230。較佳地,該些金屬柱212係可更貫穿該晶片210。更進一步地,該晶片210被該些金屬柱212貫穿處係可形成有複數個貫通孔315,並且每一貫通孔315之孔壁係設置有一電鍍層316。該些電鍍層316係可選用導電材料,例如:銅(Cu)。詳細而言,該些貫通孔315也就是所謂的矽穿孔(Though Silicon Via,TSV)。藉由該些金屬柱212貫穿該晶片210之結構能提供垂直電性導通與穩固該些金屬柱212之作用,有助於該晶片210至該些金屬柱212之超音波振動傳導,以促進該U形金屬鍵合截面230之形成。在本實施例中,該些金屬柱212之突出表面211係可為該晶片210之背面,故該晶片210之主動面則遠離該基板220,以達到較佳散熱效果。此外,該些金屬柱212的外露端面可立體堆疊另一晶片。Referring to FIG. 6, the solder-free metal pillar wafer connection structure 300 mainly includes a wafer 210 and a substrate 220. The wafer 210 is provided with a plurality of metal pillars 212 protruding from a surface 211 of the wafer 210. Each of the metal pillars 212 has a top surface 213 and two parallel sidewalls 214. The substrate 220 has an upper surface 221 and a plurality of pads 222 on the upper surface 221. Each of the pads 222 has a recess bottom surface 223 and two side pocket sides 224. The wafer 210 is bonded to the upper surface 221 of the substrate 220. The top surface 213 of the metal pillars 212 is self-welded to the bottom surface 223 of the recess. The two parallel sidewalls 214 of the metal pillars 212 are self-contained. Solder to the two side pocket sides 224 to form a solder-free U-shaped metal bond cross section 230 between the metal posts 212 and the pads 222. Preferably, the metal pillars 212 can penetrate the wafer 210 more. Further, a plurality of through holes 315 may be formed in the through hole of the metal pillars 212, and a plating layer 316 is disposed on the hole walls of each of the through holes 315. The plating layer 316 may be selected from a conductive material such as copper (Cu). In detail, the through holes 315 are also called so-called through silicon vias (TSVs). The structure of the metal pillars 212 extending through the wafer 210 can provide vertical electrical conduction and stabilize the metal pillars 212, thereby facilitating ultrasonic vibration conduction of the wafer 210 to the metal pillars 212 to promote the The U-shaped metal bond section 230 is formed. In this embodiment, the protruding surface 211 of the metal pillars 212 can be the back surface of the wafer 210, so that the active surface of the wafer 210 is away from the substrate 220 for better heat dissipation. In addition, the exposed end faces of the metal pillars 212 can vertically stack another wafer.

以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100...金屬柱晶片連接構造100. . . Metal column wafer connection structure

110...晶片110. . . Wafer

111...表面111. . . surface

112...金屬柱112. . . Metal column

120...基板120. . . Substrate

121...上表面121. . . Upper surface

122...接墊122. . . Pad

140...底部填充膠140. . . Underfill

150...焊料150. . . solder

200...免用焊料之金屬柱晶片連接構造200. . . Metal pillar wafer connection structure without solder

210...晶片210. . . Wafer

211...表面211. . . surface

212...金屬柱212. . . Metal column

213...頂面213. . . Top surface

213a...頂面213a. . . Top surface

214...平行側壁214. . . Parallel side wall

214a...平行側壁214a. . . Parallel side wall

220...基板220. . . Substrate

221...上表面221. . . Upper surface

222...接墊222. . . Pad

223...凹穴底面223. . . Underside of the pocket

223a...凹穴底面223a. . . Underside of the pocket

224...凹穴側224. . . Pocket side

224a...凹穴側224a. . . Pocket side

230...U形金屬鍵合截面230. . . U-shaped metal bonding section

240...底部填充膠240. . . Underfill

300...免用焊料之金屬柱晶片連接構造300. . . Metal pillar wafer connection structure without solder

315...貫通孔315. . . Through hole

316...電鍍層316. . . Plating

第1圖:為習知的金屬柱晶片連接構造之截面示意圖。Fig. 1 is a schematic cross-sectional view showing a conventional metal column wafer connection structure.

第2圖:依據本發明之第一具體實施例的一種免用焊料之金屬柱晶片連接構造之截面示意圖。2 is a cross-sectional view showing a solder-free metal pillar wafer connection structure in accordance with a first embodiment of the present invention.

第3A至3C圖:依據本發明之第一具體實施例的金屬柱晶片連接構造之覆晶接合過程中元件截面示意圖。3A to 3C are cross-sectional views showing the elements in the flip chip bonding process of the metal post wafer connection structure according to the first embodiment of the present invention.

第4A至4C圖:依據本發明之第一具體實施例的金屬柱晶片連接構造繪示其金屬柱、接墊與在覆晶接合過程中結合之示意圖。4A to 4C are views showing a metal post wafer connection structure according to a first embodiment of the present invention, showing a combination of a metal post and a pad and a bonding process in a flip chip bonding process.

第5A至5C圖:依據本發明之一變化實施例的金屬柱晶片連接構造繪示其金屬柱、接墊與在覆晶接合過程中結合之示意圖。5A to 5C are views showing a metal post wafer connection structure according to a variant embodiment of the present invention, showing a combination of a metal post and a pad and a bonding process in a flip chip bonding process.

第6圖:依據本發明之第二具體實施例的另一種免用焊料之金屬柱晶片連接構造之截面示意圖。Figure 6 is a cross-sectional view showing another solder-free metal post wafer connection structure in accordance with a second embodiment of the present invention.

200...免用焊料之金屬柱晶片連接構造200. . . Metal pillar wafer connection structure without solder

210...晶片210. . . Wafer

211...表面211. . . surface

212...金屬柱212. . . Metal column

213...頂面213. . . Top surface

214...平行側壁214. . . Parallel side wall

220...基板220. . . Substrate

221...上表面221. . . Upper surface

222...接墊222. . . Pad

223...凹穴底面223. . . Underside of the pocket

224...凹穴側224. . . Pocket side

230...U形金屬鍵合截面230. . . U-shaped metal bonding section

240...底部填充膠240. . . Underfill

Claims (10)

一種免用焊料之金屬柱晶片連接構造,包含:一晶片,係設有複數個金屬柱,係突出於該晶片之一表面,每一金屬柱係具有一頂面與兩平行側壁;以及一基板,係具有一上表面以及複數個在該上表面之接墊,每一接墊係具有一凹穴底面與兩側凹穴側;其中,該晶片係接合於該基板之上表面,該些金屬柱之頂面係自我焊接至該些凹穴底面,該些金屬柱之兩平行側壁之局部係自我焊接至該些兩側凹穴側,以使該些金屬柱與該些接墊之間形成為無焊料之U形金屬鍵合截面。A solder-free metal pillar wafer connection structure comprising: a wafer having a plurality of metal pillars protruding from a surface of the wafer, each metal pillar having a top surface and two parallel sidewalls; and a substrate Having an upper surface and a plurality of pads on the upper surface, each pad having a bottom surface of the recess and a side of the recess on both sides; wherein the wafer is bonded to the upper surface of the substrate, the metal The top surface of the column is self-welded to the bottom surface of the recesses, and the portions of the two parallel side walls of the metal posts are self-welded to the side of the two side pockets to form a gap between the metal pillars and the pads. It is a U-shaped metal bond cross section without solder. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接構造,其中該U形金屬鍵合截面係為銅-銅界面。The metal pillar wafer connection structure of the solder-free solder according to the first aspect of the patent application, wherein the U-shaped metal bonding cross section is a copper-copper interface. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接構造,其中該晶片之該表面係為一主動面。The metal pillar wafer connection structure of the solder-free solder according to the first aspect of the patent application, wherein the surface of the wafer is an active surface. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接構造,其中該些金屬柱係更貫穿該晶片。The metal pillar wafer connection structure of the solder-free solder according to the first aspect of the patent application, wherein the metal pillars penetrate the wafer. 依據申請專利範圍第1、2、3或4項之免用焊料之金屬柱晶片連接構造,另包含一底部填充膠,係形成於該晶片與該基板之間,以密封該些金屬柱。The metal pillar wafer connection structure of the solder-free solder according to the first, second, third or fourth aspect of the patent application, further comprising an underfill layer formed between the wafer and the substrate to seal the metal pillars. 依據申請專利範圍第1、2、3或4項之免用焊料之金屬柱晶片連接構造,其中該些接墊之凹穴深度係不大於該些金屬柱之高度之三分之一。A metal pillar wafer connection structure exempt from solder according to claim 1, 2, 3 or 4, wherein the pads have a recess depth not greater than one third of the height of the metal posts. 一種免用焊料之金屬柱晶片連接方法,包含:提供一晶片,係設有複數個金屬柱,係突出於該晶片之一表面,每一金屬柱係具有一頂面與兩平行側壁;提供一基板,係具有一上表面以及複數個在該上表面之接墊,每一接墊係具有一凹穴底面與兩側凹穴側;以及接合該晶片於該基板之上表面,利用熱、壓力與超音波施加予該晶片令該些金屬柱之頂面係自我焊接至該些凹穴底面,該些金屬柱之兩平行側壁之局部係自我焊接至該些兩側凹穴側,以使該些金屬柱與該些接墊之間形成為無焊料之U形金屬鍵合截面。A solder-free metal pillar wafer connection method includes: providing a wafer with a plurality of metal pillars protruding from a surface of the wafer, each metal pillar having a top surface and two parallel sidewalls; The substrate has an upper surface and a plurality of pads on the upper surface, each of the pads having a bottom surface of the recess and the side of the recess on both sides; and bonding the wafer to the upper surface of the substrate, utilizing heat and pressure Applying to the wafer with ultrasonic waves, the top surfaces of the metal pillars are self-welded to the bottom surfaces of the recesses, and the portions of the two parallel sidewalls of the metal pillars are self-welded to the side of the two recesses so that the A metal-free metal-bonded cross section is formed between the metal pillars and the pads. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接方法,其中該U形金屬鍵合截面係為銅-銅界面。A method of joining metal pillar wafers excluding solder according to the first aspect of the patent application, wherein the U-shaped metal bonding cross section is a copper-copper interface. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接方法,其中該晶片之該表面係為一主動面。A method of joining a solder-free metal pillar wafer according to claim 1, wherein the surface of the wafer is an active surface. 依據申請專利範圍第1項之免用焊料之金屬柱晶片連接方法,其中該些金屬柱係更貫穿該晶片。A metal pillar wafer bonding method for solder-free, according to the first aspect of the patent application, wherein the metal pillars penetrate the wafer.
TW099102171A 2010-01-26 2010-01-26 Metal post chip connecting device and method free to use soldering material TWI394247B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW099102171A TWI394247B (en) 2010-01-26 2010-01-26 Metal post chip connecting device and method free to use soldering material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099102171A TWI394247B (en) 2010-01-26 2010-01-26 Metal post chip connecting device and method free to use soldering material

Publications (2)

Publication Number Publication Date
TW201126664A TW201126664A (en) 2011-08-01
TWI394247B true TWI394247B (en) 2013-04-21

Family

ID=45024600

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099102171A TWI394247B (en) 2010-01-26 2010-01-26 Metal post chip connecting device and method free to use soldering material

Country Status (1)

Country Link
TW (1) TWI394247B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12015000B2 (en) 2016-01-06 2024-06-18 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097742B (en) * 2014-05-05 2019-09-06 中芯国际集成电路制造(上海)有限公司 Wire bonding structure and wire bonding method
US11367709B2 (en) * 2018-06-05 2022-06-21 PAC Tech—Packaging Technologies GmbH Semiconductor chip stack arrangement and semiconductor chip for producing such a semiconductor chip stack arrangement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200711018A (en) * 2005-08-31 2007-03-16 Micron Technology Inc Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
TW200822284A (en) * 2006-07-25 2008-05-16 Ibm Metal filled through via structure for providing vertical wafer-to-wafer interconnection
TW200905764A (en) * 2007-07-31 2009-02-01 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200711018A (en) * 2005-08-31 2007-03-16 Micron Technology Inc Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
TW200822284A (en) * 2006-07-25 2008-05-16 Ibm Metal filled through via structure for providing vertical wafer-to-wafer interconnection
TW200905764A (en) * 2007-07-31 2009-02-01 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12015000B2 (en) 2016-01-06 2024-06-18 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Also Published As

Publication number Publication date
TW201126664A (en) 2011-08-01

Similar Documents

Publication Publication Date Title
US8237273B2 (en) Metal post chip connecting device and method free to use soldering material
JP4074862B2 (en) Semiconductor device manufacturing method, semiconductor device, and semiconductor chip
US7619305B2 (en) Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
JP6408986B2 (en) BVA interposer
TWI529886B (en) Packages, methods of packaging a device and package on package devices
TWI483357B (en) Package structure
US8115319B2 (en) Flip chip package maintaining alignment during soldering
TWI473218B (en) Through-hole medium board, package substrate, and method of forming the same
TWI654730B (en) Package structure and manufacturing method thereof
JP2005019895A (en) Flip chip packaging structure
TWI446508B (en) Coreless package substrate and method of making same
KR101522770B1 (en) Package alignment structure and method of forming same
JP2013021058A (en) Manufacturing method of semiconductor device
TWI394247B (en) Metal post chip connecting device and method free to use soldering material
US20160211242A1 (en) Reduced volume interconnect for three-dimensional chip stack
JP4910408B2 (en) Semiconductor device
JP2018037520A (en) Semiconductor device, electronic device, method for manufacturing semiconductor device, and method for manufacturing electronic device
CN102142421B (en) Metal-column chip connecting structure and method without solders
JP2010098225A (en) Semiconductor device
TWI514490B (en) Semiconductor package and manufacturing method thereof
TWI529881B (en) The structure and method of composite carrier board for chip - scale wafer - level package
TWI424545B (en) Method for manufacturing package substrate
US7759791B2 (en) High density IC module
TWI567887B (en) Substrate structure and method of manufacture thereof
TW201546915A (en) Integrated circuit packaging system with no-reflow connection and method of manufacture thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees