TW202024649A - Circuit and method for measuring signal period - Google Patents

Abstract

A circuit and a method for measuring signal period is disclosed. The circuit for measuring signal period comprises a clock counting module, a waveform generating module, a signal sampling module, and a period recording module. The clock counting module generates a clock count in every period of a first clock signal. The waveform generating module generates M periodical waveforms according to the first clock signal, and the M periodical waveforms relate to M phases of the first clock signal. The signal sampling module, coupled to the waveform generating module, samples an input signal according to the M periodical waveforms, and generates a phase count. The period recording module, coupled to the clock counting module and the signal sampling module, records the current clock count and the corresponding phase count. Wherein M is a natural number larger than 1.

Description

Signal period measurement circuit and method

The present invention relates to a signal period measurement circuit and method, in particular to a circuit and method for dividing the clock into different phases and then separately measuring the signal period.

When the traditional test device wants to measure the periodic input signal, it can only capture the input signal by the positive edge of the system clock, so as to estimate the period of the input signal by marking the time point when the input signal is captured length. However, if the system clock frequency is not high, there is often a problem of insufficient resolution, and the period length of the input signal cannot be accurately estimated. For example, please refer to FIG. 1, which shows a schematic diagram of a traditional input signal and system clock. As shown in Figure 1, after the system clock clk catches the high-level input signal S_in in the first cycle, the system clock clk catches the high-level input signal S_in again in the tenth cycle, and then the input signal can be estimated The length is 9 system clock cycles. If the period of a certain system clock is 5ns, the length of the input signal is 45ns.

However, it can be seen from Figure 1 that the length of the input signal is actually closer to 8 system clock cycles, and the error can reach one system clock. If the period of the input signal is shorter, then obviously the measured period error is relatively larger. Therefore, the industry needs a signal period measurement circuit and method with higher resolution.

The present invention provides a signal period measuring circuit, which can divide the clock into a plurality of periodic waveforms with different phases, and measure the period of an input signal according to the plurality of periodic waveforms, thereby having a higher resolution.

The invention provides a signal period measurement circuit, which includes a clock calculation module, a waveform generation module, a signal sampling module, and a period recording module. The clock calculation module generates a clock count value in each cycle of the first clock. The waveform generating module is used for generating M periodic waveforms from each period of the first clock, and the M periodic waveforms correspond to the M phases of the first clock. The signal sampling module is electrically connected to the waveform generation module for sampling the input signal according to the M periodic waveforms to generate phase sampling values. The period recording module is electrically connected to the clock calculation module and the signal sampling module for recording the current clock count value and the corresponding phase sampling value. Where M is a natural number greater than 1.

In some embodiments, the waveform generation module may sequentially delay the first clock to generate the M periodic waveforms, where the positive edge of the i-th periodic waveform and the positive edge of the i+1th periodic waveform have a time Interval, i is a natural number and i is less than M. In addition, the phase sampling value may correspond to the sampling results of the input signal respectively sampling the M periodic waveforms. In addition, the phase sample value can have M bits, and the M bits correspond to the M phases of the first clock in sequence, and the jth bit of the phase sample value can correspond to the sampling result of the jth periodic waveform sampling input signal. , J is a natural number and j is not greater than M.

In some embodiments, the signal sampling module can further determine whether the phase sampling value changes in different periods of the first clock. When the signal sampling module determines that the phase sampling value has changed, the period recording module records the current clock. The count value and the corresponding phase sampling value. In addition, the period recording module includes a memory, which is used to store the current clock count value and the corresponding phase sampling value. When the signal sampling module determines that the phase sampling value has not changed, the period recording module does not record the current clock count value and the corresponding phase sampling value.

The present invention provides a signal period measurement method, which can divide the clock into a plurality of periodic waveforms with different phases, and measure the period of an input signal according to the plurality of periodic waveforms, so that a higher resolution can be achieved.

The present invention provides a method for measuring signal period, which includes the following steps. The clock count value is generated every cycle of the first clock. Each cycle of the first clock generates M periodic waveforms, and the M periodic waveforms correspond to M phases of the first clock. The input signal is sampled according to the M periodic waveforms to generate phase samples. Record the current clock count value and the corresponding phase sampling value. Where M is a natural number greater than 1.

In summary, the signal cycle measurement circuit and method provided by the present invention can divide the clock into multiple periodic waveforms with different phases, and use each periodic waveform to sample the input signal, so that the number of samples is greater and the sampling interval can be increased. The ground is shortened, so that the period of the input signal can be judged more accurately and with higher resolution.

The features, objectives and functions of the present invention will be further disclosed below. However, the following are only examples of the present invention, and should not be used to limit the scope of the present invention, that is, all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention will still be the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further embodiment of the present invention.

Please refer to FIG. 2. FIG. 2 is a functional block diagram of a signal period measurement circuit according to an embodiment of the present invention. As shown in FIG. 2, this embodiment discloses that the signal period measurement circuit 1 is used to measure the period of the input signal S_in. The signal period measurement circuit 1 includes a clock calculation module 10, a waveform generation module 12, a signal sampling module 14, and Cycle recording module 16. In practice, the signal period measuring circuit 1 can be used to mark the signal start time point and signal end time point of the input signal S_in, and record the signal start time point and signal end time point, and then transfer it to other test devices for conversion Out of the cycle. In other words, the signal period measurement circuit 1 can be assembled in other test devices or connected to other test devices. Of course, this embodiment is not limited to this. For example, the signal period measuring circuit 1 can also convert the period of the input signal S_in by itself. The overall function of the signal period measurement circuit 1 is described below from each module.

The clock calculation module 10 generates a clock count value in each cycle of the first clock CLK. In an example, the first clock CLK can be a system clock, a base frequency clock, or any designated clock, which is not limited in this embodiment. In addition, after the clock calculation module 10 receives the first clock CLK, it can be triggered by the positive edge of the first clock CLK to count the first clock CLK. Those with ordinary knowledge in the technical field should be able to understand that both positive-edge trigger and negative-edge trigger can achieve the same effect. For the convenience of description, the following embodiment uses positive-edge trigger to illustrate. For the convenience of description, please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a schematic diagram of sampling an input signal according to an embodiment of the present invention. As shown in the figure, the clock count value generated by the clock calculation module 10 can be marked as CLK_count, and the initial value can be any natural number N.

In an example, when the clock calculation module 10 counts the first clock CLK, it can be accumulated to the clock count value CLK_count, and the accumulated value can be 1 or other fixed values, which is not limited in this embodiment. In other words, in the example shown in FIG. 3, the clock calculation module 10 can transmit a clock count value CLK_count of N to the period recording module 16 at the beginning (for example, in the first cycle), and the clock count module 16 is at the first clock CLK In the next cycle (for example, the second cycle), the clock count value CLK_count of N+1 can be sent to the cycle recording module 16, and so on.

The waveform generating module 12 is used for generating M periodic waveforms from each period of the first clock CLK, and the M periodic waveforms correspond to the M phases of the first clock. In the example shown in FIG. 3, the waveform generating module 12 can generate 4 periodic waveforms CLK_1, CLK_2, CLK_3, and CLK_4 according to the first clock CLK, and the phase of each periodic waveform is different by 90 degrees. In one example, the waveform generation module 12 may include a phase-locked loop (PLL), which uses the phase-locked loop to delay the first clock CLK to generate multiple periodic waveforms with different phases. Although this embodiment takes the waveform generation module 12 to generate 4 periodic waveforms as an example, it is not limited to this. For example, the waveform generation module 12 can also generate 8 or 16 periodic waveforms.

The signal sampling module 14 is electrically connected to the waveform generating module 12 for sampling the input signal S_in according to the M periodic waveforms to generate phase sampling values. In one example, the signal sampling module 14 can use the positive edge of the periodic waveform to sample the input signal S_in. Taking the example shown in FIG. 3 for example, in the first cycle of the first clock CLK (the clock count value CLK_count is between N and N+1), the signal sampling module 14 can determine that the periodic waveform CLK_1 is not sampled To the input signal S_in, because at the positive edge of the periodic waveform CLK_1, the input signal S_in is still at a low level. The signal sampling module 14 can determine that the periodic waveforms CLK_2, CLK_3, and CLK_4 have sampled the input signal S_in, because the input signal S_in is at a high level when the periodic waveforms CLK_2, CLK_3, CLK_4 are positive edges. Accordingly, the signal sampling module 14 can record the phase sampling value phase_count as 0111, indicating that the input signal S_in starts from the second phase. Here, this embodiment demonstrates that the number of bits in the phase sampling value phase_count can correspond to the number of periodic waveforms, and the order of the bits can be used to understand which phase (which periodic waveform) the signal start time point of the input signal S_in corresponds to. ).

Similarly, in the 10th cycle of the first clock CLK (clock count value CLK_count is between N+9 and N+10), the signal sampling module 14 can determine that the periodic waveforms CLK_1, CLK_2, and CLK_3 are not sampled. The input signal S_in is because when the periodic waveforms CLK_1, CLK_2, CLK_3 have positive edges, the input signal S_in is still at a low level. The signal sampling module 14 can determine that the periodic waveform CLK_4 has sampled the input signal S_in, because when the periodic waveform CLK_4 has a positive edge, the input signal S_in is at a high level. Accordingly, the signal sampling module 14 can record the phase sampling value phase_count as 0001, which indicates that the input signal S_in of the next cycle starts from the fourth phase. Since the input signal S_in is a continuous signal, by measuring the signal start time point of the input signal S_in of the next cycle, it is equal to the signal end time point of the input signal S_in of the previous cycle. In one example, the signal sampling module 14 may generate the phase sampling value phase_count after all the input signals S_in have been sampled in the 4 cycle waveforms CLK_1, CLK_2, CLK_3, and CLK_4, and output it in the next cycle of the first clock CLK给 cycle record module 16.

In one example, the signal sampling module 14 can determine which phase sampling value has a physical meaning. For example, if the previous phase sampling value phase_count is recorded as 0000, the current phase sampling value phase_count is still recorded as 0000, which means that the input signal S_in is always at a low level, so that the signal sampling module 14 records such phase sampling value pair measurement Cycle does not help. Similarly, if the previous phase sampling value phase_count is recorded as 1111, the current phase sampling value phase_count is also recorded as 1111, indicating that the input signal S_in is at a high level, so the signal sampling module 14 records such phase sampling value versus the measurement period It didn't help either. However, if the previous phase sampling value phase_count is recorded as 0000, the current phase sampling value phase_count is also recorded as 0111, and the signal sampling module 14 finds a change in the phase sampling value phase_count, the signal sampling module 14 can determine the current phase sampling The value phase_count is meaningful, and the phase sampling value phase_count can be output to the period recording module 16. Conversely, if the signal sampling module 14 determines that the current phase sampling value phase_count is meaningless, it may not output the phase sampling value phase_count to the period recording module 16.

The period recording module 16 is electrically connected to the clock calculation module 10 and the signal sampling module 14 for recording the current clock count value CLK_count and the corresponding phase sampling value phase_count. Take the example shown in FIG. 3, although the positive edge of the input signal S_in is in the first cycle of the first clock CLK, those skilled in the art can understand that the circuit elements cannot be in the same During the cycle, it is necessary to sample and immediately send the sampling results in batches. Therefore, in fact, the cycle recording module 16 still has to wait until the next cycle (the second cycle) of the first clock CLK to receive the signal from the sampling module. 14 information. Accordingly, the period recording module 16 records the signal start time point of the input signal S_in, the corresponding clock count value CLK_count is N+1, and the phase sampling value phase_count is 0111.

In the same way, although the next positive edge of the input signal S_in is in the 10th cycle of the first clock CLK, in fact the cycle recording module 16 still has to wait until the next cycle (the 11th cycle) of the first clock CLK It is possible to receive data from the signal sampling module 14. Accordingly, the period recording module 16 will record the signal end time point of the input signal S_in, the corresponding clock count value CLK_count is N+10, and the phase sampling value phase_count is 0001. In other words, one period of the input signal S_in differs from the clock count value CLK_count by 9 periods, and the phase sampling value phase_count differs by 2 phases. Assume that when 1 cycle of the first clock CLK corresponds to 4 ns, each of the 4 phases is exactly 1 ns apart. Take the example shown in Figure 3, the 9 cycles of the first clock CLK can be converted into 36ns, and the 2 phases of the first clock CLK can be converted into 2ns, so the clock count value CLK_count and the phase Sampling value phase_count quickly calculates that the period of the input signal S_in is 38ns.

Here, those skilled in the art can find that when the period recording module 16 obtains the phase sampling value phase_count does not affect the estimated period of the input signal S_in. For example, even if the cycle recording module 16 waits until the next 5 cycles of the first clock CLK to receive the data from the signal sampling module 14, the signal start time point of the input signal S_in is changed to the corresponding clock The count value CLK_count is N+5 and the phase sampling value phase_count is 0111. Similarly, the signal end time point of the input signal S_in is changed to the corresponding clock count value CLK_count as N+14 and the phase sampling value phase_count as 0001. Since the delay error will be subtracted, it can still be calculated that one cycle of the input signal S_in differs from the clock count value CLK_count by 9 cycles, and the phase sampling value phase_count differs by 2 phases. Based on this, it can also be calculated that the period of the input signal S_in is 38 ns, which does not affect the result of the period measurement of the input signal S_in.

It is worth mentioning that although the aforementioned signal sampling module 14 samples the positive edge of the input signal S_in twice to obtain the start and end time points of a complete cycle of the input signal S_in. However, this embodiment is not limited to this. For example, the signal sampling module 14 may also sample the positive edge and the following negative edge of the input signal S_in to obtain the start and end time points of one and a half cycles of the input signal S_in. In this way, the time length of the complete cycle can still be calculated from the half cycle.

In the foregoing example, in addition to recording the clock count value CLK_count and the phase sampling value phase_count, the period recording module 16 can also further convert the period of the input signal S_in. Of course, in another example, the period recording module 16 may only be used to mark the signal start time point and the signal end time point of the input signal S_in, and store the clock count value CLK_count and the phase sampling value phase_count in a memory , And then transfer to other test devices to calculate the cycle. For example, the signal period measurement circuit 1 may be a field programmable gate array (FPGA), and the memory of the period recording module 16 may be a block random access memory in the FPGA ( block RAM).

In order to explain the signal period measurement method in this case, please refer to FIG. 2, FIG. 3 and FIG. 4 together. FIG. 4 is a flowchart of the steps of the signal period measurement method according to an embodiment of the present invention. As shown in the figure, in step S20, the clock calculation module 10 generates a clock count value CLK_count in each cycle of the first clock CLK. In step S22, the waveform generating module 12 is used to generate M periodic waveforms from each cycle of the first clock CLK, and the M periodic waveforms correspond to the M phases of the first clock. In step S24, the signal sampling module 14 is electrically connected to the waveform generating module 12 for sampling the input signal S_in according to the M periodic waveforms to generate a phase sampling value phase_count. In step S26, the period recording module 16 is electrically connected to the clock calculation module 10 and the signal sampling module 14 for recording the current clock count value CLK_count and the corresponding phase sampling value phase_count. Since the signal period measurement method of this embodiment has been fully explained and supported in the foregoing embodiments, it will not be repeated here.

In summary, the signal cycle measurement circuit and method provided by the present invention can divide the clock into multiple periodic waveforms with different phases, and use each periodic waveform to sample the input signal, so that the number of samples is greater and the sampling interval can be increased. The ground is shortened, so that the period of the input signal can be judged more accurately and with higher resolution.

1: Signal cycle measurement circuit 10: Clock calculation module 12: Waveform generation module 14: Signal sampling module 16: Period recording module S20~S26: Step flow clk: System clock CLK: First clock CLK_1~ CLK_4: Periodic waveform S_in: Input signal CLK_count: Clock count value Phase_count: Phase sampling value

FIG. 1 is a schematic diagram of sampling input signals in the prior art.

FIG. 2 is a functional block diagram of a signal period measurement circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of sampling an input signal according to an embodiment of the invention.

FIG. 4 is a flowchart of the steps of a signal period measurement method according to an embodiment of the present invention.

1: Signal period measurement circuit

10: Clock calculation module

12: Waveform generation module

14: Signal sampling module

16: Periodic recording module

CLK: the first clock

S_in: input signal

Claims (15)

A signal period measurement circuit, comprising: a clock calculation module for generating a clock count value in each period of a first clock; a waveform generating module for generating a clock count value from each period of the first clock Generate M periodic waveforms, the M periodic waveforms corresponding to the M phases of the first clock; a signal sampling module, electrically connected to the waveform generation module, to sample an input signal according to the M periodic waveforms, To generate a phase sampling value; and a periodic recording module, electrically connected to the clock calculation module and the signal sampling module, for recording the current clock count value and the corresponding phase sampling value; where M Is a natural number greater than 1. The signal period measurement circuit according to claim 1, wherein the waveform generation module sequentially delays the first clock to generate the M period waveform, wherein the positive edge of the i-th period waveform and the i+1-th period The positive edge of the waveform has a time interval, i is a natural number and i is less than M. The signal period measurement circuit according to claim 1, wherein the phase sampling value corresponds to the sampling result of the input signal respectively sampling the M period waveforms. The signal period measurement circuit of claim 3, wherein the phase sample value has M bits, and the M bits correspond to the M phases of the first clock in sequence. The signal period measurement circuit according to claim 4, wherein the jth bit of the phase sample value corresponds to the sampling result of the jth periodic waveform sampling of the input signal, j is a natural number and j is not greater than M. The signal period measurement circuit according to claim 1, wherein the signal sampling module further determines whether the phase sampling value has changed in different periods of the first clock, and when the signal sampling module determines that the phase sampling value has changed At the time, the period recording module records the current clock count value and the corresponding phase sampling value. The signal period measurement circuit according to claim 6, wherein the period recording module includes a memory, and the memory is used to store the current clock count value and the corresponding phase sample value. The signal period measurement circuit of claim 6, wherein when the signal sampling module determines that the phase sample value has not changed, the period recording module does not record the current clock count value and the corresponding phase sample value. A method for measuring signal period includes: generating a clock count value for each period of a first clock; generating M period waveforms for each period of the first clock, the M period waveforms corresponding to the first clock M phases of a clock; sampling an input signal according to the M periodic waveforms to generate a phase sampling value; and recording the current clock count value and the corresponding phase sampling value; where M is a natural value greater than 1. number. The signal period measurement method according to claim 9, wherein the step of generating M period waveforms from each period of the first clock further comprises: sequentially delaying the first clock to generate the M periods Waveform; There is a time interval between the positive edge of the i-th periodic waveform and the positive edge of the i+1th periodic waveform, i is a natural number and i is less than M. The signal period measurement method according to claim 9, wherein the phase sampling value corresponds to the sampling result of the input signal respectively sampling the M period waveforms. The signal period measurement method of claim 11, wherein the phase sampling value has M bits, and the M bits correspond to the M phases of the first clock in sequence. The signal period measurement method of claim 12, wherein the j-th bit of the phase sample value corresponds to the sampling result of the j-th periodic waveform sample of the input signal, j is a natural number and j is not greater than M. The signal period measurement method of claim 9, wherein in the step of sampling the input signal according to the M period waveforms to generate the phase sample value, the method further includes: determining that the phase sample value is at the first clock Whether there is a change in different periods; when it is judged that the phase sample value has changed, the current clock count value and the corresponding phase sample value are recorded. The signal period measurement method according to claim 14, wherein when it is determined that the phase sample value has not changed, the current clock count value and the corresponding phase sample value are not recorded.

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