TW201721623A - Driving circuit of active-matrix organic light-emitting diode with hybrid transistors - Google Patents

Abstract

The invention provides a driving circuit of active-matrix organic light-emitting diode with hybrid transistors, which comprises a driving current unit and a reset compensation and light emitting control circuit. The driving current unit has a first transistor and a second transistor, wherein the first transistor and the second transistor are low temperature poly-silicon (LTPS) transistors. The reset compensation and light emitting control circuit has a third transistor connected to a control terminal of the first transistor, wherein the third transistor is an oxide semiconductor transistor.

Description

Driving circuit of active matrix organic light emitting diode with hybrid transistor

The present invention relates to the technical field of liquid crystal display devices, and more particularly to a driving circuit of an active matrix organic light emitting diode having a hybrid transistor.

The driving matrix of the active matrix organic light emitting diode (AMOLED) pixel can be classified into a P-type and an N-type driving type according to the backplane process technology. 1 is a pixel circuit of a conventional P-type driving transistor of 2T1C (two transistors), which is matched with a normal OLED element. Most of the P-type driver transistors use low temperature poly-silicon (LTPS) backplane technology.

The voltage corresponding to the gate voltage (Vgs) of the P-type driving transistor PTFT_dri is the voltage of the data potential and the high potential ELVDD, wherein the high potential ELVDD is a fixed relatively high potential. For the conventional P-type driving transistor PTFT_dri, there is a phenomenon that the threshold voltage deviation of the driving transistor is caused. That is, the threshold voltage (Vt) of the P-type driving transistor of the LTPS is likely to cause regional Vt variation due to the polycrystalline crystallization process. That is, for the P-type driving transistor of the same size, when the same driving voltage is input, the same current cannot be output, resulting in uneven brightness (mura) or poor uniformity. Therefore need to drive P-type The threshold voltage (Vt) of the electromagnet is voltage compensated.

Since voltage compensation is used, multiple transistors are used, resulting in an increase in current consumption. In high-resolution applications (for example, FHD_1080RGB*1920, QHD_1440RGB*2560), the current consumption may be too large due to too many driving circuits, which may affect the usage time of the handheld device. Therefore, there is still room for improvement in the conventional pixel driving circuit. .

The object of the present invention is mainly to provide a driving circuit of an active matrix organic light emitting diode having a hybrid transistor, wherein a transistor on a driving current unit uses a low temperature polycrystalline germanium transistor. The low-temperature polycrystalline germanium transistor can provide a large current when turned on, and has a large driving capability to drive an organic light-emitting diode. At the same time, in a reset compensation and illumination control circuit, part of the transistor is changed to an oxide semiconductor transistor to provide a lower leakage current, thereby eliminating the voltage variation of the control terminal of the driving transistor on the driving current unit, thereby enabling The driving transistor can provide a stable driving current to an organic light emitting diode, and can improve the problem of uneven brightness or uniformity of the prior art. At the same time, the present invention proposes a partial transistor sharing architecture of two driving circuits, which can greatly reduce the number of transistors.

To achieve the foregoing objects, the present invention provides a driving circuit for an active matrix organic light emitting diode having a hybrid transistor, comprising a driving current unit, and a reset compensation and illumination control circuit. The driving current unit includes a first transistor and a second transistor, wherein the first transistor and the second transistor are low temperature polysilicon transistors. The reset compensation and illumination control circuit is coupled to the drive current unit, the reset compensation and illumination control circuit includes a third transistor, and the third transistor is coupled to a control of the first transistor And wherein the third transistor is an oxide semiconductor transistor.

PTFT_dri‧‧‧ drive transistor

200‧‧‧Drive circuit of active matrix organic light-emitting diode with hybrid transistor

210‧‧‧Drive current unit

220‧‧‧Reset compensation and illumination control circuit

(T1)‧‧‧First transistor

(T2)‧‧‧Second transistor

(T3)‧‧‧ Third transistor

(g) ‧ ‧ control terminal

(Cst)‧‧‧First Capacitor

(T4)‧‧‧ Fourth transistor

(T5)‧‧‧ Fifth transistor

(T6)‧‧‧ sixth transistor

(PLVDD) ‧ ‧ high potential

(a) ‧ ‧ first end

(b) ‧‧‧ second end

(RST)‧‧‧Reset signal

(REF)‧‧‧reference signal

(SN)‧‧‧First Control Signal

(D1)‧‧‧Organic Luminescent Diodes

(EM1)‧‧‧Second control signal

(Data) ‧ ‧ data line

(PLVDD) ‧ ‧ high potential

(PLVSS) ‧‧‧low potential

(VSS) ‧ ‧ control low potential

(VDD)‧‧‧Control high potential

(EM)‧‧‧First control signal

(SN)‧‧‧second control signal

(REFN)‧‧‧First reference signal

(SN2)‧‧‧ Third Control Signal

(REFS)‧‧‧second reference signal

(RST)‧‧‧Reset signal

(Cst)‧‧‧ Capacitance

(EM)‧‧‧First control signal

(SCAN1)‧‧‧Second control signal

(RST)‧‧‧Reset signal

(Dis) ‧ ‧ third control signal

(REF)‧‧‧First reference signal

(SCAN2) ‧‧‧fourth control signal

(Cst)‧‧‧First Capacitor

(C2)‧‧‧second capacitor

(T7)‧‧‧ seventh transistor

(G4)‧‧‧First control signal

(G1)‧‧‧second control signal

(G3)‧‧‧ Third control signal

(G2) ‧ ‧ fourth control signal

(G5)‧‧‧ Fifth control signal

(C1)‧‧‧second capacitor

(P1) ‧ ‧ reset cycle

(P2) ‧ ‧ compensation cycle

(P21) ‧ ‧ first time

(P22) ‧ ‧ second period

(P3) ‧‧ ‧Lighting cycle

(P31) ‧ ‧ first time

(P32) ‧ ‧ second period

FIG. 1 is a schematic diagram of a pixel circuit of a conventional 2T1C P-type driving transistor.

2 is a block diagram of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor according to the present invention.

3 is a circuit diagram of an embodiment of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor according to the present invention.

Figure 4 is a schematic illustration of the operation of Figure 3 of the present invention.

Fig. 5 is a circuit diagram showing another embodiment of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor according to the present invention.

Figure 6 is a schematic illustration of the operation of Figure 5 of the present invention.

Fig. 7 is a circuit diagram showing still another embodiment of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor according to the present invention.

Figure 8 is a schematic illustration of the operation of Figure 7 of the present invention.

Fig. 9 is a schematic view showing currents of a low temperature polycrystalline germanium transistor, an oxide semiconductor transistor, and an amorphous germanium transistor when turned on and off.

Figure 10 is a schematic illustration of the simulation results of the circuits of Figures 3, 5, and 7 of the present invention.

Figure 11 is a circuit diagram of still another embodiment of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor of the present invention.

Figure 12 is a schematic view of the operation of Figure 11 of the present invention.

Figure 13 is a circuit diagram showing two embodiments of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor in Figure 5 of the present invention.

Figure 14 is a cross-sectional view showing a portion of the transistor of Figure 13 of the present invention.

Figure 15 is a circuit diagram showing two embodiments of a driving circuit of an active matrix organic light emitting diode having a hybrid transistor in Figure 7 of the present invention.

16 to 20 are schematic views showing the application of the driving circuit of the active matrix organic light emitting diode having the hybrid transistor in Fig. 5 of the present invention.

2 is a block diagram of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor, as shown in FIG. 2, the driving circuit 200 includes a driving current unit 210, and a reset compensation and The illumination control circuit 220 is configured to drive an organic light emitting diode (D1). The driving current unit 210 includes at least a first transistor (T1) and a second transistor (T2), wherein the first transistor (T1) and the second transistor (T2) are low temperature polysilicon (Low Temperature) Poly-silicon, LTPS) transistors. The reset compensation and illumination control circuit 220 is coupled to the drive current unit 210, and the reset compensation and illumination control circuit 220 includes at least a third transistor (T3). The third transistor (T3) is connected to a control terminal (g) of the first transistor (T1), wherein the third transistor (T3) is an oxide semiconductor transistor. The oxide semiconductor transistor may be an Indium Gallium Zinc Oxide (IGZO) transistor.

3 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor according to an embodiment of the invention, wherein the reset compensation and illumination control circuit 220 includes a first capacitor (Cst), The third transistor (T3), a fourth battery Crystal (T4) and a fifth transistor (T5). The driving current unit 210 includes the first transistor (T1), the second transistor (T2), and a sixth transistor (T6). The first capacitor (Cst) is connected to a high potential (PLVDD) at one end, and the other end is connected to the control terminal (g) of the first transistor (T1) and a first portion of the third transistor (T3). a first end (a) of the terminal (a) and the fourth transistor (T4).

A control terminal (g) of the fourth transistor (T4) is coupled to a reset signal (RST), and a second terminal (b) of the fourth transistor (T4) is coupled to a reference signal (REF). In the present invention, the first end (a) and the second end (b) may be a drain and a source of the transistor or a source and a drain of the transistor. . If the transistor is used as a MOS switch, the first end (a) and the second end (b) can be interchanged.

a second end (b) of the third transistor (T3) is connected to a second end (b) of the first transistor (T1) and a first end (a) of the second transistor (T2) A control terminal (G) of the third transistor (T3) is connected to a first control signal (SN). A second end (b) of the second transistor (T2) is connected to one end of an organic light emitting diode (D1), and a control end (g) of the second transistor (T2) is connected to a second Control signal (EM1). A first end (a) of the fifth transistor (T5) is connected to a data line (Data), and a second end (b) of the fifth transistor (T5) is connected to the first transistor (T1) a first end (a) and a second end (b) of the sixth transistor (T6). A first end (a) of the sixth transistor (T6) is connected to the high potential (PLVDD), and a control terminal (g) of the sixth transistor (T6) is connected to the second control signal (EM1) . The other end of the organic light emitting diode (D1) is connected to a low potential (PLVSS). The fourth transistor (T4) is an oxide semiconductor transistor, and the second transistor (T2) and the sixth transistor (T6) are a low temperature polysilicon (LTPS) transistor, and the fifth transistor (T5) may be an oxide semiconductor transistor or a low temperature polysilicon (LTPS) transistor.

Figure 4 is a schematic illustration of the operation of Figure 3 of the present invention. In Figure 4, it shows the drive The timing of the dynamic circuit 200, the on/off state of each transistor, and the voltage of the node of the first transistor (T1).

During a reset period, the reset signal (RST) is a control low potential (VSS), the second control signal (SN) is a control high potential (VDD), and the first control signal (EM1) is a control high. Potential (VDD). The voltage level of the control high potential (VDD) may be the same as the voltage level of the high potential PLVDD, or may be different from the voltage level of the high potential PLVDD. The voltage level of the control low potential (VSS) may be the same as the voltage level of the low potential PLVSS, or may be different from the voltage level of the low potential PLVSS.

During the reset period, the second transistor (T2), the third transistor (T3), the fifth transistor (T5), and the sixth transistor (T6) are turned off, the first transistor (T1) and the fourth transistor (T4) are turned on, so the control terminal (g) of the first transistor (T1) is reset, and the voltage on the reference transistor (REF). Since the sixth transistor (T6) is turned off, the first end (a) of the first transistor (T1) is floating.

During a compensation period, the reset signal (RST) is the control high potential (VDD), the second control signal (SN) is the control low potential (VSS), and the first control signal (EM1) is the control high potential (VDD). . The second transistor (T2), the fourth transistor (T4), and the sixth transistor (T6) are turned off, the first transistor (T1), the third transistor (T3), and the first Five transistors (T5) are conductive. The signal on the data line is transmitted to the control terminal (g) of the first transistor (T1) via the fifth transistor (T5), the first transistor (T1), and the third transistor (T3). Therefore, the voltage of the control terminal (g) of the first transistor (T1) is Vdata+|Vtp|, and the voltage of the first terminal (a) of the first transistor (T1) is Vdata, wherein Vdata is a data line. The voltage of the signal, Vtp, is the threshold voltage (Vtp) of the first transistor (T1).

In a lighting cycle, the reset signal (RST) is a control high potential (VDD), the second control signal (SN) is a control high potential (VDD), and the first control signal (EM1) is a low control. Potential (VSS). The third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5) are turned off, the first transistor (T1), the second transistor (T2), and the sixth The transistor (T6) is turned on. The current of the high potential PLVDD flows through the organic light emitting diode (D1) via the sixth transistor (T6), the first transistor (T1), and the second transistor (T2). Since the third transistor (T3) and the fourth transistor (T4) are turned off, the voltage of the control terminal (g) of the first transistor (T1) is Vdata+|Vtp|. Since the sixth transistor (T6) is turned on, the voltage of the first terminal (a) of the first transistor (T1) is PLVDD.

FIG. 5 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor according to another embodiment of the present invention. The reset compensation and illumination control circuit 220 includes a first capacitor (Cst), the third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a sixth Transistor (T6). The driving current unit 210 includes the first transistor (T1) and the second transistor (T2). A first end (a) of the first transistor (T1) is connected to the high potential (PLVDD), and a second end (b) is connected to a first end of the second transistor (T2) (a And a first end (a) of the third transistor (T3).

A second end (b) of the second transistor (T2) is connected to an organic light emitting diode (D1) and a second end (b) of the fourth transistor (T4), and a control terminal thereof g) connected to a first control signal (EM). The other end of the organic light emitting diode (D1) is connected to a low potential (PLVSS). a second end (b) of the third transistor (T3) is connected to a control terminal (g) of the first transistor (T1) and one end of the first capacitor (Cst), and a control terminal thereof (g) ) is connected to a second control signal (SN). The other end of the first capacitor (Cst) is connected to a second end (b) of the fifth transistor (T5) and a first end (a) of the sixth transistor (T6). A first end (a) of the fifth transistor (T5) is connected to a data line (Data), and a control terminal (g) is connected to the second control signal (SN). A second end (b) of the sixth transistor (T6) is coupled to a first reference signal (REFN), and a control terminal (g) is coupled to a third control signal (SN2). The fourth transistor A first end (a) of (T4) is connected to a second reference signal (REFS), a control terminal (g) is connected to a reset signal (RST), and the second transistor (T2) is a low temperature. Polycrystalline germanium (LTPS) transistors. The fourth transistor (T4), the fifth transistor, and the sixth transistor (T6) may be a low temperature polysilicon (LTPS) transistor or an oxide semiconductor transistor.

Figure 6 is a schematic illustration of the operation of Figure 5 of the present invention. In FIG. 6, the timing of the driving circuit 200, the on/off state of each transistor, and the voltage of the node of the first transistor (T1) are shown. The operation process of the reset period, the compensation period, and the illuminating period can be known from the description of the present invention and the related disclosure of FIG. 4, and therefore will not be described again. In FIG. 6, Vrefn represents the voltage of the first reference signal (REFN), Vrefs represents the voltage of the second reference signal (REFS), and Vdata represents the voltage of the data line (Data).

7 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor according to still another embodiment of the present invention. The reset compensation and illumination control circuit 220 includes a first capacitor (Cst), the third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a sixth Transistor (T6). The driving current unit 210 includes the first transistor (T1) and the second transistor (T2). A first end (a) of the first transistor (T1) is connected to a high potential (PLVDD), and a second end (b) is connected to a first end of the second transistor (T2) (a And a first end (a) of the third transistor (T3).

A second end (b) of the second transistor (T2) is coupled to an organic light emitting diode (D1), and a control terminal (g) is coupled to a first control signal (EM). a second end (b) of the third transistor (T3) is connected to a control terminal (g) of the first transistor (T1), one end of the first capacitor (Cst), and the fourth transistor ( A second end (b) of T4), a control terminal (g) is connected to a second control signal (SCAN1). A first end (a) of the fourth transistor (T4) is coupled to a reset signal (RST), and a control terminal (g) is coupled to a third control signal (Dis). The other end of the first capacitor (Cst) is connected to a second end (b) of the fifth transistor (T5) and the A first end (a) of the sixth transistor (T6). A first end (a) of the fifth transistor is connected to a first data line (Data), and a control terminal (g) is connected to the second control signal (SCAN1). A second end (b) of the sixth transistor (T6) is coupled to a first reference signal (VREF), and a control terminal (g) is coupled to a fourth control signal (SCAN2), the fourth transistor (T4) is an oxide semiconductor transistor, and the second transistor (T2) is a low temperature polysilicon (LTPS) transistor. The fifth transistor and the sixth transistor (T6) may be a low temperature polysilicon (LTPS) transistor or an oxide semiconductor transistor.

Figure 8 is a schematic illustration of the operation of Figure 7 of the present invention. In FIG. 8, the timing of the driving circuit 200, the on/off state of each transistor, and the voltage of the node of the first transistor (T1) are shown. The operation process of the reset period, the compensation period, and the illuminating period is known to those skilled in the art and can be known from the description of the present invention and the related disclosure of FIG. 4, and therefore will not be described again. In FIG. 8, Vrst represents the voltage of the reset signal (RST), Vref represents the voltage of the first reference signal (REF), and Vdata represents the voltage of the data line (Data).

Fig. 9 is a schematic view showing currents of a low temperature polycrystalline germanium (LTPS) transistor, an oxide semiconductor transistor, and an amorphous germanium (a-Si) transistor when turned on and off. As shown in Figure 9, the low temperature polysilicon (LTPS) transistor has a large current when it is turned on. When the oxide semiconductor transistor is turned off, its leakage current is much smaller than that of the low temperature polysilicon (LTPS) transistor and amorphous germanium (a- Si) leakage current of the transistor.

Figure 10 is a schematic illustration of the simulation results of the circuits of Figures 3, 5, and 7 of the present invention. It shows the effect of the transistor leakage current (Ioff) on the operation of the circuit when the transistor is turned off. The analog parameters are: PLVDD (PVDD) of 7 volts, PLVSS (PVSS) of -1 volt, capacitance Cst of 0.1 pF, and Vdata of 4 volts. In FIG. 10, in the row of the connection gate, O indicates that the transistor has a control terminal (g) connected to the first transistor (T1), and X indicates that the transistor is not connected to The control terminal (g) of the first transistor (T1). example For example, corresponding to the behavior OXO of the fourth transistor (T4), the fourth transistor (T4) is connected to the control terminal (g) of the first transistor (T1), respectively, in FIG. The fourth transistor (T4) is not connected to the control terminal (g) of the first transistor (T1), and the fourth transistor (T4) is connected to the first transistor (T1) in FIG. Control terminal (g). In FIG. 10, ΔI/frame indicates the current difference flowing through the organic light-emitting diode during the display of each frame, and the difference mainly comes from the influence of the transistor leakage of the operating circuit. For example, the transistor corresponding to the fourth transistor (T4) causes the difference between the current of the organic light emitting diode and the original prediction to be +0.2u, -0.0028u, and +0.084u, respectively, which represents the fourth transistor in FIG. 3, respectively. (T4) affects the organic light-emitting diode current +0.2u ampere (A), the fourth transistor (T4) affects -0.0028u ampere (A) in Figure 5, and the fourth transistor (T4) in Figure 7 +0.084u amps (A).

As shown in FIG. 10, if a transistor is connected to the control terminal (g) of the first transistor (T1), it requires a lower leakage current to eliminate the control terminal of the first transistor (T1) ( The voltage fluctuation of g) further eliminates the current fluctuation of the organic light-emitting diode (D1). Therefore, in the present invention, the transistor on the driving current unit 210 uses a low temperature polysilicon (LTPS) transistor, which provides a large current when turned on, and drives the organic light emitting diode (D1). If the transistor in the reset compensation and illumination control circuit 220 is connected to the control terminal (g) of the first transistor (T1), an oxide semiconductor transistor is used to provide a lower leakage current, and the transistor is eliminated. The voltage fluctuation of the control terminal (g) of the first transistor (T1) and the current fluctuation of the organic light-emitting diode (D1) are based on the problem that the brightness of the technology is not uniform (mura) or the uniformity is poor.

11 is a circuit diagram of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor according to still another embodiment of the present invention. The reset compensation and illumination control circuit 220 includes a first capacitor (Cst), a second capacitor (C2), the third transistor (T3), a fourth transistor (T4), and a fifth transistor. (T5) and a sixth transistor (T6), the driving current unit 210 includes the first transistor (T1), the second transistor (T2), and a seventh transistor (T7). A first end (a) of the first transistor (T1) is coupled to a second end (b) of the fourth transistor (T4) and a second end of the seventh transistor (T7) (b) a second end (b) is connected to a first end (a) of the second transistor (T2) and a first end (a) of the third transistor (T3).

A second end (b) of the second transistor (T2) is connected to an organic light emitting diode (D1) and a first end (a) of the sixth transistor (T6), and a control end thereof g) connected to a first control signal (G4). a second end (b) of the third transistor (T3) is connected to a control terminal (g) of the first transistor (T1), one end of the first capacitor (Cst), and the second capacitor (C2) One end of the fifth transistor (T5) and a first end (a) of the fifth transistor (T5) are connected to a second control signal (G1) and the other end of the second capacitor (C2). The other end of the first capacitor (Cst) is connected to a low potential.

A first end (a) of the fourth transistor (T4) is connected to a data line (Data), and a control terminal (g) is connected to the second control signal (G1). a second end (b) of the fifth transistor is connected to a third control signal (G3) and a second end (b) of the sixth transistor (T6), and a control terminal (g) is connected to A fourth control signal (G2). A control terminal (g) of the sixth transistor (T6) is connected to a fifth control signal (G5). A first end (a) of the seventh transistor (T7) is connected to the high potential (VDD), and a control terminal (g) is connected to the first control signal (G4). The fifth transistor is an oxide semiconductor transistor, the seventh transistor (T7) is a low temperature polysilicon (LTPS) transistor, and the fourth transistor (T4) and the sixth transistor (T6) may be oxidized. Semiconductor transistor or low temperature polysilicon (LTPS) transistor.

Figure 12 is a schematic illustration of the operation of Figure 11 of the present invention. In FIG. 12, the timing of the driving circuit 200, the on/off state of each transistor, and the voltage of the node of the first transistor (T1) are shown. Its reset cycle, compensation cycle, and operation process of the illumination cycle, Those skilled in the art can disclose the disclosure of the present invention and the related disclosure of FIG. 4, and therefore will not be described again. In FIG. 12, Vini represents the voltage of the signal written by the third control signal (G3) during the reset period, and Vdata represents the voltage of the data line (Data).

Figure 13 is a circuit diagram showing two embodiments of a driving circuit 200 of an active matrix organic light emitting diode having a hybrid transistor in Figure 5 of the present invention. The second control signal (SN) is shorted to the third control signal (SN2). In the lower left circuit, the fifth transistor (T5) is a P-type low temperature polysilicon (LTPS) transistor and the sixth transistor (T6) is an N-type oxide semiconductor transistor. In the lower right circuit, the fifth transistor (T5) is an N-type oxide semiconductor transistor and the sixth transistor (T6) is a P-type low temperature polysilicon (LTPS) transistor.

Figure 14 is a cross-sectional view showing a portion of the transistor of Figure 13 of the present invention. As shown in FIG. 14, the upper half is a schematic view of a low temperature polycrystalline germanium (LTPS) transistor and an oxide semiconductor transistor, and the lower half of FIG. 14 is the fifth transistor (T5) and the first in the lower right circuit of FIG. A schematic cross-section of a six-electrode (T6). As shown in FIG. 14, the fifth transistor (T5) and the sixth transistor (T6) in the lower right circuit of FIG. 13 can be stacked to form a three-dimensional (3-dimension, 3D) transistor. Can save layout area. The various symbols in FIG. 14 are familiar to those skilled in the art in the context of the disclosure of the present invention and will not be described again.

Figure 15 is a circuit diagram showing two embodiments of the driving circuit 200 of the active matrix organic light emitting diode having the hybrid transistor of Figure 7 of the present invention. The second control signal (SCAN1) is shorted to the fourth control signal (SCAN2). In the lower left circuit, the fifth transistor (T5) is a P-type low temperature polysilicon (LTPS) transistor and the sixth transistor (T6) is an N-type oxide semiconductor transistor. In the lower right circuit, the fifth transistor (T5) is an N-type oxide semiconductor transistor and the sixth transistor (T6) is a P-type low-temperature polysilicon. (LTPS) transistor.

16 to 20 are schematic views showing the application of the driving circuit 200 of the active matrix organic light emitting diode having the hybrid transistor of Fig. 5 of the present invention. As shown in FIG. 16, it further includes a second capacitor (C1), one end of the second capacitor (C1) is connected to the first end (a) of the first transistor (T1), and the other end is connected to The control terminal (g) of the first transistor (T1) is shared with another driver circuit. As shown in FIG. 16, at a reset period (Period 1, P1), the drive circuit performs a reset operation, and the other drive circuit performs a light-emitting operation. That is, the other driving circuit is a lighting period (P3) in timing.

As shown in FIG. 17, in a first period (P21) of a compensation period (P2), the driving circuit performs a compensation operation, and the other driving circuit performs a reset operation, that is, the other driving circuit is in timing Reset cycle (P1). As shown in FIG. 18, in a second period (P22) of the compensation period (P2), the driving circuit performs a compensation operation, and the other driving circuit performs a compensation operation, that is, the other driving circuit compensates in timing. A first period of time (P2) of the period (P2).

As shown in FIG. 19, in a first period (P31) of an illumination period (P3), the driving circuit performs a lighting operation, and the other driving circuit performs a compensation operation, that is, the other driving circuit compensates in timing. A second period of time (P2) of the period (P2). During a second period (P32) of the lighting period (P3), the driving circuit performs a lighting operation, and the other driving circuit performs a lighting operation, that is, the other driving circuit is a timing of the lighting period (P3). The first time period (P31).

16 to FIG. 20 and related description, in FIG. 3, FIG. 7, and FIG. 11 of the present invention, a resetting-related electro-crystal system of a driving circuit can be shared with an adjacent driving circuit, so that the transistor can be largely reduced. Number of. For example, when applying a high-resolution panel, the FHD panel is taken as an example, which has 1080X1920X3=6220800 sub-pixels, so 6,220,800 drive circuits. As with the technique of the present invention, 3,110,400 transistors can be saved since the two drive circuits can save one transistor.

As can be seen from the above description, the transistor on the driving current unit 210 uses a low temperature polysilicon (LTPS) transistor. The LTPS transistor provides a large current when turned on, and has a large driving capability to drive the organic light emitting diode (D1). At the same time, in the reset compensation and illumination control circuit 220, if a transistor is connected to the control terminal (g) of the first transistor (T1), the transistor is changed to an oxide semiconductor transistor to provide a lower The leakage current can eliminate the voltage variation of the control terminal (g) of the first transistor (T1), thereby enabling the first transistor (T1) to provide a stable driving current to the organic light emitting diode (D1). ), which can improve the problem of poor brightness (mura) or poor uniformity of the prior art.

In addition, since the present invention has an architecture in which the two driver circuit portions are shared by the transistors, the number of transistors can be greatly reduced.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

200‧‧‧Drive circuit of active matrix organic light-emitting diode with hybrid transistor

210‧‧‧Drive current unit

220‧‧‧Reset compensation and illumination control circuit

(T1)‧‧‧First transistor

(T2)‧‧‧Second transistor

(T3)‧‧‧ Third transistor

(g) ‧ ‧ control terminal

(Cst)‧‧‧First Capacitor

(T4)‧‧‧ Fourth transistor

(T5)‧‧‧ Fifth transistor

(T6)‧‧‧ sixth transistor

(PLVDD) ‧ ‧ high potential

(a) ‧ ‧ first end

(b) ‧‧‧ second end

(RST)‧‧‧Reset signal

(REF)‧‧‧reference signal

(SN)‧‧‧First Control Signal

(D1)‧‧‧Organic Luminescent Diodes

(EM1)‧‧‧Second control signal

(Data) ‧ ‧ data line

(PLVDD) ‧ ‧ high potential

(PLVSS) ‧‧‧low potential

Claims (10)

A driving circuit of an active matrix organic light emitting diode having a hybrid transistor, comprising: a driving current unit comprising a first transistor and a second transistor, wherein the first transistor and the second transistor a low temperature polycrystalline germanium transistor; and a reset compensation and illumination control circuit coupled to the driving current unit, the reset compensation and illumination control circuit comprising a third transistor coupled to the first transistor A control terminal, wherein the third transistor is an oxide semiconductor transistor. The driving circuit of claim 1, wherein the reset compensation and illumination control circuit further comprises a first capacitor, a fourth transistor and a fifth transistor, wherein the driving current unit further comprises a first a sixth transistor, the first capacitor is connected to a high potential at one end, and the other end is connected to the control end of the first transistor, a first end of the third transistor, and a first end of the fourth transistor a control end of the fourth transistor is connected to a reset signal, a second end of the fourth transistor is connected to a reference signal, and a second end of the third transistor is connected to the first transistor. a second end of the second transistor and a first end of the second transistor, a control end of the third transistor is coupled to a first control signal, and a second end of the second transistor is coupled to an organic light emitting device a first terminal of the second transistor is connected to a second control signal, a first end of the fifth transistor is connected to a data line, and a second end of the fifth transistor is connected to the first a first end of a transistor and a second end of the sixth transistor, the first A first end of the sixth transistor is connected to the high potential, and a control end of the sixth transistor is connected to the second control signal, wherein the fourth transistor is an oxide semiconductor transistor, the second The crystal and the sixth transistor are a low temperature polycrystalline germanium transistor. The driving circuit of claim 1, wherein the reset compensation and illumination control circuit further comprises a first capacitor, a fourth transistor, a fifth transistor, and a sixth transistor. a first end of the first transistor is connected to a high potential, and a second end is connected to a first end of the second transistor and a first end of the third transistor, the second transistor a second end connected to an organic light emitting diode and a second end of the fourth transistor, wherein a control end is connected to a first control signal, and a second end of the third transistor is connected to the first end a control terminal of the transistor and an end of the capacitor, wherein a control terminal is connected to a second control signal, and the other end of the capacitor is connected to a second end of the fifth transistor and a first transistor a first end of the fifth transistor is connected to a data line, a control end is connected to the second control signal, and a second end of the sixth transistor is connected to a first reference signal. One control end is connected to a third control signal, and a first end of the fourth transistor is connected Connected to a second reference signal, a control terminal is coupled to a reset signal, and the second transistor is a low temperature polysilicon transistor. The driving circuit of claim 1, wherein the reset compensation and illumination control circuit further comprises a capacitor, a fourth transistor, a fifth transistor, and a sixth transistor, the first a first end of the transistor is connected to a high potential, and a second end is connected to a first end of the second transistor and a first end of the third transistor, and a second end of the second transistor The second end is connected to an organic light emitting diode, and one control end is connected to a first control signal, and a second end of the third transistor is connected to a control end of the first transistor, one end of the capacitor, and a second end of the fourth transistor is connected to a second control signal, a first end of the fourth transistor is connected to a reset signal, and a control end is connected to a third control a signal, the other end of the capacitor is connected to a second end of the fifth transistor and a first end of the sixth transistor, and a first end of the fifth transistor is connected to a first data line. One control end is connected to the second control signal, and a second end of the sixth transistor is connected To a first reference signal, a control terminal is coupled to a fourth control signal, the fourth transistor is an oxide semiconductor transistor, and the second transistor is a low temperature polysilicon transistor. The driving circuit of claim 1, wherein the reset compensation and illumination control circuit further comprises a first capacitor, a second capacitor, a fourth transistor, a fifth transistor, and a sixth a transistor, the driving current unit further includes a seventh transistor, a first end of the first transistor is coupled to a second end of the fourth transistor and a second end of the seventh transistor, a second end is connected to a first end of the second transistor and a first end of the third transistor, a second end of the second transistor is connected to an organic light emitting diode and the sixth a first end of the transistor is connected to a first control signal, and a second end of the third transistor is connected to a control end of the first transistor, one end of the first capacitor, One end of the second capacitor and a first end of the fifth transistor are connected to a second control signal and the other end of the second capacitor, and the other end of the first capacitor is connected to a low potential. a first end of the fourth transistor is connected to a data line, and a control end thereof is connected to the a second control signal, a second end of the fifth transistor is connected to a third control signal and a second end of the sixth transistor, and a control end is connected to a fourth control signal, the sixth A control terminal of the crystal is connected to a fifth control signal, a first end of the seventh transistor is connected to the high potential, a control terminal is connected to the first control signal, and the fifth transistor is an oxide A semiconductor transistor, which is a low temperature polycrystalline germanium transistor. The driving circuit of claim 3, wherein the second control signal is short-circuited with the third control signal, the fifth transistor is a P-type low temperature polysilicon transistor and the sixth transistor is a N The type oxide semiconductor transistor, or the fifth transistor is an N-type oxide semiconductor transistor and the sixth transistor is a P-type low temperature polycrystalline germanium transistor. The driving circuit of claim 4, wherein the second control signal is short-circuited with the fourth control signal, and the fifth transistor is a P-type low temperature polycrystalline germanium And the sixth transistor is an N-type oxide semiconductor transistor, or the fifth transistor is an N-type oxide semiconductor transistor and the sixth transistor is a P-type low-temperature polycrystalline germanium transistor. The driving circuit of claim 3, further comprising a second capacitor, one end of the second capacitor being connected to the first end of the first transistor, and the other end being connected to the first transistor The control terminal, the sixth transistor system is shared with another driver circuit, wherein the driver circuit performs a reset operation during a reset period, and the other driver circuit performs a light-emitting operation. The driving circuit of claim 8, wherein the driving circuit performs a compensation operation during a first period of a compensation period, and the other driving circuit performs a reset operation at a second of the compensation period. During the period, the driving circuit performs a compensation operation, and the other driving circuit performs a compensation operation. The driving circuit of claim 9, wherein the driving circuit performs a lighting operation during a first period of an illumination period, and the other driving circuit performs a compensation operation for a second period of the illumination period. The driving circuit performs a lighting operation, and the other driving circuit performs a lighting operation.