TW201407805A - Solar cells - Google Patents

Abstract

A composition of matter, in particular a photovoltaic cell, comprising: at least one core semiconductor nanowire on a graphitic substrate, said at least one core nanowire having been grown epitaxially on said substrate wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or at least one group IV element; a semiconductor shell surrounding said core nanowire, said shell comprising at least one group III-V compound or at least one group II-VI compound or at least one group IV element such that said core nanowire and said shell form a n-type semiconductor and a p-type semiconductor respectively or vice versa; and an outer conducting coating surrounding said shell which forms an electrode contact.

Description

Solar battery

The present invention relates to a method for epitaxially growing nanowires on a graphite substrate and subsequently providing a sheath and a conductive coating to the nanowires. In particular, the present invention employs molecular beam epitaxy to epitaxially and ideally grow the nanowires on a graphite substrate, thereby allowing a shell material and then an outer conductive coating material to be carried on the nanowires. on-line. The resulting coated core shell nanowires form a further aspect of the invention. A core shell nanowire with a graphite substrate and an outer conductive coating forms a cell that can be used to absorb photons in solar applications.

In recent years, as nanotechnology has become an important engineering discipline, attention has been raised to semiconductor nanowires. It has been found that nanowires (some authors also refer to them as nanobes, nanorods, nanopillars or nanocylinders) are important applications in a variety of electrical devices, such as sensors, LED solar cells. .

For the purposes of this application, the term nanowire is to be interpreted as being substantially in one-dimensional form (i.e., having a width or diameter and a nanometer dimension whose length is typically in the range of a few hundred nanometers to a few millimeters). a structure. Typically, the nanowires are considered to have at least two dimensions of no more than 500 nm.

Controlling one-dimensional growth at the nanoscale provides a unique opportunity to combine materials and handling properties including mechanical, electrical, optical, thermoelectric, piezoelectric, and electromagnetic properties, as well as to design novel devices.

There are many different types of nanowires, including metal (eg, Ni, Pt, Au) nanowires, semiconducting (eg, Si, InP, GaN, GaAs, ZnO, etc.) nanowires, and insulation (eg, SiO ₂ , TiO ₂ ) nanowire. Although the principles detailed below are contemplated for use in all manner of nanowire technology, the inventors have focused primarily on semiconductor nanowires.

Conventionally, a semiconductor nanowire (homogeneous epitaxial growth) has been grown on one of the same substrates as the nanowire itself. Therefore, the GaAs nanowires are grown on a GaAs substrate, and so on. Of course, this ensures a lattice match between the crystal structure of the substrate and the crystal structure of the grown nanowire. Both the substrate and the nanowires may have the same crystal structure.

However, growing a nanowire on a matching substrate is extremely expensive and restrictive. For example, GaAs substrates need to be specifically manufactured and expensive. To ensure that the nanowires grow along the generally preferred [111] B direction, the substrate needs to be specifically sliced to have a (111) B oriented surface compared to a more common substrate having a (001) oriented surface. A (111) B oriented GaAs substrate is more expensive than a (001) oriented GaAs substrate. In addition, GaAs is not ideal for carrying a nanowire. For example, GaAs is brittle and not inert. GaAs is not flexible or transparent. Preferably, other more attractive substrates can be employed.

The inventors sought ways to get rid of such limiting substrates. Of course, doing this is not only a matter of using one different substrate. The substrate is different from the positively grown nanowire. By definition, there is a possible lattice mismatch between the substrate and the nanowire, and there are many other possible problems to be considered. However, the literature contains several attempts by other workers to grow semiconductor nanowires on alternative substrates.

In Plissard et al., Nanotechnology 21 (2010) (385602-10), several attempts have been made to grow vertical GaAs nanowires on a ytterbium (111) oriented substrate using Ga as a catalyst. Obviously, tantalum is a preferred electronic substrate, but it is also expensive when it is in pure form. In addition, the crucible is not transparent and not flexible. It also has a negative interaction with gold (one of the catalysts commonly used in nanowire growth). Gold can diffuse into the crucible and form a mid-gap defect state in the nanowire and the substrate. In fact, Plissard et al. summarized the undesired use of gold and a Si substrate and developed a gold-free nanowire growth technique.

The inventors sought to epitaxially grow nanowires on a graphite substrate. The graphite substrate is a substrate composed of a single layer or a plurality of layers of graphene or a derivative thereof. In its purest form, graphene is a single atomic layer thick sheet of carbon atoms bonded together by a two-electron bond (referred to as a sp ² bond) configured as a honeycomb lattice pattern. Unlike other semiconductor substrates such as GaAs substrates, graphite substrates provide an extremely inexpensive and readily available material for growing an ideal substrate for a nanowire. It is desirable to use a graphene-based plate which is rarely layered, so that the graphene-based plate is thin, light and flexible, but extremely strong. Its electrical properties can be modified from highly conductive to insulative. It is also unaffected by anything, extremely inert and therefore compatible with gold and other catalysts.

However, the defect-free epitaxial growth of the nanowires between these different material types is not obvious, since (most) semiconductor systems have a three-dimensional shape of reactive dangling bonds at the surface, while graphite has a surface There is no two-dimensional honeycomb structure with dangling bonds and thus forms a very inert and hydrophobic surface.

The growth of nanowires on substrates such as graphite can also be challenging because it has been observed that there will be a large lattice mismatch between the substrate and the growing nanowire. Large lattice mismatches can result in defective nanowires with poor rows or actually result in complete nanowire growth. Epitaxial growth of the nanowires is important so that the nanowires will be ordered and one of the matching substrates will be compatible with the crystal structure.

For many applications, it is important that the nanowires grow vertically perpendicular to the surface of the substrate. Semiconductor nanowires are typically grown in the [111] direction (if cubic crystal structure) or in the direction (if hexagonal crystal structure). This means that the substrate surface (111) or (0001) needs to be oriented, wherein the surface atoms of the substrate are arranged in a hexagonal symmetry.

There are still many difficulties to overcome before a semiconductor nanowire can be grown on a graphite surface.

As mentioned above, many attempts have been made to grow vertical GaAs nanowires on Si (111) substrates. The invention is only concerned with graphite substrates. Has also made crystal growth on graphite substrates Some attempts at nanomaterials.

In JACS (2010, 132, 3270-3271), nanocrystals of oxides and hydroxides of Ni, Co and Fe are synthesized on a graphene support.

In Appl. Phys Lett. (95, 213101 (2009)), Kim et al. report a vertically aligned ZnO nanostructure grown on a graphene layer. These are grown using catalyst-free organometallic vapor phase epitaxy (MOVPE), and the surface morphology of the ZnO nanostructure depends on the growth temperature.

The inventors have discovered that certain compound/element epitaxial nanowires can be grown on a graphite substrate. Since the graphite substrate does not have a dangling bond at the surface and has a very short atomic bond length compared to a typical semiconductor such as germanium and GaAs, there is no reason to expect nucleation and epitaxial growth of the nanowire thereon. As surprisingly described below, depending on how the semiconductor atoms are placed on the surface of the graphene, there is a good lattice match with many semiconductors when graphene is used.

In particular, the use of molecular beam epitaxy provides excellent results in terms of nanowire growth. In particular, the present invention enables the growth of Group IV, II-VI or (specifically) Group III-V semiconductor nanowires on a graphite substrate. The inventors have used this amazing ability to grow epitaxial nanowires on conductive graphite substrates and have developed the concept of photovoltaic cells that can absorb photons and thus provide solar energy technology and value as a photodetector.

Thus, in one aspect, the present invention provides a composition of matter, in particular a photovoltaic cell comprising: at least one core semiconductor nanowire on a graphite substrate, the at least one core nanoparticle a wire has been epitaxially grown on the substrate, wherein the nanowire comprises at least one III-V compound or at least one II-VI compound or at least one Group IV element; a semiconductor shell surrounding the core nanowire The shell layer comprises at least one group III-V compound or at least one group II-VI compound or at least one group IV element such that the core The core nanowire and the shell layer form an n-type semiconductor and a p-type semiconductor, respectively, or vice versa; and an outer conductive coating surrounds the shell layer, the outer conductive coating forming an electrode contact.

Viewed from another aspect, the present invention provides a composition of matter, in particular a photovoltaic cell comprising: at least one core semiconductor nanowire on a graphite substrate, the at least one core nanowire has Epitaxial growth on the substrate, wherein the nanowire comprises at least one III-V compound or at least one II-VI compound or at least one group IV element; a semiconductor shell surrounding the core nanowire, The shell layer comprises at least one group III-V compound or at least one group II-VI compound or at least one group IV element such that the core nanowire and the shell layer form an n-type semiconductor and a p-type semiconductor, respectively, or vice versa And, as the case may be, an external conductive coating surrounding the shell, the outer conductive coating forming an electrode contact.

Viewed from another aspect, the present invention provides a method for preparing a battery as defined above, the method comprising: (I) a Group II-VI element or a Group III-V element or at least one Group IV element Preferably provided to the surface of the graphite substrate via a molecular beam; (II) epitaxially growing at least one nanowire from the surface of the graphite substrate to provide a nanowire core; (III) giving the at least one nano The wire core coating comprises at least one III-V compound or at least one II-VI compound or at least one shell of a Group IV element such that the core nanowire and the shell layer form an n/p junction or a p/n junction; and (IV) coating the shell with an outer conductive coating surrounding one of the shell layers, the outer conductive coating forming an electrode contact, preferably a transparent electrode contact.

Viewed from another aspect, the present invention provides a method for preparing a battery as defined above, wherein a crystal is epitaxially grown in the presence of a catalyst At least one nanowire.

Optionally, the surface of the graphite substrate can be chemically/physically modified to enhance the epitaxial growth of the nanowires.

Viewed from another aspect, the invention provides a device comprising a battery as defined above, such as a solar cell.

Viewed from another aspect, the invention provides a solar cell comprising a plurality of photovoltaic cells as defined above.

In another aspect, the present invention provides a solar cell comprising a plurality of photovoltaic cells as defined above, wherein at least two of the photovoltaic cells have a different band gap and thereby absorb different wavelengths Light.

definition

A III-V compound means a compound comprising at least one ion from Group III and at least one ion from Group V. Similarly, a Group II-VI compound includes at least one Group II ion and at least one VI Group ion compound. In this application, the term (II) family encompasses both the typical (IIa) family cycle and the (IIb) family cycle (ie, the alkaline earth series elements and the Zn series elements). Group IV elements include Si and Ge. It will be appreciated that the term Group IV element encompasses both a single Group IV element and also encompasses the presence of two such elements that can be combined to form a compound such as SiC or SiGe. There may be more than one ion from each family (for example) to form InGaAs or the like.

The term nanowire is used herein to describe a solid linear structure of one of the nanometer dimensions. The nanowire preferably has a uniform diameter throughout most of the nanowires (e.g., at least 75% of its length). The term nanowire is intended to encompass the use of nanorods, nanopillars, nanocylinders or nanowhiskers, some of which may have a tapered end structure. The nanowires can be said to be substantially in the form of one of the nanometer dimensions having a width or diameter and a length generally ranging from a few hundred nanometers to a few micrometers (e.g., 6 micrometers to 8 micrometers). Typically, the nanowires will have two dimensions of no more than 700 nm (ideally no more than 600 nm, especially no more than 500 nm).

Ideally, the diameters at the base of the nanowire and at the top of the nanowire should remain about the same (e.g., within 20% of each other). It will be appreciated that the line must be narrowed at the very top, usually forming a half ball.

It will be appreciated that the substrate preferably includes a plurality of nanowires. This can be referred to as a nanowire array.

The graphite substrate is a substrate composed of a single layer or a plurality of layers of graphene or a derivative thereof. The term graphene refers to a planar sheet of sp ² bonded carbon atoms in a honeycomb structure. The derivatives of graphene are derivatives having surface modifications. For example, a hydrogen atom can be attached to the surface of the graphene to form a graphane. Graphene having an oxygen atom attached to a surface together with carbon and hydrogen atoms is called a graphene oxide. Surface modification may also be treated by chemical doping or oxygen/hydrogen plasma.

The term epitaxy is derived from the Greek roots "epi" (meaning "above") and "taxis" (meaning "in an orderly manner"). The atomic configuration of the nanowire is based on the crystal structure of the substrate. Epitaxy is a term commonly used in this technology. Epitaxial growth as used herein means the growth of one of the orientations of the simulated substrate on the substrate.

Molecular beam epitaxy (MBE) is one of the methods of forming a deposit on a crystalline substrate. The MBE process is performed to heat the lattice structure of the substrate by heating a crystalline substrate in a vacuum. The atomic or molecular mass beam(s) are then directed onto the surface of the substrate. The term element as used above is intended to encompass the use of atoms, molecules or ions of the element. When the directed atom or molecule reaches the surface of the substrate, the directed atom or molecule encounters an energized lattice structure of the substrate or one of the catalyst droplets as detailed below. Over time, the incident atoms form a nanowire.

The term photovoltaic cell is used to indicate the presence of a semiconductor core/shell material and two electrodes (contacts). The battery converts photons from sunlight to electricity.

The term n/p junction or a p/n junction implies that one of the core layer or the shell layer is a p-type semiconductor and the other is an n-type semiconductor, thus forming a junction at the interface between the two layers. path Connect to p/n.

Figure 1a to Figure 1d show the atomic configuration when atoms are placed on 1) H and B sites (Figures 1a, 1b and 1d) and 2) H sites or B sites (Figure 1c). . In Figure 1e, the band gap energy of the III-V semiconductor (and Si and ZnO) is plotted against its lattice constant. A vertical solid (virtual) color line depicts the lattice constant of an ideal crystal relative to one of the graphenes, which will be given and used for one of the four different atomic configurations (Fig. 1a to Fig. 1d) (six sides) Perfect crystal lattice matching of crystalline graphene. This plot shows the great possibility of epitaxially growing vertical semiconductor nanowires on a graphite substrate. In the case of certain semiconductors, the lattice mismatch with graphene is minimal for a proposed atomic configuration (eg, InAs, GaSb, and ZnO). For other semiconductors like GaAs, the lattice mismatch is quite large and exists between two different atomic configurations (as in Figure 1b or Figure 1c).

Figure 2 shows an MBE experiment setup.

Figure 3a is an idealized representation of one of the Ga (self) catalyzed GaAs nanowires grown on graphite.

Figure 3b is a 45° oblique view SEM image of two vertical Ga-assisted GaAs nanowires grown on a condensed graphite sheet by MBE. Spherical particle system Ga droplets.

Figure 3c is a cross-sectional TEM image of a graphite/nano-line interface of a vertical Ga-assisted GaAs nanowire epitaxially grown on top of the condensate graphite.

Figure 4 shows one of the masks on the surface of the graphite that has been etched with holes.

Figure 5a shows a schematic image of a semiconducting nanowire grown by a metal catalyst assisted vapor-liquid-solid (VLS) process. The substrate is graphene deposited on a SiO ₂ substrate.

Figure 5b shows a schematic image as in Figure 5a, but here graphene is used as a top contact material. It is also conceivable that two of the graphene layers serve as one of the two terminals of the nanowire solar cell.

Figure 6a shows an oblique view SEM image of a Ga-assisted GaAs nanowire array grown on a Si (111) substrate by MBE.

Figure 6b shows an SEM image of a GaAs nanowire array covered with a graphene layer deposited on top. The nanowire array was grown as in Figure 6a.

Figure 6c shows an enlarged SEM image of one of the GaAs nanowire arrays having a graphene layer partially deposited on top. The nanowire array was grown as in Figure 6a.

Figure 7 is a schematic illustration of one of the radial core shell nanowire solar cells of the present invention. The nanowire epitaxial growth is carried out on a graphene-based plate having a cerium oxide mask. The carrier material is a metal foil or glass. The core of the nanowire is GaAs, the shell material is AlGaAs and an AlZnO top coat is used.

Figure 8 is a schematic diagram of a double junction solar cell structure using graphene as a common intermediate layer in which two active layers are connected in parallel. The first active low bandgap material can be any semiconductor solar cell material, for example, a Si based n-p junction solar cell. The second active high bandgap material on top of the first cell is made of graphene, pn core on graphene as an intermediate contact for one of the two cells (a common p-type or common n-type contact can be used) The shell III-V semiconductor nanowire array and a top transparent conductive layer are formed. The top conductive layer can be any transparent conductive material comprising graphene.

The invention will now be illustrated with reference to the following non-limiting examples.

Example 1 Test procedure:

The nanowire is grown in a Varian Gen II module molecular beam epitaxy (MBE) system equipped with a Ga double wire unit, an In SUMO double wire unit and an As valve controlled cracking unit, thereby allowing the immobilization of the dimer and the four The ratio of the polymer. In this study, the main species of arsenic is As ₄ . NW growth is performed on a condensed graphite sheet or on a graphene film (1 single layer thick to 7 single layer thick) by a chemical vapor deposition (CVD) of the condensed graphite sheet or graphene film The technique is directly grown on a Ni or Cu film deposited on a cerium oxide wafer. The CVD graphene film was purchased from "Graphene Supermarket" in the United States. Samples were prepared using two different procedures. In the first procedure, the sample is cleaned by isopropyl alcohol, followed by a blow drying with one of the nitrogens, and then In is bonded to the germanium wafer. In the second procedure, a layer of -30 nm thick SiO ₂ is deposited on a sample prepared using the first procedure in an electron beam evaporator chamber, and then the diameter is made in SiO ₂ using electron beam lithography and plasma etching. ~100nm hole.

The sample is then loaded into an MBE system for nanowire growth. Then, the substrate temperature is increased to a temperature suitable for the growth of the GaAs/InAs nanowire: that is, 610 ° C / 450 ° C, respectively. First, supply Ga/In flux to the surface during one of the time intervals typically between 5 minutes and 10 minutes (depending on the Ga/In flux and the desired droplet size) while closing the As gate to Formation of Ga/In droplets on the starting surface. The GaAs/InAs nanowire growth is initiated by simultaneously opening the gate of the Ga/In effusion cell and the gate and valve of the As bleed unit. The temperature of the Ga/In effusion cell is preset to produce a nominal planar growth rate of 0.1 μm/hour. To form a GaAs nanowire, an As ₄ flux of 1.1 × 10 ^-6 Torr was used, and the As ₄ flux was set to 4 × 10 ^-6 Torr to form an InAs nanowire.

For p-type doping of GaAs core nanowires, beryllium (Be) is used. The Be cell temperature was set to 990 ° C, which gave a nominal p-type doping concentration of 3 x 10 ¹⁸ cm ^-3 . Under the conditions mentioned above, the nanowire growth was carried out for a duration of 3 hours, and the growth was stopped by closing all the gates and simultaneously tilting the substrate to room temperature. For the n-type doping of the GaAs core nanowire, germanium (Te) is used at a battery temperature of 440 ° C, which corresponds to a nominal n-type doping concentration of 4 × 10 ¹⁸ cm ^-3 . The Te-doped GaAs nanowires were grown at a substrate temperature of 580 ° C and at an As flux of 8 × 10 ^-7 Torr. All other conditions are the same as for the Be-doped nanowire.

Finally, a Be-doped GaAs p core with a Si-doped GaAs n shell and a Te-doped GaAs n core with a Be-doped GaAs p shell are also grown. After growing the Be-doped GaAs p core, the Ga droplets were depleted into the nanowire material by performing a growth interruption of 10 min, in which the Ga gate was closed and the As flux was increased to 1 × 10 ^-5 Torr. . To grow the Si-doped n-type GaAs shell layer, the substrate temperature was reduced to 540 ° C and the As flux was increased to 1.5 × 10 ^-5 Torr. When the shutter is opened, growth occurs only on the side of the GaAs core forming a core shell structure. The GaAs shell growth was carried out at a Si cell temperature of 1295 ° C for a duration of one hour, which would result in a nominal n-type doping concentration of 1 x 10 ¹⁸ cm ^-3 . In the case of a Te-doped GaAs core and a Be-doped GaAs shell, the substrate temperature was increased to 610 ° C for shell growth and the As flux used was 4 × 10 ^-6 Torr.

Example 2 - Axial p/n junction

The axial p-n and n-p junction GaAs core nanowires were grown by using Be as the p-dopant and Te as the n-dopant. The GaAsp(n) core was grown for one of the durations of 1.5 hours using the same growth conditions as in Example 1. Then, close the Be(Te) gate and open the Te(Be) gate to switch the dopant and continue the growth for 1.5 hours.

Example 3 - Transparent Electrode Contact Coating

A final conformal cover of one of the MBE grown nanowires having a transparent contact is formed by depositing Al-doped ZnO (AZO) using atomic layer deposition (ALD). For ALD, use trimethylaluminum, diethylzinc and go in a custom flow type reactor with one of argon carrier gases at a flow rate of 10 sccm at one of 50 mTorr and one temperature of 200 °C. Ionic water acts as a precursor.

Example 4 - Experimental procedure for transferring a graphite layer to the top of a nanowire array:

A graphite layer (<5 layers) grown on a Cu foil was used. Since the graphite layer is formed on both sides of the Cu foil during CVD growth, the graphite layer formed on one side is removed by oxygen plasma to expose Cu for etching. Then, this was immersed in a dilute iron nitrate (Fe(NO ₃ ) ₃ ) solution (<5%) to completely etch Cu. After overnight etching (>8 hours), the graphite layer was floated on an etching solution that was replaced with deionized water. After further washing with deionized water several times, the graphite layer was transferred to the array of nanowires together with deionized water. Deionized water naturally dries out in a clean room without any N ₂ blowing.

The present invention relates to epitaxial growth of a nanowire as a first step on a graphite substrate. The composition of the present invention comprises both a substrate and a nanowire grown thereon.

One of the nanowires with epitaxial growth provides homogeneity with the material being formed, which can enhance various end properties, such as mechanical, optical or electrical properties.

The epitaxial nanowire can be grown from a gaseous or liquid precursor. Since the substrate acts as a sub-crystal, the deposited nanowires can take one of the same lattice structures and orientations as the lattice structure and orientation of the substrate. This is different from other thin film deposition methods in which a polycrystalline film or an amorphous film is deposited even on a single crystal substrate.

In the present invention, the substrate is a graphite substrate, and more particularly, it is graphene. As used herein, the term graphene refers to a planar sheet of sp ² bonded carbon atoms densely packed in a honeycomb (hexagonal) crystal lattice. The graphene-based plate should contain no more than 10 layers of graphene or a derivative thereof, preferably no more than 5 layers (referred to as a very little layered graphene). Particularly preferably, it is a monoatomic thick planar sheet of graphene.

The crystalline or "slice" form of graphite consists of a plurality of graphene sheets (i.e., more than 10 sheets) stacked together. Therefore, a graphite substrate means a substrate formed of one or a plurality of graphene sheets.

Preferably, the thickness of the substrate is 20 nm or less. The graphene sheets were stacked to form graphite having an interplanar spacing of 0.335 nm. Preferred substrates include only a few of these layers and desirably, the thickness can be less than 10 nm. Even more preferably, the thickness may be 5 nm or less. The area of the substrate is not limited. This can be up to 0.5 mm ² or more, for example up to 5 mm ² or more, such as up to 10 cm ² . Therefore, the area of the substrate is limited only by practicality.

It will be appreciated that it may be desirable to support the graphite substrate to allow growth of the nanowires thereon. However, in some embodiments, for example, where the graphite layer forms both a substrate and a top electrode contact in a series of cells, such a support may not be required as set forth below. Graphene thin The sheet can be supported on any type of material comprising a conventional semiconductor substrate and transparent glass. Preferably, cerium oxide or SiC is used. The support must be inert. It is also possible to deposit a graphite substrate directly on a metal film deposited on a cerium oxide wafer or directly on a metal foil. The graphite substrate can then be detached from the metal by etching and easily transferred to any material.

For the bottommost or bottom cell in a stack (as explained later herein), the battery substrate need not be transparent. Therefore, if graphene on the metal foil is used as a substrate, this can be directly used as the bottom electrode. Therefore, in this case, graphene does not need to be removed from the metal foil. However, if a battery is not a bottom cell in a stack, the substrate should be transparent to allow light to penetrate down to the next cell in a stack.

In a highly preferred embodiment, the carrier material used will be transparent, such as glass. The use of a transparent support material is important in the field of solar technology to allow light to penetrate the solar cell of the present invention.

In a highly preferred embodiment, the graphite substrate is one of a delaminated (Kish) graphite delaminated substrate or a highly oriented pyrolytic graphite (HOPG). Alternatively, it may be a graphene-based plate grown by chemical vapor deposition (CVD) on a metal film or a metal foil made of, for example, Cu, Ni or Pt.

Although it is preferred to use a graphite substrate without modification, the surface of the graphite substrate can be modified. For example, it can be treated with a slurry of hydrogen, oxygen, NO _2, or a combination thereof. Oxidation of the substrate enhances nanowire nucleation. It is also preferred to pretreat the substrate, for example, to ensure purity prior to growth of the nanowire. A treatment with a strong acid such as HF or BOE is an option. The substrate can be rinsed with isopropanol, acetone or N-methyl-2-pyrrolidone to remove surface impurities.

The cleaned graphite surface can be further modified by doping. A dopant atom or molecule can serve as a seed for growing the nanowire. The graphite substrate can be doped by adsorbing organic or inorganic molecules such as metal chlorides (FeCl ₃ , AuCl ₃ or GaCl ₃ ), NO ₂ , HNO ₃ , aromatic molecules or ammonia. Therefore, a solution of one of FeCl ₃ , AuCl ₃ or GaCl ₃ can be used in a doping step.

Therefore, it is also contemplated that the surface of the graphite substrate may be doped during its growth by a doping method of doping a dopant such as B, N, S or Si.

Preferably, the graphite substrate is doped with the same dopant material as the nanowire.

The use of a graphite substrate (ideally a thin graphite substrate) is highly advantageous in the present invention, whereby the graphite substrate is therefore thin but extremely strong, light and flexible, highly conductive and thermally conductive. The graphite substrates are transparent at the low thicknesses preferred for use herein and are impermeable and inert.

To enhance the conductivity of the graphite substrate, metal nanostructures (such as nanowires and nanoparticles) having a high electrical conductivity (>10 ³ S/cm) may (particularly) be partially interconnected (eg, one This way of the Ag nanowire/graphene mixed top contact) is dispersed on the top.

To prepare commercially important nanowires, these nanowires are substantially epitaxially grown on a substrate. Also desirably, the growth occurs perpendicular to the substrate and thus desirably along [111] (for cubic crystal structures) or (for hexagonal crystal structures) directions. As described above, it is not possible to ensure that one of the substrate materials is different from a specific substrate of one of the positively grown nanowires. However, the inventors have determined that epitaxial growth on a graphite substrate is possible by determining a possible lattice match between the atoms in the semiconductor nanowire and the carbon atoms in the graphene sheets.

The carbon-carbon bond length in the graphene layer is about 0.142 nm. Graphite has a hexagonal crystal geometry. The inventors have surprisingly recognized that graphite can provide one of the substrates on which semiconductor nanowires can be grown, since the lattice mismatch between the grown nanowire material and the graphite substrate can be extremely low.

The inventors have recognized that due to the hexagonal symmetry of the graphite substrate and the (111) plane of one of the nanowires grown in the [111] direction with a cubic crystal structure (or an edge having a hexagonal crystal structure) The hexagonal symmetry of the semiconductor atoms in the (0001) plane of one of the nanowires, so that a tight lattice can be achieved between the grown nanowire and the substrate. match.

1a to 1d show (111) (or (0001)) one of the nanowires on the top of a hexagonal lattice of carbon atoms in a graphene layer in which the lattice mismatch does not occur. The configuration of four different hexagonal structures of semiconductor atoms in a plane. As a possible semiconductor adsorption site on the top of graphene, consider 1) above the center of the hexagonal carbon ring of graphene (H site) and 2) above the bridge between carbon atoms (B site), As indicated by the arrows in Figure 1a.

The figures show a cubic crystal when the atoms are placed at 1) H and B (Fig. 1a, Fig. 1b and Fig. 1d) and 2) H or B (Fig. 1c). An idealized lattice matching configuration of one of the (111) planes (the (0001) plane of the hexagon). The dashed line emphasizes the hexagonal symmetry of the crystal lattice of the semiconductor atoms in the (111) plane. The relative rotation of these hexagons for each atomic configuration is written on top of each figure. For (Fig. 1a) and (Fig. 1d), two relative orientations of ±10.9° and ±16.1°, respectively, are possible (only + rotation is shown in the image).

Figure 1e shows the artificial lattice matching lattice constants for the atomic configurations in (a), (b), (c), and (d). The dotted line and the solid line correspond to the hexagon (a ₁ ) and the cube of the lattices respectively (a=a ₁ × 2) Crystal phase. Squares (■) and hexagons represent cubic and hexagonal phases for Si, ZnO, and III-V semiconductors, respectively. Squares with two different colors (GaAs, AlAs, AlSb) indicate that the semiconductor can be selected from either of the two atomic configurations on graphene. This figure shows the great possibility of epitaxial growth of vertical semiconductor nanowires on a graphite substrate.

If a semiconductor atom is placed above the alternating H site and B site as in FIG. 1a, if a cubic semiconductor crystal has a lattice constant a (the lattice constant a is defined as the side length of the cubic unit cell) is equal to 4.670 Å, An exact lattice match can be achieved. Some cubic semiconductors have lattice constants close to this value, the closest being SiC (a = 4.36 Å), AlN (a = 4.40 Å), and GaN (a = 4.51 Å). For a hexagonal semiconductor crystal, if the lattice constant a ₁ is equal to 3.258 Å, an exact lattice match will be achieved. Some hexagonal semiconductors have lattice constants close to this value, the closest of which is SiC (a ₁ =3.07Å), AlN (a ₁ =3.11Å), GaN (a ₁ =3.19Å), and ZnO(a). ₁ = 3.25 Å) crystal.

If a semiconductor atom is placed above the alternating H and B sites as in Figure 1b, then if a cubic semiconductor crystal has a lattice constant a equal to: 1.422 Å (carbon atom distance) × 3/2 × sqr (6) =5.225Å, an exact lattice match can be achieved. This is close to the lattice constants of Si (a = 5.43 Å), GaP (a = 5.45 Å), AlP (a = 5.45 Å), InN (a = 4.98 Å), and ZnS (a = 5.42 Å). For a hexagonal semiconductor crystal, if the lattice constant a ₁ is equal to: 1.422 Å × 3 / 2 × sqr (3) = 3.694 Å, the exact lattice matching will be achieved. This is close to the a ₁ lattice constant of the hexagonal form of InN (a ₁ = 3.54 Å) and ZnS (a ₁ = 3.82 Å) crystals.

For the atomic configuration as in Figure 1c, if the lattice constant a of a cubic semiconductor crystal is equal to: 1.422 Å (carbon atom distance) x 3 x sqr(2) = 6.033 Å, an exact lattice match can be achieved. This is close to the lattice constant of the III-V compound (such as InAs, GaAs, InP, GaSb, AlSb, and AlAs) and the II-VI compound (such as MgSe, ZnTe, CdSe, and ZnSe) semiconductor crystals. In particular, this is close to Group III-V compounds (such as InAs (a = 6.058 Å), GaSb (a = 6.096 Å) and AlSb (a = 6.136 Å)) and Group II-VI compounds (such as ZnTe (a = 6.103Å) and CdSe (a=6.052Å)) The lattice constant of the semiconductor crystal.

For a hexagonal semiconductor crystal, if the lattice constant a ₁ is equal to: 1.422 Å (carbon atom distance) × 3 = 4.266 Å, an exact lattice match will be achieved. This is close to the a ₁ lattice constant of the hexagonal form of the CdS (a ₁ = 4.160 Å) and CdSe (a ₁ = 4.30 Å) crystals of the II-VI material.

If a semiconductor atom is placed above the alternating H and B sites as in Figure 1d, an exact lattice match can be achieved if the lattice constant a of a cubic semiconductor crystal is equal to 6.28 Å. This is close to the lattice constant of InSb (a = 6.479 Å), MgTe (a = 6.42 Å), and CdTe (a = 6.48 Å). For a hexagonal semiconductor crystal, if the lattice constant a ₁ is equal to 4.44 Å, an exact lattice match will be achieved. This is close to the a ₁ lattice constant of the hexagonal form of InSb (a ₁ = 4.58 Å), MgTe (a ₁ = 4.54 Å), and CdTe (a ₁ = 4.58 Å) crystals.

Without wishing to be bound by theory, due to the hexagonal symmetry of the carbon atoms in the graphite layer, and the cubes along the [111] and crystal directions (for the preferred direction of most of the nanowire growth) Or the hexagonal symmetry of the atoms of the hexagonal semiconductor, so that when the semiconductor atoms are ideally placed in a hexagonal pattern over the carbon atoms of the graphite substrate, a tight lattice matching between the graphite substrate and the semiconductor can be achieved. . This is a new and surprising discovery and can enable epitaxial growth of nanowires on graphite substrates.

The four different hexagonal configurations of the semiconductor atoms as set forth above allow the semiconductor nanowires of such materials to grow vertically to form individual nanowires on top of a thin carbon-based graphite material.

For example, although it is desirable to have no lattice mismatch between a grown nanowire and a substrate, the nanowire can accommodate much more lattice mismatch than the thin film. The nanowires of the present invention can have a lattice mismatch of up to about 10% of the substrate, and epitaxial growth is still possible. Ideally, the lattice mismatch should be 7.5% or less than 7.5%, for example, 5% or less than 5%.

For cubes like InAs (a=6.058Å), cube GaSb (a=6.093Å), cubic CdSe (a=6.052Å), hexagonal CdSe (a ₁ =4.30Å) and hexagonal ZnO (a ₁ =3.25 Some semiconductors of Å) have a lattice mismatch that is so small (<~1%) that excellent growth of such semiconductors can be expected.

For some semiconductors like GaAs (a = 5.653 Å), the semiconductor atoms are placed at the same location as in Figure 1c (a = 6.033 Å and therefore the lattice constant of GaAs is 6.3%) or as in Figure 1b ( The lattice mismatch is quite small when the alternating H and B sites in the a = 5.255 Å and therefore the GFP lattice constant is 8.2%) (both configurations are possible). The method of the present invention enables the semiconductor nanowires of the materials mentioned above to be grown vertically to form individual nanowires on top of a thin carbon-based graphite material.

The length of the nanowires grown in the present invention can range from 250 nm to several microns, for example, up to 8 microns or up to 6 microns. Preferably, the length of the nanowire is at least 1 micron. Alive In the case of a plurality of nanowires, preferably, all of them satisfy these dimensional requirements. Ideally, at least 90% of the nanowires grown on a substrate will have a length of at least 1 micron. Preferably, substantially all of the nanowires will have a length of at least 1 micron.

Furthermore, it will be preferred that the grown nanowires have the same size, for example within 10% of each other. Thus, at least 90% (preferably substantially all) of the nanowires on a substrate will preferably have the same diameter and/or the same length (i.e., within 10% of the diameter/length of each other). Therefore, basically, those skilled in the art are looking for nanowires of homogeneity and substantially the same in terms of size.

The length of the nanowire is usually controlled by the length of time the growth program is run. A longer procedure usually results in a (longer) longer nanowire.

The nanowires usually have a hexagonal cross-sectional shape. The nanowire may have a cross-sectional diameter (ie, its thickness) of 25 nm to 700 nm (such as 25 nm to 600 nm, especially 25 nm to 500 nm). As described above, the diameter is ideally constant throughout most of the nanowires. The diameter of the nanowires can be manipulated to produce a ratio of atoms of the nanowires as further explained below.

In addition, the length and diameter of the nanowires can be affected by the temperature at which they are formed. Higher temperatures contribute to high aspect ratios (i.e., longer and/or thinner nanowires). Those skilled in the art will be able to manipulate the growth program to design a nanowire of the desired size.

The nanowire of the present invention is formed of at least one III-V compound, at least one II-VI compound, or it may be derived from at least one Group IV element selected from Si, Ge, Sn or Pb (especially Si and Ge). Rice noodles. Therefore, the formation of a pure Group IV nanowire or a nanowire such as SiC and SiGe is contemplated.

Group II elements are Be, Mg, Ca, Zn, Cd and Hg. Preferred options here are Zn and Cd.

Group III options are B, Al, Ga, In, and Tl. Here, preferred options are Ga, Al, and In.

The V family options are N, P, As, Sb. All options are preferred.

The VI family options include O, S, Se, and Te. Se and Te are preferably used.

It is preferred to produce a Group III-V compound. It will be appreciated that any compound formed during the growth of the nanowire does not need to be completely stoichiometric due to the possibility of doping, as discussed below.

Preferred compounds for the manufacture of nanowires include InAs, GaAs, InP, GaSb, InSb, GaP, ZnTe, SiC, CdSe, and ZnSe. GaAs or InAs are preferably used highly. Other options include Si, ZnO, GaN, AlN, and InN.

Although a binary material is preferably used, there is no reason why it is impossible to grow a ternary or quaternary nanowire or the like by the method of the present invention. Epitaxial growth can be expected as long as the crystal lattice of the compound in question matches the crystal lattice of the substrate, especially graphene. Thus, a ternary system in which two Group III cations and a Group V anion are present is an option here, such as InGaAs and AlGaAs. Thus, the ternary compound may have the chemical formula XYZ, wherein X is a Group III element, Y is different from X and Z one of Group III or V elements, and Z is a Group V element. X and Y or Y and Z mole in XYZ are preferably from 0.2 to 0.8, that is, the chemical formula is preferably X _x Y _1-x Z (or XY _1-x Z _x ), wherein the subscript x is 0.2 to 0.8. The quaternary system can be represented by the chemical formula A _x B _1-x C _y D _1-y , where A and B are Group III elements and C and D are Group V elements. Again, the subscripts x and y are typically between 0.2 and 0.8. Those skilled in the art will be aware of other options.

The nanowire to be doped is within the scope of the present invention. Doping generally involves introducing impurity ions into the nanowires. These impurity ions can be introduced at one of up to 10 ¹⁹ /cm ³ (preferably up to 10 ¹⁸ /cm ³ ). As desired, the nanowires can be p-doped or n-doped, but as described below, there may be an undoped layer. The doped semiconductor is an impure conductor and the undoped semiconductor is pure.

An impure semiconductor having an electron concentration greater than the concentration of the hole is referred to as an n-type semiconductor. In an n-type semiconductor, electrons are majority carriers and holes are minority carriers. The N-type semiconductor is formed by doping a pure semiconductor with a donor impurity. Suitable for III-V compounds The combined body can be, for example, Si and Te.

The p-type semiconductor has a hole concentration greater than the electron concentration. The phrase "p-type" refers to the positive charge of a hole. In a p-type semiconductor, a hole is a majority carrier and an electron is a minority carrier. A P-type semiconductor is formed by doping a pure semiconductor with a acceptor impurity. Suitable acceptors for the III-V compound can be, for example, Be and Zn. It will be appreciated that in some cases, whether an impurity will act as one of the III-V compounds or the acceptor will depend on the orientation of the growth surface and the growth conditions. The dopant can be introduced by ion implantation of the nanowire during or after the growth process.

Suitable donors for the Group IV nanowires can be, for example, P and As. Suitable acceptors for Group IV can be, for example, B and Al. Suitable donors for the II-VI compound are generally readily detectable and can be, for example, Al and Ga. Suitable receptors are more difficult to find for many II-VI compounds but can be, for example, Li and Mg.

The nanowire of the present invention is epitaxially grown. It is attached to the underlying graphite substrate by a covalent bond, an ionic bond or a quasi-vana combination. Therefore, at the junction of the substrate and the substrate of the nanowire, crystal plane epitaxy is formed in the nanowire. These crystal planes are constructed one above the other in the same crystal direction, allowing epitaxial growth of the nanowires. Preferably, the nanowires grow vertically. Here, the term is used vertically to imply that the nanowires are grown perpendicular to the graphite support. It will be appreciated that in experimental science, the angle of growth may not be exactly 90°, but rather the term vertically implies that the nanowire is within about 10° of vertical/perpendicular, for example, within 5°.

It will be appreciated that the substrate preferably includes a plurality of nanowires. Preferably, the nanowires grow about parallel to each other. Thus, preferably, at least 90% (e.g., at least 95%, preferably substantially all) of the nanowires are grown in the same direction from the same plane of the substrate.

It will be appreciated that there are many planes in one of the substrates in which epitaxial growth can occur. Preferably, substantially all of the nanowires are grown in the same plane such that they are parallel. More preferably, the plane is perpendicular to the substrate.

The nanowire of the present invention should preferably be grown in the [111] direction for a nanowire having a cubic crystal structure and in the direction of a nanowire having a hexagonal crystal structure. If the crystal structure of the grown nanowire is cubic, this also indicates the (111) interface between the cubic nanowire in which axial growth occurs and the catalyst droplet. If the nanowire has a hexagonal crystal structure, the (0001) interface between the nanowire and the catalyst droplet represents a plane in which axial growth occurs. Both planes (111) and (0001) represent the same (hexagonal) plane of the nanowire, and the nomenclature of this plane depends only on the crystal structure of the grown nanowire.

The nanowires are preferably grown by molecular beam epitaxy (MBE). Although vapor phase deposition to be used is within the scope of the present invention, for example, a CVD, especially an organometallic CVD (MOCVD) or organometallic vapor phase epitaxy (MOVPE) process, MBE is highly preferred. In this method, the substrate is provided with a molecular beam of one of each reactant, for example, preferably one of a group III element and a group V element are simultaneously supplied. Control of a higher degree of nucleation and growth of the nanowire on the graphite substrate can be achieved by means of MBE technology using migration enhanced epitaxy (MEE) or atomic layer MBE (ALMBE), alternatively Supply, for example, Group III and V elements.

A preferred technique is a solid state source MBE in which very pure elements, such as gallium and arsenic, are heated in a separate effusion cell until they begin to slowly evaporate (eg, gallium) or sublimate (eg, arsenic). The gaseous element then condenses on the substrate, wherein the gaseous elements can react with each other. In the examples of gallium and arsenic, single crystal GaAs is formed. The use of the term "bundle" implies that the vaporized atoms (eg, gallium) or molecules (eg, As ₄ or As ₂ ) do not interact with each other or interact with the vacuum chamber gases before they reach the substrate.

It is also easy to introduce doping ions using MBE. Figure 2 is a possible setup of one of the MBE machines.

MBE occurs in an ultra-high vacuum having a background pressure of typically from about ^10-10 Torr to 10 ^-9 Torr. The nanostructures are typically grown slowly, such as at a rate of up to a few μm/hour, such as about 10 μm/hour. This allows epitaxial growth of the nanowires and maximizes structural efficiency.

Nanowires to be grown in the presence or absence of a catalyst are within the scope of the invention. Thus, a nanowire without catalyst growth is an embodiment of the invention.

Preferably, a catalyst is used in the growth procedure. The catalyst may be one of the elements constituting the nanowire - so-called autocatalysis, or any of the elements constituting the nanowire.

For catalyst-assisted growth, the catalyst may be Au or Ag, or the catalyst may be from one of the metals used in the growth of the nanowire (eg, Group II or III metals), especially among the metal elements of the actual nanowire. One of them (self-catalytic). Therefore, it is possible to use another element of the group III as a catalyst for growing a III-V nanowire, for example, using Ga as a catalyst for an In (V group) nanowire or the like. Preferably, the catalyst is Au, or the growth system is autocatalytic (i.e., Ga is used for a Ga (V group) nanowire, etc.). The catalyst can be deposited on a graphite substrate to serve as a nucleation site for growing the nanowires. Ideally, this can be achieved by providing a film of one of the catalytic materials formed over the surface of the substrate. When the catalyst film is melted (generally forming a eutectic alloy having one or more of the semiconductor nanowire components), it forms droplets on the substrate and the droplets form a point where the nanowires can be grown. This is referred to as vapor-liquid-solid growth (VLS) because the catalyst system liquid, molecular beam vapor and nanowire provide a solid component. In some cases, the catalyst particles may also be solid during the growth of the nanowires by a so-called vapor-solid-solid growth (VSS) mechanism. When the nanowires are grown (by the VLS method), liquid (eg, gold) droplets remain on top of the nanowire. This is shown in the figures.

As described above, it is also possible to prepare autocatalytic nanowires. Autocatalytic means one of the components of the nanowire acts as a catalyst for its growth.

For example, a Ga layer can be applied to the substrate, melted to form droplets that serve as nucleation sites for growing Ga-containing nanowires. Again, a Ga metal portion can be finally positioned on top of the nanowire. Group II or Group III metals can be used as catalysts for containing the The catalyst is used as a component of the nanowire to achieve a similar procedure.

In more detail, a Ga/In flux can be supplied to the surface of the substrate over a period of time to form the Ga/In droplets on the starting surface immediately after heating the substrate. The substrate temperature can then be set to a temperature suitable for growing one of the nanowires in question. The growth temperature can range from 300 °C to 700 °C. However, the temperatures employed are limited to the nature of the materials and catalyst materials in the nanowire. For GaAs, a preferred temperature is from 590 ° C to 630 ° C, for example, 610 ° C. For InAs, the range is lower, for example, 430 ° C to 540 ° C, such as 450 ° C.

Once a catalyst film has been deposited and melted, the nanowire growth can be initiated by simultaneously opening the gate of the Ga/In effusion cell and the counter of the ion effusion cell.

The temperature of the effusion unit can be used to control the growth rate. A suitable growth rate measured during conventional planar (layer by layer) growth is from 0.05 μm/hr to 2 μm/hr, for example, 0.1 μm/hr.

The pressure of the molecular beam can also be adjusted depending on the nature of the nanowire being grown. The suitable level of the beam equivalent pressure is between 1 x 10 ^-7 Torr and 1 x 10 ^-5 Torr.

It has been surprisingly found that the use of MBE tends to cause the GaAs nanowires to grow vertically on the (111) B plane of a GaAs substrate.

The beam flux ratio between the variable reactants (e.g., Group III atoms and Group V molecules), the preferred flux ratio depends on other growth parameters and the nature of the positively growing nanowire.

It has been found that the beam flux ratio between the reactants can affect the crystal structure of the nanowire. For example, using Au as a catalyst, a GaAs nanowire is grown at a growth temperature of 540 ° C, a Ga flux equal to a plane (layer by layer) growth rate of 0.6 μm / hour, and 9 × 10 of As ₄ A bundle of equivalent pressure (BEP) of ^-6 Torr produces a wurtzite crystal structure. In contrast, GaAs nanowires were grown at the same growth temperature, but one of the Ga fluxes was equal to a plane growth rate of 0.9 μm/hr, and ₄ of 10 ^{Å to 6} Å of As ₄ produced sphalerite crystals. structure.

In some cases, the diameter of the nanowire can be varied by changing the growth parameters. For example, when an autocatalytic GaAs nanowire is grown under the condition that the axial nanowire growth rate is determined by the As ₄ flux, the Ga:As ₄ flux ratio can be increased/decreased. Increase/decrease the diameter of the nanowire. Thus, those skilled in the art are able to manipulate the nanowires in a number of ways.

Thus, one embodiment of the present invention employs a multi-step process, such as two steps, a growth procedure, for example, to optimize nanowire nucleation and nanowire growth, respectively.

One of the significant benefits of MBE is that the grown nanowires can be analyzed in situ, for example, by using reflected high energy electron diffraction (RHEED). RHEED is a technique commonly used to characterize the surface of crystalline materials. In the case where the nanowire is formed by other techniques such as MOVPE, this technique cannot be applied so easily.

One limitation of the techniques set forth above is the limited control of where the nanowires are present on the surface of the substrate. The nanowires will grow where a catalyst droplet is formed, but there is minimal control over where droplets can be formed. A further problem is that it is not easy to control the size of the droplets. If the formation is too small to initiate the nucleation of a nanowire, the yield of the nanowire can be lower. This is a particular problem when using gold catalysis because the droplets formed from gold can be too small to allow high nanowire growth.

To prepare a more regular array of nanowires, the inventors envisioned using a mask on the substrate. The mask can have regular holes in which the nanowires can grow homogenously across the surface. Hole patterns in the mask can be easily fabricated using conventional light/electron beam lithography or nanoimprinting. A focused ion beam technique can also be used to form a regular array of nucleation sites on the surface of the graphite used for nanowire growth.

Thus, a mask can be applied to the substrate and etched (as appropriate) with a pattern of exposed holes in the surface of the graphite substrate. In addition, the size of the holes can be carefully controlled. Catalysts can then be introduced into their pores to provide nucleation sites for nanowire growth. By regularly arranging the holes, a regular pattern of the nanowires can be grown.

In addition, the size of the holes can be controlled to ensure that only one nanometer can be grown in each well line. Finally, the pores can be made with a droplet in which the catalyst formed in the pores is large enough to allow for the growth of the nanowires. In this way, Au catalysis can be used to grow a regular array of nanowires.

The mask material can be any material that does not significantly damage the underlying graphite layer during deposition. The pores used in this embodiment may be slightly larger than the diameter of the nanowire, for example, up to 200 nm. The minimum pore size may be 50 nm, preferably at least 100 nm to 200 nm.

The mask itself may be made of an inert compound such as hafnium oxide or tantalum nitride. It can be provided on the surface of the substrate by any suitable technique, such as by electron beam deposition, CVD, plasma enhanced CVD, and sputtering. The thickness of the mask itself can be less than 50 nm.

In a highly preferred embodiment, the mask also provides an insulating layer between the graphite substrate and the outer coating discussed below.

To prepare a positioned Au catalyzed nanowire on a graphite substrate, a thin Au layer having a thickness of less than 50 nm can be deposited, for example, after etching the hole pattern in the mask. This deposition can be made by means of a photoresist or electron beam resist on the top. A regularly patterned pattern of Au dots on the surface of the graphite substrate can be made by removing the photoresist or electron beam resist, a so-called "peeling" procedure. The mask may be partially or completely removed after fabrication, as appropriate.

Although catalyst-assisted growth techniques are preferred in the present invention, it is contemplated that the nanowires can be grown on a graphite substrate in the absence of a catalyst. This can be especially possible in combination with a mask.

In particular, nanowire growth can be achieved simply by using vapor-solid growth. Thus, in the context of MBE, the simple application of reactants (e.g., In and As) to the substrate without any catalyst can result in the formation of a nanowire. This forms a further aspect of the invention which thus provides for the direct growth of a semiconductor nanowire formed from the elements set forth above on a graphite substrate. Therefore, the term directly implies that there is no catalyst film to achieve growth.

As described above, the nanowire of the present invention preferably grows into a cubic (sphalerite) or hexagonal (zinc-zinc) structure. The inventors have discovered that it is possible to alter the crystal structure of the grown nanowires by manipulating the amount of reactants fed to the substrate, as discussed above. For example, a higher feed amount of Ga forces a GaAs crystal into a cubic crystal structure. The lower feed amount contributes to a hexagonal structure. By manipulating the concentration of the reactants, the crystal structure within the nanowire can be altered.

The nature of the material forming the nanowire to be altered during the growth procedure is also within the scope of the invention. Thus, by changing the nature of the molecular beam, a portion of the different structures will be introduced into a nanowire. An initial GaAs nanowire can extend, for example, an InAs nanowire segment by changing from a Ga feed to an In feed. The GaAs/InAs nanowire can then be expanded with a GaAs nanowire segment by changing back to a Ga feed, and so on. Again, by developing different structures with different electrical properties, the inventors provide nanowires with interesting and steerable electronic properties.

In this regard, a nanowire is grown to have one of the n/p junctions axially present in the nanowire. This can be achieved by changing the nature of the dopant material as it grows on the nanowire. Thus, during initial growth, an n-type dopant pattern can be used to introduce n-type conductivity into the nanowire. The nanowires can include p-type conductivity by changing the dopant to a p-type dopant during the growth process. The junction between the two semiconductors forms an axial n/p junction. It will be appreciated that the order of the n and p semiconductors in this nanowire can vary, with the p or n type material on top and the opposite semiconductor on the bottom.

This axial type junction is particularly useful when the solar cell has a graphene top contact layer, as set forth herein. It is also noted that a radial shell is not required where an axial p/n junction is present.

Therefore, in a further aspect, the present invention provides a composition of matter, in particular a photovoltaic cell comprising: at least one nanowire on a graphite substrate, the at least one nanowire has been rendered Crystal growth on the substrate, wherein the nanowire comprises: a bottom portion comprising at least one III-V compound or at least one II-VI compound or at least one Group IV element, the bottom portion having been doped to form An n-type or p-type semiconductor; and an upper portion comprising at least one III-V compound or at least one II-VI compound or at least one group IV element, the upper portion having been doped such that the upper portion is formed The semiconductor of the bottom portion is opposite to one of the n-type semiconductors or the p-type semiconductors.

The nature of the dopants and materials used to form the nanowires is the same as above. Preferably, both the top portion and the bottom portion of the nanowire are formed of the same compound (eg, a compound of the III-V group such as GaAs).

The junction is preferably placed about half of the nanowire. The change from n-type conductivity to p-type conductivity or vice versa from p-type conductivity to n-type conductivity can be achieved only by changing the nature of the dopant atoms. Therefore, when the change is desired, the supply of the first dopant element is stopped, and the supply of the second dopant element suitable for providing one of the opposite conductivity is started. This can be easily achieved in the context of the MBE procedure set forth above.

Although it is not necessary to provide such an axial n/p type nanowire having a shell layer, a shell layer may contribute to passivation. This passivation will be used to reduce surface depletion and carrier recombination and thereby increase solar cell efficiency.

As noted above, this axial type of junction is preferably used with the same top contact (especially one of the top contacts formed by a graphite substrate). The substrate is preferably transparent because it forms a top layer. A plurality of batteries of this type can be stacked to form a tandem battery, as further defined below. This axial type battery to be used with the same radial core shell battery is also within the scope of the present invention.

Radial shell growth

Then, the grown nanowires are epitaxially grown with a radial shell. Therefore, this forms a core shell type configuration of the nanowire as a whole. The nanowires of the present invention can be applied by conventional methods such as those discussed above for the MBE grown nanowires. cloth. The shell should cover all of the core surface.

The shell material will be formed from one of the Group III-V or II-VI compounds or Group IV elements as described above for the core of the nanowire. Both the core material and the shell material need to act as a semiconductor to produce useful nanowires and thus solar cells. Optimally, in terms of the periodic table, the core material matches the shell material. Therefore, the III-V family nanowire core preferably has a III-V shell layer. The II-VI core can carry the II-VI shell, and so on.

More preferably, the core is identical to at least one of the elements in the shell, preferably the two elements are the same. In one embodiment, the compounds for the core and shell layers are identical and differ only in the nature of the doping profile.

It is desirable to dope the shell material such that it forms one of the p or n junctions opposite the junction formed by the core nanowires. Thus, a p-doped core can be covered by an n-doped shell (or vice versa). Preferably, the core is a p-doped semiconductor and the shell is an n-doped semiconductor. One can be discussed above in relation to the discovery of doping on the core nanowire.

In one embodiment, when the core nanowire is a III-V group nanowire, the shell layer may be a mixed III-V shell layer, that is, including two elements from the group III and An element of the V group, for example, AlGaAs. It will be appreciated that in such ternary (or quaternary) compounds, the amount of Al and Ga combined satisfies the price of As (of course, depending on the doping), but varying amounts of Al and Ga may be present.

Thus, the ternary compound may have the chemical formula XYZ, wherein X is a Group III element, Y is different from X and Z one of Group III or V elements, and Z is a Group V element. X and Y or Y and Z mole in XYZ are preferably from 0.2 to 0.8, that is, the chemical formula is preferably X _x Y _1-x Z (or XY _1-x Z _x ), wherein the subscript x is 0.2 to 0.8. The quaternary system can be represented by the chemical formula A _x B _1-x C _y D _1-y , where A and B are Group III elements and C and D are Group IV elements. Again, the subscripts x and y are typically between 0.2 and 0.8.

A pure (i) undoped layer can also be used between the radial p core and n shell (or vice versa) structures to enhance solar cell performance. This intermediate layer (i) can be doped by continuing growth The shell layer is first formed by growing an undoped radial shell layer.

It is also possible to grow a shell in which a "p-i-n" or "n-i-p" structure is present by using an appropriate doping technique. Thus, first, the shell layer can be p-doped (covering a p-core nanowire) followed by an undoped pure shell layer and an n-doped shell layer (or vice versa).

Thus, in another aspect, the invention provides a composition of matter as defined above, wherein a pure layer (undoped) is located between the core and the shell. Ideally, the nature of the undoped layer will be essentially the same as the core or shell or both, ie if the core nanowire is doped with GaAs, the undoped layer is only undoped GaAs .

The dopants used in the shell are the same as those used in the nanowires and have been discussed above. Whether the core/shell layer forms a p-junction or an n-junction varies with the nature of the dopant, its amount, and the like. Those skilled in the art are familiar with the doping of such semiconductor materials to introduce p-type or n-type conductivity.

Particularly preferably, the shell material is an n-type GaAs shell. The core is preferably a p-type GaAs.

The thickness of the shell layer is about several nanometers, for example, 10 nm to 500 nm. The shell layer is preferably thinner than the core of the nanowire.

External transparent conductive electrode coating

It is possible to form one of the current flows using one of the core layers of the p and n junctions. Of course, it is necessary to provide electrodes to form a battery. The graphite substrate is a conductor and thus provides a bottom electrode. Preferably, the core shell nanowire also has an outer conductive coating designed to act as one of the transparent conductive top contacts. The presence of the top contact and the bottom contact based on the graphite substrate forms a circuit and thus allows current to flow in the cell as the absorbed photons generate free carriers in the core shell nanowire.

The outer coating is preferably transparent. It is preferred to allow photons to penetrate the outer coating and to be absorbed by the semiconductor core or shell material within the nanowire. The outer coating must also be a conductor.

The outer coating is preferably formed of a mixed metal oxide. Preferably, the coating is formed of a transition metal or a mixed metal oxide of one of the (III) or (IV) metals. The transition metal is preferably a Group 10 to Group 12 metal. Ideally, it comes from a first transition system, such as Zn. Preferably, the metal of Group (III) or (IV) is In, Sn, Al or Ge.

Therefore, the coating used in the present invention contains InSnO (Sn-doped InO or ITO) and AlZnO (Al-doped ZnO or AZO).

There is an outer shell to allow for high conductivity while being transparent. In fact, graphene acts as an electrode and the outer coating acts as a second electrode.

The outer coating can be applied using atomic layer deposition or sputtering.

The thickness of the coating is about several nanometers, for example, 10 nm to 100 nm. The outer coating should ideally be conformal and as thin as possible, but here there is a trade-off between transparency (thin layer) and electrical conductivity (thicker layer).

The outer coating will require a substrate that covers not only the nanowire but also the nanowires that are grown thereon. Of course, the graphite substrate forming a bottom contact is unlikely to be in direct contact with the top contact formed by the outer casing. Therefore, it may be desirable to provide an insulating layer on top of the graphite substrate. Conveniently, this can be achieved using a cerium oxide mask as defined above.

The nanowires are designed to cover at least 5% of the surface of the graphite substrate. Ideally, the coverage can be as much as 20% of the graphite surface. Thus, these percentages refer to the surface area below the substrate of the nanowire. These densities allow for a low light reflection and high photon absorption. The photons are absorbed by both the core component and the shell component of the nanowire. Without wishing to be bound by theory, in a p-doped core and an n-doped shell nanowire, it is envisaged that light will be directed from above to the nanowire. Photons are absorbed in the nanowire and produce a free charge. The charge carrier is a negatively charged electron and a positively charged hole. The electron charge moves through the n-shell to the top contact. Thus, in practice, electrons can be envisaged to travel radially in the nanowire to reach the top contact. Since the outer coating acts as an electrode, the electrons only have to pass a very short distance to the electrode, that is, the electron has to travel through only a few tens of nm of the n-type shell before being connected to a conductor. touch. The positive charge (hole) passes down the nanowire to the other bottom contact (graphite substrate) substrate layer, and the charge passes very rapidly down through the nanowire to the contact.

The nature of the top contact design can depend on the system. If a problem with the surface state occurs, it may be important to have a passivation layer on the outside of the radial semiconductor shell, rather than having only the top contact in direct contact with the semiconductor shell at the top portion of the nanowire. The radial passivation layer may be undoped (pure) epitaxial window layer by chemical passivation (eg, using an ammonium sulfide solution) or by overgrowing the doped nanowire shell layer (eg, one Introduced as an AlGaAs window layer of one of the GaAs nanowire shell layers. The nanowire can then be embedded in a transparent insulator (eg, benzocyclobutene resin (BCB)), after which a transparent conductive top contact (eg, ITO or AZO) is formed to adhere to the tip of the nanowire. Conductive part. One discussion of the passivation of GaAs nanowires can be found in Maria Let et al. (2011, 11, 2490-2494).

Having such a short distance for electron travel means that the electron collection time can be shorter than the electron heating time, and thus, the battery of the present invention can be extremely efficient. Efficiency above 34% is possible.

It is also possible to supply an external coating contact by providing a further metal top contact on the battery. The metal top contact is preferably a metal or alloy of gold or a typical electrode type metal such as Pt, Pd, Ti, Ge, and Au.

In this way, the top contact is formed by an outer coating that is also in contact with the metal top contact. The charge can quickly pass down through the conductive outer coating to the top contact.

It will be appreciated that the photons absorbed by a particular core shell nanowire will depend on the band gap of the material in question. Bandgap usually refers to the energy difference (in electron volts) between the top of the cost band and the bottom of the conductive strip. This is equivalent to transporting the top of an electron from the valence band to the bottom of the conductive strip to make the electrons become the energy required to move one of the mobile charge carriers within the semiconductor material. The bandgap system therefore determines that photons are one of the primary factors required to form free carriers in the semiconductor.

Photons with energy less than the band gap will not form any free load in the semiconductor Streams, and therefore do not absorb any light. The free carriers that have been formed by photons larger than the band gap will release a portion of their energy (equal to the difference between the photon energy and the band gap energy) for heating. Therefore, the efficiency of a solar cell depends greatly on the band gap of the material.

Materials having different band gaps can be produced by manipulating the chemical composition of the semiconductor material in the core and shell nanowires.

Stacked battery/series battery

In order to maximize the effectiveness of a solar cell, it is important to absorb as much photon as possible. The nature of the photons that a particular battery will absorb and how much power the battery can produce is largely determined by the bandgap. The size of the band gap varies with the core layer and the shell layer and can therefore vary depending on the nature of the material used. Accordingly, the inventors contemplate that a plurality of different cells as defined above can be used to form a solar cell that absorbs photons that span one width of the wavelength. By providing batteries with different band gaps, each cell will absorb photons from a portion of the solar spectrum that is different from the solar spectra of the other cells. This maximizes the performance of the solar cell because it allows for less heat loss and absorbs a wider spectrum of photons. Combining a plurality of such different batteries should enable the formation of a highly efficient solar cell.

Thus, in another aspect, the present invention provides a solar cell comprising at least two cells having different band gaps as defined above. Such batteries are referred to herein as series connected batteries.

The batteries should absorb light of different wavelengths from each other, for example, blue light and red light.

There are no specific restrictions on the configuration of the battery within a device. However, it is envisaged that the batteries can be stacked on top of one another precisely. Nanowire growth programs often produce nanowires of the same length. Therefore, the top surface of a battery is generally flat. Therefore, the bottom of one of the upper batteries can be located on the top of the battery below. Therefore, it is important that the bottom contact of the top cell is transparent to allow photons to penetrate below the solar cell. There should also be an insulator (or air gap) between the stacked cells.

Thus, in one embodiment, a top cell can absorb blue photons. a bit The battery absorbs red photons. The nature of the absorbed photons is determined by the band gap. It is preferred to have a lower bandgap material in the bottom cell in a stack. The stacking order from bottom to top preferably reflects the lowest to highest band gap.

The nanowires in the stacked battery do not need to be aligned.

Of course, there is no reason to limit solar cells to visible light. For example, the GaSb nanowire has a lower band gap and will absorb IR photons.

Preferably, in use, the nanowires are oriented in a solar cell parallel to the direction of the sunlight. Thus, the light passes primarily down the length of the nanowire and does not radially span the nanowire. The use of a light collector such as one for focusing light onto one of the cells of the battery can be an option, as is done in concentrated photovoltaic (CPV) applications.

Each cell can be from 1 micron to 2 microns long, so a tandem cell can be from 2 microns to 4 microns and a triple cell can be from 3 microns to 6 microns in height.

It is also possible to use a battery of the present invention in combination with other designs of solar cells, such as a conventional thin film p-n junction cell. In particular, by using graphene as a common intermediate (conductive and transparent) layer, a pair is made without stacking (ideally, based on a first low bandgap cell and a second high bandgap cell) It is also possible to connect the batteries in series, in which the two active cells are connected in parallel or in series.

Short circuit current (open circuit voltage) can be independently added from each battery by having two cells connected in parallel (series) and a common intermediate graphene layer. In a parallel configuration, the following will also be possible: "break" the connection between the top and bottom contacts, and operate the upper and lower batteries independently at different voltages across each cell, but There is still a common intermediate layer as a common contact. In this case, there is no insulating layer (or air gap) between the two cells.

This is particularly advantageous for battery cells that are connected in parallel, because a high solar energy can be achieved without requiring current matching when two cells are connected in series (as in a conventional multi-junction battery). Battery efficiency.

The first cell (low band gap) may be a conventional thin film pn junction cell having a transferred graphene on top, which serves as both a common intermediate layer (ie, a top electrode) and also serves as a growth top A substrate of a rice noodle core shell solar cell (second cell).

Therefore, in another aspect, the present invention provides a composition of matter, in particular a tandem photovoltaic cell comprising: (A) at least one core semiconductor nanowire on a graphite substrate, the At least one core nanowire has been epitaxially grown on the substrate, wherein the nanowire comprises at least one III-V compound or at least one II-VI compound or at least one Group IV element; a semiconductor shell surrounding The core nanowire, the shell layer comprising at least one group III-V compound or at least one group II-VI compound or at least one group IV element such that the core nanowire and the shell layer form an n-type semiconductor and a a p-type semiconductor, or vice versa; and an outer conductive coating surrounding the shell, the outer conductive coating forming an electrode contact; and (B) a thin film pn junction cell having a bottom electrode and a top electrode; wherein the graphite substrate acts as both the top electrode of the thin film battery and also serves as the substrate for the growth of the nanowires.

Therefore, ideally, the graphite layer forms one of the transparent substrates for nanowire growth while serving as one of the electrodes of the thin film junction cell.

It will be appreciated that this tandem battery can then additionally include a further stacked battery on top, and so on. Thus, one of the batteries of the present invention can be stacked on the top layer of the tandem cell to provide a triple cell structure. If desired, a dielectric layer or air gap can be used between the stacked battery and the series battery.

Graphite top layer

In a further possible embodiment of the invention, the battery can be provided with a graphite top layer. A graphite layer can be placed on the formed radial p/n junction core shell and coated nanowires Or on the top of the axial p/n junction nanowire. Obviously, this forms a top contact with the nanowire. Preferably, the graphite top layer is substantially parallel to the substrate layer. It will also be appreciated that the area of the graphite layer need not be the same as the area of the substrate. Several graphite layers may be required to form a top layer.

The graphite layers used may be the same as those of the graphite layers detailed above with respect to the substrate. The top layer is graphite, and more particularly, it is graphene.

Preferably, the thickness of the top layer is 20 nm or less. Even more preferably, the graphite top contact may have a thickness of 5 nm or less.

The application of the top contact to the formed nanowire can be achieved by any suitable method. A method similar to the previously mentioned methods for transferring a graphite layer to a substrate carrier can be used. Graphite layers from condensed graphite, highly oriented pyrolytic graphite (HOPG) or CVD can be spalled by mechanical or chemical means. It can then be transferred to an etching solution such as HF or an acidic solution to remove Cu(Ni, Pt) (especially for CVD-grown graphite layers) and any contaminants from the spalling process. The etching solution can be further changed to another solution such as deionized water to clean the graphite layer. The graphite layer can then be transferred to the formed nanowire as a top contact. Again, an electron beam resist or photoresist can be used to support the thin graphite layer during the spalling and transfer process, which can be removed after deposition.

Preferably, the graphite layer is completely dried after etching and cleaning, after which it is transferred to the top of the array of nanowires. To enhance the contact between the graphite layer and the nanowire, a humidity pressure and heat can be applied during this "dry" transfer.

Alternatively, the graphite layer can be transferred to a top of the array of nanowires along with a solution (eg, deionized water). As the solution dries, the graphite layer naturally forms into close contact with one of the underlying nanowires. In this "wet" transfer method, the surface tension of the solution during the drying process can bend or destroy the array of nanowires. To prevent this in the case of using this wet method, a more robust nanowire is preferred. A nanowire having a diameter of >200 nm may be suitable. Alternatively, a patterned apertured substrate supporting a vertical nanowire structure can be used. Critical point drying techniques can also be used to avoid any damage caused by surface tension during the drying process.

If there is a water droplet on a nanowire array and the attempt to remove the water droplet involves, for example, a nitrogen blow, the water droplet will become smaller and smaller by evaporation, but the water droplet will always try due to surface tension. Keep a spherical form. This can damage or destroy the nanostructure surrounding the water droplets or inside the water droplets.

Critical point drying avoids this problem. By increasing the temperature and pressure, the phase boundary between the liquid and the gas can be removed and the water can be easily removed.

The top contact graphite layer is preferably transparent, electrically conductive and flexible. To enhance the electrical and mechanical contact of the graphite layer with the metal particles on top of the further grown nanowires, an annealing procedure can be used. After depositing the graphite top contact, the sample can be annealed in an inert atmosphere (eg, argon) or vacuum. The temperature can be as much as 600 ° C. The annealing time can be as much as 10 min.

Doping of the top contact of the graphite can also be utilized. The main carriers of the graphite top contact can be controlled to be holes or electrons by doping. It is preferred to have the same doping type in the graphite top contact and in the semiconducting nanowire. For example, a core shell nanowire having p-doping in the shell layer should match the p-doping of the top graphite layer. One of the axial p/n junction nanowires having p-doping at the upper portion of the nanowire should match the p-doping of the top graphite layer. To enhance the conductivity of the top contact of the graphite, metal nanostructures (such as nanowires and nanoparticles) having a high electrical conductivity (>10 ³ S/cm) may (particularly) be partially interconnected (eg This way, an Ag nanowire/graphene mixed top contact) is dispersed on top.

application

The nanowire of the present invention can be used in the manufacture of a solar cell. This solar cell has the potential to be both efficient, inexpensive, and flexible.

The invention will now be further discussed with respect to the following non-limiting examples and figures.

Claims (28)

A composition of matter, in particular a photovoltaic cell comprising: at least one core semiconductor nanowire on a graphite substrate, the at least one core nanowire has been epitaxially grown on the substrate, wherein the nano The rice noodle comprises at least one III-V compound or at least one II-VI compound or at least one Group IV element; a semiconductor shell surrounding the core nanowire, the shell comprising at least one III-V compound or At least one Group II-VI compound or at least one Group IV element such that the core nanowire and the shell layer form an n-type semiconductor and a p-type semiconductor, respectively, or vice versa; and an external conductive coating surrounds The shell layer, the outer conductive coating forms an electrode contact. The composition of claim 1, wherein the nanowire is grown in the [111] or [0001] direction. The composition of claim 1 or 2, wherein the shell layer and the core nanowire independently comprise a III-V compound. The composition of claim 1 or 2, wherein the nanowires comprise AlAs, ZnO, GaSb, GaP, GaN, GaAs, InP, InN, InAs, InGaAs or AlGaAs. The composition of claim 1 or 2, wherein the graphite substrate and/or the graphite layer comprises graphene, graphane or graphene oxide, preferably wherein the graphene, the graphane or the graphene oxide Includes 10 or fewer layers. The composition of claim 1 or 2, wherein the graphite substrate and/or the graphite layer is on a metal film or foil of a condensed graphite, a highly oriented pyrolytic graphite (HOPG), such as Ni, Cu or Pt. One of the CVD-grown graphene layer peels off the laminated substrate. The composition of claim 1 or 2, wherein the graphite substrate and/or the graphite layer are flexible And transparent. The composition of claim 1 or 2, wherein the graphite substrate is doped with the same doping carriers as the contacted nanowires. The composition of claim 1 or 2, wherein the graphite substrate is adsorbed by an organic or inorganic molecule such as a metal chloride (FeCl ₃ , AuCl ₃ or GaCl ₃ ), NO ₂ , HNO ₃ , an aromatic molecule or ammonia. Doping. The composition of claim 1 or 2, wherein the surface of the graphite substrate is doped during its growth by substituting one of the dopants such as B, N, S or Si for the doping method. The composition of claim 1 or 2, wherein the surface of the graphite substrate has a nanostructure having a high electrical conductivity (>10 ³ S/cm) dispersed thereon, such as a nanowire or a nanoparticle. The composition of claim 1 or 2, wherein the nanowire has a diameter of no greater than 500 nm and a length of up to 8 microns (such as up to 5 microns). The composition of claim 1 or 2, wherein the substrate comprises a plurality of nanowires, wherein the nanowires are substantially parallel. The composition of claim 1 or 2, wherein the nanowires are grown in the presence of a catalyst. The composition of claim 1 or 2, wherein the outer coating is a mixed metal oxide such as AlZnO (AZO) and InSnO (ITO) having a high electrical conductivity and transparency and/or a further graphite layer. The composition of claim 1 or 2, wherein the core is a p-type semiconductor and the shell is an n-type semiconductor. A composition according to claim 1 or 2, wherein an undoped (pure) layer is present between the core layer and the shell layer. The composition of claim 1 or 2, wherein a graphite layer is used as the nanowire formed Top contact. A method for producing a battery according to any one of claims 1 to 17, comprising: (I) supplying a group II-VI element or a group III-V element or a group IV element to the graphite substrate preferably via a molecular beam a surface; (II) epitaxially growing at least one nanowire from the surface of the graphite substrate to provide a nanowire core; (III) coating the at least one nanowire core to include at least one III-V compound or a shell layer of at least one II-VI compound or at least one group IV element such that the core nanowire and the shell layer form an n/p junction or a p/n junction, respectively; and (IV) The shell coating surrounds an outer conductive coating of one of the shell layers, the outer conductive coating forming an electrode contact. The method of claim 19, wherein in step (I), a catalyst is deposited on the substrate prior to supplying the reactants to the substrate. The method of claim 19 or 20, wherein in step (I), the substrate is coated with a patterned apertured mask prior to supplying the reactants to the substrate. A solar cell comprising the battery of claims 1 to 17. A solar cell comprising a plurality of photovoltaic cells according to claims 1 to 17, preferably stacked vertically above each other. A solar cell comprising a plurality of photovoltaic cells according to claims 1 to 17, wherein at least two of the photovoltaic cells have different band gaps. A composition of matter, in particular a photovoltaic cell comprising: at least one nanowire on a graphite substrate, the at least one nanowire has been epitaxially grown on the substrate, wherein the nanowire comprises a bottom portion comprising at least one III-V compound or at least one II-VI compound or at least one Group IV element, the bottom portion having been doped to form an n-type or p-type semiconductor; and an upper portion, It comprises at least one III-V compound or at least one II-VI a compound or at least one group IV element, the upper portion having been doped such that the upper portion forms an n-type semiconductor or a p-type semiconductor opposite the semiconductor of the bottom portion. The composition of claim 25, wherein a graphite layer is used as the top contact of the formed nanowires. A composition of matter, in particular a photovoltaic cell comprising: (A) at least one core semiconductor nanowire on a graphite substrate, the at least one core nanowire has been epitaxially grown on the substrate, Wherein the nanowire comprises at least one III-V compound or at least one II-VI compound or at least one Group IV element; a semiconductor shell surrounding the core nanowire, the shell comprising at least one III-V a compound or at least one Group II-VI compound or at least one Group IV element such that the core nanowire and the shell layer form an n-type semiconductor and a p-type semiconductor, respectively, or vice versa; and an external conductive coating Surrounding the shell layer, the outer conductive coating forms an electrode contact; and (B) a thin film pn junction cell having a bottom electrode and a top electrode; wherein the graphite substrate serves as both the thin film battery The top electrode also serves as the substrate for the growth of the nanowires. The composition of matter of claim 27, further comprising a photovoltaic cell, such as one of the claims, stacked thereon, preferably separated from the electrode contact via a dielectric layer or air gap.