TW200409130A - An option fuse circuit using standard CMOS manufacturing process - Google Patents

Abstract

An option fuse circuit using standard CMOS manufacturing process. The option fuse circuit contains a latch for latching signals, which includes a first endpoint and a second endpoint. The option fuse circuit also contains a comparator, which includes two input nodes and an output node. The comparator is inputted at the two input nodes with signals from the first and the second endpoints, and compares the two signals in order to output a comparison signal. The option fuse circuit further contains two logic cells for storing non-volatile data. The logic cell includes a word line end and a bit line end. The word line ends are electrically connected to the output end of the comparator, while the bit line ends are electrically connected to the first and the second endpoints, respectively.

Description

200409130

Technical Field to which the Invention belongs The present invention provides a selective melting and filling type metal oxide layer semiconductor manufacturing process: selective melting; a standard mutual prior art is currently available on the market + -0M * D: A: '; ^ sr-) ^ Features. _ $ 情 体 巾 ~ f Any digital data store that stores volatile and non-volatile data ^ Remember ^ single ^ is used to store a bit " ⑴ △ 枓, and the number of memory cells is Generally, an array cannot reach the average semiconductor process. Since the yield rate (Y 1 e 1 d) will usually be one hundred percent, so in the manufacturing process of integrated circuits, it can be expected to produce a predetermined ratio. The production of defective products is also in the process of the integrated circuit from the lack of manufacturing. The steps of product testing are very important and cannot be performed. Only through the process of product testing can the semiconductor process be eliminated due to good results. ^ Incomplete or unusable products are screened out and produced, so that we can ensure that customers receive normal shipping products at the time of shipment. It can be seen that product testing is very important in the semiconductor manufacturing process.

200409130 V. Description of the invention (2) One of the important processes. Because the memory contains a very large amount of memory units (the current memory capacity is mostly tens to hundreds of megabytes (Mbyte), such as 64M, 1 28M, etc.), so it is counted as such Of the many memory units, at least one memory unit will have a high probability of failure, and if only one memory unit fails in a memory, the memory will be regarded as defective and cause its failure. Unusable, this will cause great trouble for memory manufacturers. Therefore, in the design of general memory, a group of spare memory cells (Redundancy Cell) is usually added in addition to the original memory cell array, and a special circuit configuration design is used to control and select the group. The connection between the spare memory unit and the memory unit array. With this design, when a memory unit at a certain position in the memory unit array is found to be faulty during the product testing process, the special circuit group can be used to control the group of spare memory units. To replace the original function of the faulty memory unit, so that the memory is not scrapped due to the failure of a small number of parts, thus saving a lot of costs. This special circuit configuration is generally called Option Fuse Circuit. Please refer to FIG. 1. FIG. 1 shows a schematic view of a conventional selection fuse circuit 10. The selective fuse circuit 10 includes a P-type metal oxide semiconductor transistor 1 2. A P-type metal oxide semiconductor transistor 1 4. An N-type metal oxide semiconductor transistor 16 and a selective fuse 18. Transistor 1 4 and Transistor

Page 7 200409130 V. Description of the invention (3) The body 16 is electrically connected to each other to form an inverter. The two gates are connected to each other and the input terminal of the inverter is connected to the two non-polar terminals to be the inverter. Output. The drain of transistor 12 and one of the selection fuses 18 are electrically connected to the input of the inverter, and the gate of transistor 12 is electrically connected to the output of the inverter, and the output That is, the output terminal Vout is one of the selection fuse circuits 10. Finally, the sources of the transistors 12, 14 are electrically connected to a system voltage Vdd, while the source of the transistor 16 and the other end of the selection fuse 18 are electrically connected to the ground voltage Vs s. Please refer to FIG. 2A and FIG. 2B. FIG. 2A shows a schematic diagram of the layout of selecting the dissolving silk 18 in FIG. 1. Generally, the fuse 18 is selected by using metal (Meta 1) line segments or polycrystalline silicon (p 〇1 y) line layout, and the selection fuse 18 can be used for point blowout according to the needs of the laser during the product testing stage. As shown in FIG. 2B, because the selection fuse circuit 10 is different from the output value of the output terminal Vout when the selection fuse 18 is not yet blown and when it is blown (the selection fuse circuit shown in FIG. 1) 10 as an example, when the selection fuse 18 has not been blown, Vout outputs a signal π 1π, that is, a high potential, and when the selection fuse 18 is blown, Vout outputs a signal π 01 ', that is, a low potential), Then, in the circuit design of a memory, the output signal values of the plurality of selection fuse circuits 10 can be used to encode and determine the combination of the spare memory cells to replace the failed memory cells in the memory cell array. However, since fuses 18 are selected for layout, usually sufficient space must be reserved in a certain area around them (as shown in Figure 2A and Figure 2B, reserved

Page 8 200409130 V. Description of the invention (4) A 5 / z mx 5 / zm piece and a lightning circuit to reserve a rotten rice, thereby destroying the phenomenon of an increase in memory memory capacity and a silk circuit 1 0 Represents that a component is contaminated. Relatively, it is relatively long. • For a large number of working hours, it ’s a long and time-consuming space. However, if you choose this piece, you can choose the process wire that has been left open for a long time, and the process wire 18 has also been greatly increased. The laser wire 18 is used for laser burnout and the fuse 18 is selected. An open product will cause the number of components to be 10, because it is low. The circuit of the week is clear. In addition, it is burned on the line, so that on the one hand, the water vapor that destroys the surrounding hollowed out surface may penetrate the guilty degree when the action of the test process is interrupted. In the selected melted memory, each of the lasers must be burned because of the laser burnout, which also caused the test: the circuit technology is due to the use of electrical burnout technology (FI h ii know the drive technology also uses non-volatile flash Flash Mem on memory ory) Cooperate with suitable circuit design to achieve the same goal X ^ And because the flash memory cannot use the method compatible with the standard complementary metal oxidation: 彳 conductor process ... Must have multiple layers of polysilicate silicon layer in the process (Poly Silic 〇n), thus increasing manufacturing costs. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a selective fuse circuit using a standard complementary metal oxide semiconductor process, using only one polycrystalline silicon layer in the process, and without using laser blowout technology, so as to solve the above-mentioned reliability.

200409130 V. Description of the invention (5) The problem of reduced degree, lengthy test time and increased manufacturing cost. According to the patent application scope of the present invention, a selective fuse circuit is disclosed. The selective fuse circuit is manufactured using standard complementary metal oxide semiconductor process technology. The selective fuse circuit includes a latch including a first terminal and a A second terminal for latching the signals of the first and second terminals; a comparator including two input terminals and an output terminal, the two input terminals are electrically connected to the first and second terminals respectively The comparator is used to input the signals of the first and second endpoints respectively at the two input terminals and compare the two signals to output a comparison signal at the output terminal; a first logic unit is used to store a Non-volatile data, the first logic unit includes a first word line terminal and a first bit line terminal, the first word line terminal is electrically connected to the output terminal of the comparator to input the comparison signal, The first bit line terminal is electrically connected to the first terminal; and a second logic unit for storing a non-volatile data, the second logic unit includes a second word line terminal and a first Two bit line end, the first The two-character line terminal is electrically connected to the output terminal of the comparator to input the comparison signal, and the second bit line terminal is electrically connected to the second terminal. The selective fuse circuit of the present invention uses a standard complementary metal Oxide layer semiconductor manufacturing technology, so it is very suitable for general memory process, only one layer of polycrystalline silicon layer is needed in the process, so it can avoid the problem that the conventional technology increases the manufacturing cost due to the use of flash memory, and the choice of the present invention The fuse circuit uses two logic units to store non-volatile data to replace the habit

Page 10 200409130 V. Description of the invention (6) In the known technology, the method of determining the output signal value according to the state of a selected fuse is used, so the aforementioned reliability reduction and test time for using the laser blowout technology will not occur. Too long a problem. Embodiment 1 Please refer to FIG. 3, which shows the intention of the selective fuse circuit 20 of the present invention. The selection fuse circuit 20 includes a latch 22, which includes a first terminal N and a second terminal ZN for latching the signals of the first and second terminals N and ZN. A comparator (c0mparat〇r) 24, which includes two input terminals and an output terminal, the two input terminals are electrically connected to the first and second terminals N, ZN, respectively. The comparator 24 is used for the The second input knows not to input the signals of the first and the first one, point ^, ZN, and compare the two signals to output a comparison signal WL at the output terminal;-the first logic cell (Logic Cell) 26 'is used to store a Non-volatile data. The first logic unit 26 includes a first word line terminal WL1 and a first bit line terminal BL1. The first word line terminal WL1 is electrically connected to the comparison. The output terminal of the device 24 receives the comparison signal WL, and the first bit line terminal BL1 is electrically connected to the first terminal N; and a second logic unit 28 is used to store a non-volatile data. The second logic The unit 28 includes a second word line terminal WL2 and a second bit line terminal BL2. The second word line terminal WL2 is electrically connected to the output of the comparator 24. The input end of the comparison signal WL, while the second end of the bit line BL2 is electrically connected to the second terminal ZN. Please note that the latch 22 is usually connected with two inverters in opposite phases, as shown in FIG. 3. Next will

Page 11 200409130 V. Description of the invention (7) The operation principle of the selection fuse circuit 20 will be described in detail using a preferred embodiment of the present invention. Please refer to FIG. 4 and FIG. 5. FIG. 4 shows a schematic diagram of the selection fuse circuit 30 as an embodiment of the present invention. The connection between the components is the same as the selection fuse circuit 20, so there is no need to repeat the description. . As shown in FIG. 4, the selective fuse circuit 30 includes a latch 32, in which a P-type metal oxide semiconductor transistor 42 and an N-type metal oxide semiconductor transistor 46 constitute an inverter, and A P-type metal oxide semiconductor transistor 44 and an N-type metal oxide semiconductor transistor 48 form another inverter. The two inverters are connected to each other in opposite directions and the two output terminals are used as the first and second terminals. Points N, ZN. The selection fuse circuit 30 also includes a comparator 34. As shown in FIG. 4, the comparator 34 uses a plurality of logic gates to compare the signals input from the first and second terminals N and ZN to generate a signal at its output. Compare signal ZWL. The comparator 34 also includes a mode selection input terminal ZPGM, which is used to determine whether the fuse circuit 30 is in the write mode (Program Mode) or in the read mode; —the data write input terminal DB, It is used to input the data to be written when the fuse circuit 30 is in the write mode. The selection fuse circuit 30 also includes a first logic unit 36 and a second logic unit 38, which are the same as the selection fuse circuit 20 shown in FIG. 3. The logic units 36, 38 are used to store non-volatile For volatile data, its word line terminal is electrically connected to the output terminal of the comparator 34 to input the comparison signal ZWL, and its bit line terminal is electrically connected to the first and second terminals N, ZN, respectively. In this embodiment,

Page 12 200409130 V. Description of the invention (8) The first logic early element 36 and the second logic element 38 use one-time programmable cell 40 (One-Time Programmable Cell) as shown in FIG. The single-time programmable logic unit 40 includes a first transistor 52 and a second transistor 5 4 ′. The first and second transistors 5 2 and 5 4 are P-type metal oxide semiconductor transistors. The source of the transistor 52 is electrically connected to a power supply voltage Vcc, and the gate of the first transistor 52 is used as the word line terminal of the logic cells 36, 38 (connected to the comparison signal ZWL in FIG. 5) 'The drain of the first transistor 5 2 is electrically connected to the source of the second transistor 54, and the word line terminal marked BL in the second transistor 5 4 and the floating gate can be programmed once. The poles between the crystals 54 serve as logic.) The one-time bit line terminal stores the stored logic logic unit, and the second line terminal (Figure 5 uses the change of the transistor 54 to store it in

Floating) This bit editing unit 40 of 8 is to change the second and then achieve the purpose. Pole floating (series unit 3, 6. Programmable logic wheel input signal value of the number of charge data in 40 and the Luo Luo second electric power ^ 30, and also contains an initial module, electrically connected to the first-poor Die, Luo = -36, 38, used to write data to the first ancient, early Fan 36, 38 in the write mode. As shown in Figure 4, the initial module includes a transistor 56 and a second initial power Crystal 58, the first and the first generation of the eighth, you are N-type metal oxide semiconductor transistor, to make waves, and to recognize the bit line of the brother and the second logic unit 36, 38 Wu q "2 4 people > The power supply is connected to a ground voltage Vss (0V), and the comparator 34 also contains two-phase 乂 brothers, φ, *, and the initial output terminals BLO, ZBL0 of opposite phases are not singed. The gates of transistors 5 6 and 5 8 are used to control

Page 13 200409130 V. Description of the invention (9) The first and second initial transistors 56 and 58 are turned on to write the data into the first and second logic units 36 and 38. Next, the selection fuse circuit 30 of this embodiment will be used to describe its operation in the write mode and the read mode in detail.

In the process of product testing, if the tester finds that some specific memory cells in a memory cell array of a memory have failed, the tester will write to a plurality of selection fuse circuits in the memory The replacement action is to select a plurality of spare memory cells previously placed in the memory to replace the faulty memory cells. Here, one of the plurality of selection fuse circuits will be taken as an example, and the use of Select the fuse circuit 30 to perform the operation principle of its write mode.

When the fuse circuit 30 is selected for data writing, the mode selection input terminal ZPGM will input a low voltage (0V) (that is, the selection fuse circuit 30 is in the write mode), and input it to the data write input DB. If you want to write the data of the first and second logic units 36, 38, it is assumed here that the data is "0 π, then the initial output terminal BL0 will output a low voltage, and the initial output terminal ZBL0 will output a high voltage, so it will cause The first initial transistor 5 6 and the second initial transistor 5 8 are in a path state and an open state, respectively, further making the first and second terminals N and ZN a low voltage and a high voltage, respectively, and due to the mode selection input terminal ZPGM The low voltage makes the comparison signal ZWL a low voltage. The first and second logic cells will turn on the first transistor 5 2 because of the low voltage input to the word line end, so the gate of the second transistor will be turned on. Electricity stored in the pole

Page 14. Description of the invention (10) ____ Step The number of charges will be changed according to the bit line end of the first and second logic cells 36 and the value, and will be added to

Program State, its second electric heliostat is in the write state erasing state (Erase State, the $ gate is charged with an electronic charge), and the data is stored in the first, the first one-the gate of the crystal is not loaded Have. By the same principle, if the units 36, 38 logic units 36, 38 in turn will be on ice ^… 1 respectively, the first and second materials are stored in the first and second logic units 6, and the writing state is One of the actions that writes information that has passed product testing into the memory—electronic products. When used, the memory will take one of the plurality of spare circuits which can normally replace the memory as one of the circuits that can be used correctly. For example, the operation mode of its read mode is equal to ί ί two of its multiple choices. The 1-wire circuit of the library has been installed. It will be installed on a certain electronic product. The power supply of the electronic product will be restored. Select the dissolving circuit to read the operation. The function of the faulty memory unit makes the ground operate. Here, the plurality of selection fuses will be explained using the selection fuse circuit 30 in FIG. ΪFuse circuit 3 〇 When data is to be read, the mode selection input is in reading 'two high voltages (Vcc) (that is, the selection of the fuse circuit is 30 volts, the guide type) is the initial output terminals BL0 and ZBL. Both will output a low-power surname, Ming Ming Huidi, and the second initial transistor 56, 58 are in an open circuit state. π 月 茶 read Figure 6, same as _π-Figure 6 shows the signal value changes with time in Figure 4

200409130

V. Description of the invention (ll) At this time, when the power is turned on, the figure 丄 will increase with time until it reaches a place. The action of the power supply voltage Vcc 30 can be divided into data induction and mixing, and the solution is selected according to the selection. The above-mentioned selection operation of the fuse circuit 30 is a stage of writing. Please note that the data stored in elements 36, 38 must be the first and second logical singles, 2 = 6 states, and the second logical unit 38 must be edited. The element 36 is in the second logical position: When the terminal N power supply voltage value is different, the high voltage is as shown in Figure 3. The signal of the transistor h induction selection fuse circuit 30 is in the data sensing stage. The voltage value of k ZN will follow the power supply voltage and the second applied voltage VCC. The value has not yet reached the first increase, because: the first and second logical units 36, 38 = point N: with J :: the first and second endpoints N, ZN ~ 冋 and With plus mode selection input ZPGM system is-ancient φI s R is

The plurality of logic gates in the comparator 34 of Twf: make 5 f pass = WL is a low voltage, the first and second logic 'day make ratio to maintain the path state, so the first and the first two H, w38 Out of the data stored in the first and second logic units 36 and 38, 2 the current value is different due to the voltage value of the power supply for ZN. For example, the second emperor chooses Xuansi circuit 30 and enters the data latch stage. When the value of the f-stem Vcc has reached the state where the first and second endpoints N, a logic unit 36, 38 are different, the voltage values of the first and second endpoints N, ZN will appear. 200409130 V. Description of the invention (12) Figure 6 (shown in Figure 6 is when the first logic unit 36 is in the writing state and the second logic unit 38 is in the erasing state). The function of the plurality of logic gates in the comparator 34 will change the comparison signal ZWL to a high voltage as shown in FIG. 6 to cause the first transistors of the first and second logic units 36 and 38 to be turned off. One and the second endpoints N, ZN will stop the action of sensing the data, and will use the data according to the results of their sensing. The latch in the latch 32 (shown in FIG six, N is a first high voltage terminal, a second terminal to a low voltage ZN), so the read operation is completed. In addition, the comparator 34 of the selection fuse circuit 30 also includes a signal output terminal Vout for outputting the signal latched by the latch 32. In this embodiment, since the first terminal N is a high voltage Through the function of a plurality of logic gates in the comparator 34, the signal output terminal Vout will output a low voltage, that is, the logic value is shown in FIG. 7 and FIG. 8. FIG. 7 shows a selective fuse as another embodiment of the present invention. A schematic diagram of the silk circuit 60. The selection fuse circuit 60 includes a latch 62, a comparator 64, a first logic unit 66, and a second logic unit 68. FIG. Schematic diagram of the single-time programmable logic unit 70 used by the first and second logic units 66, 68. The single-time programmable logic unit 70 includes a first transistor 82 and a second transistor. 8 4 and transistors 8 2 and 8 4 are N-type metal oxide semiconductor transistors. The connection between the various components is very similar to the fuse circuit 30 and the single programmable logic unit 40. No need to repeat the details. However, the interconnections of the plurality of logic gates in the comparator 64 are compared with

Page 17 200409130 V. Description of the invention (13) The device 34 is different, and the source selection fuse circuit 60 of the second logic unit 66 and a transistor 8 2 is very compatible with the fuse circuit 30. That is, the circuit 60 also includes a 8 8 whose connection and operation and the second initial transistor transistor 8 6 and 8 8 are both poles electrically connected to a circuit compared to the conventional circuit system using a latch to write When entering the mode, the data in the initial mode is turned on when the power is turned on, and the bypass technology is generated. Due to the selection of the semiconductor process technology layer of the present invention, the problem of the book can also be avoided. The above is only that the comparator 64 series outputs a comparison signal W1JL first and 68, and the series of the single-time programmable logic unit 70 is electrically connected to a ground voltage VSS (ov). In addition, the operations in the writing mode and the item taking mode are also similar to those in the selection mode. Therefore, it is known that the above-mentioned operation on the selection melting circuit 30 has the same result. In addition, the method of selecting the first initial transistor 86 and the second initial transistor in FIG. 7 is very similar to the first 5 6 and 5 8 of the selective flash circuit 30 in FIG. 4, but the first and The second initial P-type metal oxide semiconductor transistor has a high voltage source (here, Vcc). Selective fuse circuit technology. The selectable fuse, a comparator, and two logic units of the present invention are used. The initial value is set in the two logic units, and is read. The latch is used to sense and store the two logic units. In this way, the conventional technology is used to avoid the problems of reduced laser reliability and long test time. The fuse circuit is made of a standard complementary metal oxide layer, and only one layer of polycrystalline silicon is needed in the process. Using flash memory to increase manufacturing cost

I

200409130

Page 19 200409130 Brief description of the diagrams Brief description of the diagrams Figure 1 is a schematic diagram of a conventionally selected fuse circuit. Figure 2A is a schematic diagram of the layout of the selective fuse of Figure 1 when it has not been blown. FIG. 2B is a schematic diagram of the layout when the selection fuse of FIG. 1 is blown. FIG. 3 is a schematic diagram of a selective fuse circuit according to the present invention. FIG. 4 is a schematic diagram of an embodiment of the selective fuse circuit of FIG. 3. FIG. 5 is a schematic diagram of the logic unit in FIG. 4. Figure 6 is a schematic diagram of the signal value of Figure 4 as a function of time. FIG. 7 is a schematic diagram of another embodiment of the selective fuse circuit of FIG. 3. FIG. 8 is a schematic diagram of the logic unit in FIG. 7. Symbols shown in the figure 10 '20> 3 (L · 60 Selective fuse circuit 12 ^ 14, 42> 44 P-type metal oxide semiconductor transistor 16 ^ 46, 48 N-type metal oxide semiconductor transistor 18 Select fuse 11, 32 '62 Latcher 24> 3 [64 Comparator 26 ~ 36 ^ 66 First logic unit 28> 38 ^ 68 Second logic unit 40, 70 Single-time programmable logic unit

Page 20 200409130 Brief description of the drawings 5 2, 8 2 First transistor 54, 84 Second transistor 5 6, 8 6 First initial transistor 5 8, 8 8 Second initial transistor Page 21

Claims (1)

200409130 6. Scope of patent application 1. An option fuse circuit, which is manufactured using standard complementary metal oxide semiconductor semiconductor process (Standard CMOS Manufacturing Process) technology. The selective green circuit includes: a latch Latch, which includes a first endpoint and a second endpoint, for latching the signals of the first and second endpoints; a comparator, which includes two inputs and an output Terminal, the two input terminals are electrically connected to the first and second endpoints respectively, and the comparator is used to input the signals of the first and second endpoints respectively at the two input terminals and compare the two signals with The output terminal outputs a comparison signal. A first logic unit (Logic Cel 1) is used to store a non-volatile data. The first logic unit includes a first Word Line terminal and a first bit. A bit line terminal, the first word line terminal is electrically connected to an output terminal of the comparator to input the comparison signal, and the first bit line terminal is electrically connected to the first terminal; and One second logic sheet For storing a non-volatile data, the second logic unit includes a second word line terminal and a second bit line terminal, and the second word line terminal is electrically connected to the output terminal of the comparator to The comparison signal is input, and the second bit line terminal is electrically connected to the second terminal; wherein the data stored in the first logic unit and the data stored in the second logic unit are complementary. 2. The selection fuse circuit described in item 1 of the scope of patent application, which is in a read mode and when the power is turned on, a power supply 200409130 VI. Scope of patent application The voltage will increase with time until reaching a preset value, and the voltage value of the first and second bit line terminals will increase with the power supply voltage. 3. According to the selective fuse circuit described in item 2 of the scope of patent application, if the voltages of the first and second bit line terminals are equal to each other during the increasing process, the comparison signal output by the comparator will cause The first and second logic units are in a Turn-On state, and the first endpoint will sense the data stored by the first logic unit, and the second endpoint will sense the data stored by the second logic unit. Stored data. 4. According to the selection fuse circuit described in item 2 of the scope of patent application, if the voltages of the first and second bit line terminals are different from each other during the increasing process, the comparison signal output by the comparator will be The first and second logic units are placed in a Turn-Off state, and the flash locker will lock the signals of the first and second endpoints. 5. The selective fuse circuit according to item 1 of the scope of patent application, wherein the latch is formed by two inverters connected in antiphase. 6. The selective fuse circuit as described in item 5 of the scope of patent application, wherein the inverter is composed of a P-type metal oxide semiconductor transistor (PM0S Transistor) and an N-type metal oxide semiconductor transistor (NM0S T ransist 〇), the gates of the two transistors are electrically connected to each other as an input terminal of the inverter, and the drains of the two transistors are electrically connected to each other as 200409130 6. Scope of patent application One of the output terminals of this inverter. 7. Select the fuse circuit as described in item 1 of the scope of patent application, wherein the comparator includes a plurality of logic gates (L0gic Gate) for comparing the signals of the first and second endpoints Therefore, the comparison signal is output at the output terminal. 8. The selection fuse circuit described in item 1 of the patent application scope, wherein the comparator further includes a mode selection input terminal for determining whether the selection fuse 'circuit is in a write mode (Program Mode) or in Read mode. 9. The selective fuse circuit as described in item 1 of the patent application scope, wherein the ® comparator further includes a data write input terminal for inputting the first fuse to be written to the first fuse when the selective fuse circuit is in a write mode. And the information of the second logical unit. 10. The selective fuse circuit as described in item 1 of the scope of the patent application, wherein the first and second logic cells are one-time programmable cells (One-Time Programmable Cells). 1 1. The selective fuse circuit as described in item 10 of the scope of patent application, wherein the single-time programmable logic unit includes a first transistor and a second transistor, the source of the first transistor The pole is electrically connected to a power supply voltage, and the gate of the first transistor is used as a word line terminal of the logic unit. The first transistor ~ Page 24, 200409130 VI. The drain of the patent application body is electrically connected to the source of the second transistor, and the intervening electrode of the second transistor is floating. The pole acts as the bit line end of the logic unit. 1 2. The selective fuse circuit as described in item 11 of the scope of patent application, wherein the first and second transistor systems are P-type metal oxide semiconductor transistors, and the source of the first transistor is Connected to a high voltage. 1 3. The selective fuse circuit as described in item 11 of the scope of patent application, wherein the first and second transistor systems are N-type metal oxide semiconductor transistors, and the source of the first transistor is Connected to a ground voltage (0V). 14. The selective fuse circuit as described in item 1 of the scope of patent application, further comprising an initial module electrically connected to the first and second logic units for writing data into the first logic unit in a write mode. One and second logic unit. 15. The selective fuse circuit according to item 14 of the scope of patent application, wherein the initial module includes a first initial transistor and a second initial transistor, and the first and second initial transistor systems are The N-type metal oxide semiconductor transistor has its drain electrodes electrically connected to the first and second bit line terminals, respectively, and its source electrodes are electrically connected to a ground voltage, and the comparator further includes two opposite phases. The initial output terminals are electrically connected to the gates of the first and second initial transistors, respectively, for controlling the conduction of the first and second initial transistors to write the data into the first and second logic units. . 200409130 6. Application for patent scope 1 6. The selective fuse circuit according to item 14 of the scope of patent application, wherein the initial module includes a first initial transistor and a second initial transistor, the first and second The two initial transistor systems are P-type metal oxide semiconductor transistors, whose drains are electrically connected to the first and second bit line terminals, respectively, and their sources are electrically connected to a high voltage, and the comparator is It also includes two initial outputs with opposite phases, which are electrically connected to the gates of the first and second initial transistors, respectively, for controlling the conduction of the first and second initial transistors to write the data into the first One and second logic unit. 1 7. The selective fuse circuit according to item 1 of the scope of patent application, wherein the comparator further includes a signal output terminal for outputting a signal latched by the latch. Page 26