KR20140139757A - Shift circuit, shift resistor and display - Google Patents

Abstract

The present invention relates to a shift circuit of a shift register including a plurality of cascaded shift circuits. The shift register comprises: an input circuit which has an input terminal (IN), a reset terminal (RST), and a first node (Q), and sets a potential of the first node to a potential based on a level of an input signal (IN[k]) when the input signal (IN[k]) is supplied to the input terminal; an inverter circuit which has a second node (QB) and a first terminal (Vss) and, when the potential of the first node is supplied, sets a potential of the second node to an inverted potential of the first node; and an output circuit which has a clock terminal (CLK) and an output terminal (OUT) and, when the potential of the first node and the potential of the second node are supplied, sets a potential of an output signal (OUT[k]) to a potential of a clock signal (CLK1). The inverter circuit comprises a first transistor of which a gate terminal is connected to the reset terminal and which forms a current path between the first node and the first terminal; and a second transistor of which a gate terminal is connected to the first node and which forms a current path between the second node and the first terminal.

Description

SHIFT CIRCUIT, SHIFT RESISTOR AND DISPLAY [0002]

The present invention relates to a shift circuit, a shift register including the shift circuit, and a display device including the shift register.

Development of a display device for displaying an image by actively driving an organic EL element (OLED) or a liquid crystal display (LCD) by a gate driver using a thin film transistor (TFT) Use is becoming common.

The active driving type display device includes a gate driver for selecting a pixel circuit for switching each pixel arranged in a row unit, and a shift register is usually used for the gate driver.

As such a shift register, there is known a gate driver using an amorphous silicon thin film transistor called Thomson type (Non-Patent Document 1).

1 is a circuit diagram showing the configuration of a conventional shift register disclosed in Non-Patent Document 1. [Fig.

When the start signal is inputted to the input terminal IN, the transistor T1 is turned on and the transistor T3 is charged while the charge is charged to the point P. The transistor T1 is turned on when the start signal is inputted to the input terminal IN, A voltage reduced by the threshold voltage of the transistor T1 is applied to the gate of the transistor T1 and when the clock signal CLK applied to the clock terminal is changed from the low level to the high level, The voltage of the point is subjected to coupling interference by the parasitic capacitances Cgd and Cgs of the transistor T3 so that the P point is bootstrapped to a high threshold voltage. Therefore, the clock signal CLK is output through the output terminal OUT.

When the output of the next stage is inputted to the reset terminal RST, the transistors T2 and T4 are turned on, so that the electric charges charged at the point P and the output terminal OUT are discharged only during the pulse width of the reset signal And remains in a floating state until the next period.

In recent years, there has been a strong demand for miniaturization, weight reduction, high resolution, and low power driving of a display device. Further, a display device using an oxide thin film transistor (OLT) TFT has advantages in that it has higher mobility and higher on-current and transparency than TFTs using amorphous silicon as a semiconductor material, and is particularly adopted as a material for a TFT of a display device (TOLED) using a transparent organic EL element in a pixel circuit have.

Non-Patent Document 1: Improving the reliability of a gate driver using an amorphous silicon thin film transistor, Kwon Min-sung, 2009. 2. Kyunghee University

However, there is a problem in that the oxide TFT has a decisive disadvantage that the threshold voltage is lower than 0 V, which is not easy to apply to a circuit.

For example, if the conventional shift circuit of FIG. 1 is formed of an oxide transistor, the threshold voltage of the transistors Tl to T4 made of an oxide semiconductor material is lower than 0 V, so that even if the output of the next stage is input to the reset terminal RST There is a problem in that an abnormal output voltage is increased when the clock signal T3 is not completely turned off and is partially output to the output terminal OUT every time the clock CLK is turned on or off.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a shift circuit for preventing a problem that the output of the output terminal abnormally rises in accordance with the on / off state of the clock even when the shift circuit is in the reset state, And a display device including the display device.

It is still another object of the present invention to provide a shift circuit which can reliably operate even at a threshold voltage of 0 V or less, a shift register provided with this shift circuit, and a display device provided with this shift register.

A shift circuit according to the present invention for solving the above problems is a shift circuit of a shift register composed of a plurality of cascade-connected shift circuits. The shift circuit includes an input terminal to which the output signal of the preceding stage is supplied as an input signal, An input circuit having a reset terminal supplied as a signal and a first node and setting the potential of the first node to a potential corresponding to the level of the input signal when the input signal is supplied to the input terminal; An inverter circuit having a first terminal and being supplied with a potential of the first node so that the potential of the second node is a potential that inverts the potential of the first node; a clock terminal to which a clock signal is supplied; The potential of the first node and the potential of the second node are supplied so that the potential of the output signal is connected to the clock signal Wherein the inverter circuit includes a first transistor having a gate terminal connected to the reset terminal and forming a current path between the first node and the first terminal, And a second transistor connected to the node and forming a current path between the second node and the first terminal.

Each of the transistors constituting the shift circuit may be constituted by an oxide thin film transistor and the first terminal may be set to a potential lower than the threshold voltage of the oxide thin film transistor constituting the shift circuit.

Wherein the input circuit is turned on when the input signal is supplied to the input terminal and sets a potential of the first node to a potential corresponding to the level of the input signal; And a fourth transistor which is turned on to invert the potential of the first node.

The output circuit comprising: a fifth transistor having a gate terminal connected to the first node and forming a current path between the clock terminal and the output terminal; a gate terminal connected to the second node, And a sixth transistor which forms a current path between the terminals.

The shift register of the present invention is a shift register of a plurality of stages composed of a plurality of cascade-connected shift circuits, and each of the plurality of shift circuits is a shift register composed of any one of the above-mentioned shift circuits.

A display device of the present invention is a display device including a plurality of pixel circuits arranged in a matrix and having a light emitting element and a plurality of pixel circuits including the shift register, And a row selection driver for supplying the plurality of pixel circuits in units of a row and selecting the plurality of pixel circuits in a row unit.

According to the shift circuit of the present invention having the above configuration, when a shift circuit is constituted by a transistor whose threshold voltage is lower than 0 V, it is possible to prevent the problem that the output of the output terminal abnormally rises in accordance with the on / off state of the clock signal in the reset state At the same time, the reference voltage stage and the output stage can be surely separated at the time of outputting the shift circuit, so that the clock signal can be accurately outputted to the output terminal. Therefore, stability of operation of the shift register can be ensured. The stability of operation can be ensured in the case of configuring a shift circuit with a low oxide thin film transistor.

1 is a circuit diagram showing a configuration of a shift circuit of a conventional shift register,
2 is a diagram showing a configuration of a display device according to a preferred embodiment of the present invention,
3 is a diagram showing a configuration of a shift register of the gate driver of FIG. 2,
4 is a diagram showing the configuration of each shift circuit of Fig. 3,
5 is a timing chart showing the operation of the shift circuit of Fig.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

In the following description, the display device of the present embodiment has a plurality of pixels, and each pixel is a display device provided with an organic electroluminescent element (hereinafter referred to as " organic EL element ") as a light emitting element.

Fig. 2 shows a configuration of a display device according to a preferred embodiment of the present invention.

As shown in Fig. 2A, the display device 1 according to the present embodiment includes a plurality of pixel circuits 11 (i, j) (i = 1 to m, j = 1 to n, m and a gate driver (row selection driver) 12, an anode driver 13, a data driver 14, and a controller 15 are provided.

The pixel circuit 11 (i, j) corresponds to each pixel of the image and is arranged in a matrix form. As shown in Fig. 2 (b), the organic EL element 101 and two transistors T11 and T12 And a capacitor C1.

Capacitor C1 is a capacitor disposed between the gate and source of transistor T12.

The organic EL element 101 is a display element having a structure in which a pixel electrode (anode electrode), an organic EL layer composed of a single or a plurality of carrier transporting layers, and an opposing electrode are sequentially laminated, and a cathode potential Vcath) is applied.

The transistors T11 and T12 are TFTs composed of n-channel FETs (Field Effect Transistors) and have drains, sources, and gates. A semiconductor layer is provided between the drains and the sources, and a predetermined bias voltage is applied between the drains and the sources At the same time, when a voltage larger than the threshold voltage is applied to the gate, a channel is formed in the semiconductor layer, and this channel becomes a current path between the drain and the source.

The transistor T11 is a transistor for applying a gradation signal Vdata representing the gradation of the image data Data to one end of the capacitor C1. The source of the transistor T11 of each pixel circuit 11 (i, j) is connected to the gate of the transistor T12 and one end of the capacitor C1.

The drains of the transistors T11 of the pixel circuits 11 (i, 1) to 11 (i, n) are connected to the i-th data line Ldi, , ..., 11 (m, j) are connected to the gate line Lgj of the j-th row, respectively.

Then, when a high-level signal is sequentially outputted to each of the gate lines Lg1, ..., Lgn, each transistor T11 of the pixel circuits 11 (1, j), ..., 11 (m, j) And outputs the gradation signals Vdata respectively inputted to the data lines Ld1, ..., Ldm to the gate of the transistor T12 and one end of the capacitor C1.

The transistor T12 is a transistor for supplying the organic EL element 101 with a current of a current amount based on the gradation signal Vdata and has its gate connected to the source of the transistor T11 and one end of the capacitor C1 The drain is connected to the anode line Laj and the source is connected to the other end of the capacitor C1 and the anode of the organic EL element 101. [

The gate driver 12 is a driver for selecting the pixel circuits 11 (i, j) on a row-by-row basis. As shown in Fig. 3, the voltage Vss is applied to the gate driver 12 from the controller 15 , And the start signal St and the clock signals CLK1 and CLK2 are supplied.

The gate driver 12 starts the operation by being supplied with the start signal St and sequentially outputs the output signals OUT (1) to (n) to the gate lines Lg1 to Lgn in accordance with the clock signals CLK1 and CLK2 .

Thus, the gate driver 12 selects the pixel circuits 11 (1, 1) to 11 (m, 1), ..., 11 (1, n) to 11 (m, n).

The gate driver 12 has a shift register as shown in FIG. 3. The shift register starts its operation by the start signal St supplied from the controller 15 and outputs the clock signals CLK1 and CLK2 And sequentially outputs the output signals OUT (1) to OUT (n) by transmitting the start signal St in synchronization with each other.

The shift register includes first to n-th shift circuits 21_1 to 21_n, which are connected in series with each other.

The input signals IN [k] (including the start signal St) and the clock signals CLK1 and CLK2 are supplied to the shift circuits 21_1 to 21_n and the supplied input signals IN [k] And shifts according to the signal CLK1 or CLK2 to output the shifted signal as the output signal OUT [k] (k = 1 to n).

4, each of the shift circuits 21_k (k = 1 to n) includes an input terminal IN and an output terminal OUT, a reset terminal RST, a voltage terminal Vss, and a clock terminal CLK. .

The input terminal IN is a terminal to which the input signal IN [k] is supplied. The input terminal IN of the shift circuit 21_1 which is the first shift circuit receives the start signal ST from the controller 15, (IN (1)).

The output terminal OUT is a terminal for outputting the output signal OUT [k] and connected to the gate line Lgk. The respective input terminals of the shift circuits 21_2 to 21_n are connected to the output terminals OUT of the shift circuits 21_1 to 21_ (n-1) at the preceding stages, respectively.

The reset terminal RST is a terminal to which the reset signal RST [k] is supplied and the reset terminal RST of each of the shift circuits 21_1 to 21_ (n-1) is connected to the shift circuits 21_2 to 21_n And the output signals OUT (2) to OUT (n) are supplied as reset signals RST (1) to RST (n-1).

The clock terminal CLK is a terminal to which the clock signal CLK1 or CLK2 is supplied and the clock signal CLK1 is supplied from the controller 15 to the clock terminal CLK of the odd numbered stage shift circuit 21_k, The clock signal CLK2 is supplied from the controller 15 to the clock terminal CLK of the single shift circuit 21_ (k + 1).

The reference voltage terminal Vss is a terminal to which a Low level voltage is applied as a reference voltage and the Low level voltage as a reference voltage is a voltage at which the transistors T21 to T26 constituting each shift circuit of this embodiment are composed of oxide transistors It is preferable that the threshold voltage of the oxide transistor is lower than the threshold voltage of the oxide transistor, considering the threshold voltage of the oxide transistor.

The shift circuit 21_k includes transistors T21 to T26. The transistors T21 to T26 are composed of an n-channel type FET composed of an oxide thin film transistor.

The transistors T21 to T26 have a drain, a source, and a gate. A semiconductor layer is provided between the drain and the source. When a predetermined bias voltage is applied between the drain and the source and a voltage greater than the threshold voltage is applied to the gate, A channel is formed, and this channel becomes a current path between the drain and the source.

The transistor T21 is a transistor for determining the potential of the node Q in accordance with the signal level of the input signal IN [k] supplied to the input terminal IN. The gate and the drain of the transistor T21 are connected to the input terminal IN IN, and the node Q is a connection point connected to the source of the transistor T21 as a signal output terminal.

The transistor T23 is a transistor for resetting the shift circuit 21_k by a high level signal supplied to the reset terminal RST. The gate and the drain of the transistor T23 are connected to the reset terminal RST, The source is connected to the gate of the transistor T24 and the transistor T26 through the node QB and the drain side of the transistor T25.

Here, the node QB is an inverting terminal having a potential of the opposite polarity to the node Q, and the transistor T21 and the transistor T23 correspond to the input circuit of the present invention.

The transistor T24 and the transistor T25 constitute an inverter circuit INV which inverts the potential of the node Q and the potential of the node QB to a potential having an inverse relationship with each other.

The transistor T24 inverts the potential of the node Q in accordance with the input of the reset terminal RST and the gate of the transistor T24 is connected to the source side of the transistor T23, And the sources are connected to the reference voltage terminal Vss, respectively.

The transistor T25 is a transistor for controlling the potential of the node QB according to the potential of the node Q. The gate of the transistor T25 is connected to the node Q, the drain is connected to the node QB, Voltage terminal Vss, respectively.

The potentials of the node Q and the node QB are complementarily switched to the high level (on level) and the low level (off level) by the inverter circuit INV constituted by the transistors T24 and T25, Becomes the high level, the other becomes the low level.

The transistor T22 is supplied with the clock signal CLK1 or CLK2 applied from the clock terminal CLK and is turned on or off according to the potential of the node Q. In the on state, And outputs the signal OUT [k] to the output terminal OUT.

The transistor T22 has a gate connected to the node Q, a drain connected to the clock terminal CLK, and a source connected to the output terminal OUT. A capacitor C _Q for generating a bootstrap effect is connected between the gate and the source of the transistor T22.

The transistor T26 is turned on or off according to the potential of the node QB and is turned on during the non-selection period of the pixel circuit 11 (i, k) in the k-th row to output to the output terminal OUT Is a transistor for stabilizing the output signal OUT [k] by fixing the signal OUT [k] to Vss (voltage lower than the threshold voltage of each transistor) as a reference voltage.

The gate of the transistor T26 is connected to the node QB, the drain is connected to the source and the output terminal OUT of the transistor T22, and the source is connected to the reference voltage terminal Vss.

The transistor T22 and the transistor T26 correspond to an output circuit.

Returning to FIG. (A), (b) of Figure 2, the anode driver 13 includes an anode line (La (1) -La (n)) for each voltage V V _High or _Low of a signal (Vsource (1) -Vsource (n)), and the anode driver 13 applies a voltage to the drain of the transistor T12 of each pixel circuit 11 (i, j) through the anode line Laj (j = 1-n) Respectively.

The anode driver 13 starts operation by the start signal St supplied from the controller 15 and operates in accordance with the clock signal CLK1 supplied from the controller 15 to generate a voltage V _High or V _Low And outputs a signal (Vsource (1) -Vsource (n)). The voltage V _Low is a voltage for _turning the organic EL element 101 of each pixel circuit 11 (i, j) into a non-light emitting state at the time of the writing process, and the voltage V _High is a voltage for each pixel circuit 11 j) to turn the organic EL element 101 into a light emitting state.

However, if necessary, the anode driver 13 may not be provided separately, and a so-called common anode may be used in which the anode voltage is simultaneously applied to the anode lines of the plurality of pixel circuits.

For example, the cathode voltage (Vcath) of the organic EL element 101 is set to 0 V, the voltage V _Low is set to 0V or lower, and the voltage V _High is set to, for example, + 15V.

The data driver 14 is a driver for writing the gradation signal Vdata of the display signal based on the pixel data Data supplied to each capacitor C1 of the pixel circuit 11 (i, j) And outputs the generated gradation signals Vdata to the gate driver 12 through the data lines Ld1 to Ldm, respectively, by the gate driver 12, to the pixel circuits 11 (1, j) -11 (m, j) of the j-th row.

The controller 15 controls the gate driver 12 and the data driver 14 and includes a CPU (Central Processing Unit), a ROM (Read Only Memory) and a RAM (Random Access Memory), and the shift circuits 21_1- And supplies the start signal St to the shift circuit 21_1 of the first stage of the gate driver 12 in a state of outputting the clock signal CLK1 to the odd-numbered stage of the gate driver 21_n and outputting the clock signal CLK2 to the even- (12) to start operation.

The controller 15 supplies the start signal St and the image data Data and the clock signal CLK1 to the data driver 14.

Next, the operation of the display apparatus of the present embodiment will be described. 5 is a timing chart showing the operation of the shift circuit of Fig.

5, the controller 15 supplies clock signals CLK1 and CLK2 having phases different from each other by 180 degrees and a start signal St of a high level to the gate driver 12, and when the clock signal CLK1 is at the Low level At time t10, the start signal St of the high level is supplied as the input signal IN [1] to the input terminal IN of the first-stage shift circuit 21_1, whereby the shift circuit 21_1 having the diode structure The transistor T21 is turned on. The period during which the start signal St of the high level is supplied is the input period tin.

When the transistor T21 is turned on, the potential of the node Q becomes a high level, whereby the transistor T22 and the transistor T25 are turned on. When the transistor T25 is turned on, the voltage of the node QB Becomes a Vss voltage, that is, an OFF voltage, so that the transistor T26 becomes a reverse diode state and becomes a completely OFF state.

Next, after the input period tin, the input signal IN [1] goes Low level and the transistor T21 turns off in the output period tout when the clock signal CLK1 goes High.

However, since the transistor T26 is off, the voltage of the node Q does not fall to the low level and remains in a floating state. At this time, when the clock signal CLK1 becomes high level, the node _{Q is} supplied with the node Q by the bootstrap capacitor C _Q A bootstrap occurs as much as the clock signal CLK1 and the gate voltage of the transistor T22 becomes the sum of the floating voltage and CLK1 so that the clock signal CLK1 is reliably output as the output signal OUT [1] through the output terminal OUT .

The output signal OUT [1] of the high level is outputted to the gate line Lg1 and is supplied as the input signal IN [2] to the next shift circuit 21_2. The shift circuit 21_2 outputs And shifts the input signal IN [2] in synchronization with the clock signal CLK2 to output the high level output signal OUT [2].

The output signal OUT [2] of the high level is supplied to the reset terminal RST of the shift circuit 21_1 as the reset signal RST [1] of the shift circuit 21_1 of the preceding stage.

When the reset signal RST [1] is supplied to the reset terminal RST of the shift circuit 21_1, the transistor T23 having the diode structure is turned on and the voltage of the node QB becomes high level, The transistor T24 and the transistor T26 are turned on and the voltage of the node Q and the output terminal OUT falls to the Vss voltage, that is, the Low level.

In addition, the voltage of the node Q becomes low level, so that the transistor T25 is turned off. Even when the reset signal RST [1] becomes Low level after the reset period RST, the potential of the node QB becomes The floating state is maintained, whereby the transistor T26 is turned on and the output signal can be reliably kept off.

Similarly to the above operation, the shift circuit 21_k (k = 2 to n) outputs the output signal OUT [k-1] output from the shift circuit 21_k-1 in synchronism with the clock signals CLK1 and CLK2, (IN [k]) and shifts this input signal IN [k]. The shift circuit 21_k outputs the shifted signal as the output signal OUT [k].

The gate driver 12 outputs the high level output signal OUT [1] of the shift circuit 21_1 to the gate line Lg1 and the pixel circuits 11 (1, 1) to 11 (m, 1) Is turned on by the output signal OUT [1] of the high level.

The data driver 14 supplies the gradation signals Vdata to the pixel circuits 11 (1, 1) to 11 (m, 1) selected by the gate driver 12 through the data lines Ld1 to Ldm during this period, And the gradation signals Vdata are written to the respective capacitors C1 of the pixel circuits 11 (1, 1) to 11 (m, 1) through the respective transistors T11.

The gate driver 12 sequentially outputs the high level output signals OUT [2], OUT [3], ..., OUT [n] of the shift circuits 21_2, 21_3 ... 21_n to the gate lines Lg2 , Lg3, ..., Lgn.

When the output signals OUT [2], OUT [3], ..., OUT [n] are sequentially output to the gate lines Lg2, Lg3, ..., Lgn, , 11 (1, n) to 11 (m, n)) are selected and the data driver 14 selects the pixel data (M, 2) to 11 (1, 3) to 11 (m, 3) to 11 (m) are applied to the data lines Ld1 to Ldm by applying the gradation signals Vdata to the data lines Ld1 to Ldm, ..., and 11 (1, n) to 11 (m, n).

When the writing is completed in the above manner, the controller 15 controls the light emitting operation.

The anode driver 13 outputs the high level signals Vsource (1) to Vsource (n) to the anode lines La (1) to La (n) The transistor T22 of the organic EL element 101 supplies the electric current corresponding to the gate voltage Vgs to the organic EL element 101 with the voltage held by each capacitor C1 as the gate voltage, And emits light at a luminance corresponding to the current value of the current.

However, the present invention is not limited thereto. If the display device is a common anode, the anode voltage may be simultaneously applied to a plurality of pixel circuits from one anode power source.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments.

In the above embodiment, the display device of the present invention has been described as a display device having an organic EL device. However, the display device is not limited thereto and any display device may be used as long as it is a display device having a light emitting element. For example, a liquid crystal display device having a liquid crystal element.

In the above-described embodiment, each of the transistors constituting the shift circuit is formed of an n-channel FET, but may be a p-channel FET. In this case, the control signal supplied to the control electrode (gate) of each transistor may be supplied with a signal opposite to that of the n-channel type FET.

In the above embodiment, the case where the transistor constituting the shift circuit is an oxide thin film transistor has been described as an example, but the present invention is not limited to this, and other kinds of transistors may be used.

1 display device
11-pixel circuit
12 gate driver
13 Anode driver
14 data driver
15 controller
21 shift circuit
T21 ~ T26 Transistors
IN input terminal
OUT output terminal
RST reset terminal
Vss reference voltage terminal
IN [k]] input signal
OUT [k] output signal
RST [k] reset signal

Claims (7)

A shift register shift circuit comprising a plurality of cascade-connected shift circuits,
A reset terminal to which an output signal of the previous stage is supplied as an input signal and a reset terminal to which an output signal of the next stage is supplied as a reset signal and a first node, An input circuit for setting the potential to a potential corresponding to the level of the input signal,
An inverter circuit having a second node and a first terminal and being supplied with the potential of the first node to set the potential of the second node to a potential that inverts the potential of the first node;
A clock terminal to which a clock signal is supplied and an output terminal to which the output signal is output and which is supplied with the potential of the first node and the potential of the second node to set the potential of the output signal to a potential corresponding to the clock signal Circuit,
The inverter circuit comprising: a first transistor having a gate terminal connected to the reset terminal and forming a current path between the first node and the first terminal; and a gate terminal connected to the first node, And a second transistor forming a current path between the first terminals. The method according to claim 1,
Wherein the input circuit is turned on when the input signal is supplied to the input terminal and sets a potential of the first node to a potential corresponding to the level of the input signal; And a fourth transistor which is turned on to invert the potential of the first node. The method according to claim 1,
The output circuit comprising: a fifth transistor having a gate terminal connected to the first node and forming a current path between the clock terminal and the output terminal; a gate terminal connected to the second node, And a sixth transistor forming a current path between the terminals. The method according to claim 1,
Wherein each transistor constituting the shift circuit is constituted by an oxide thin film transistor. The method of claim 4,
And the first terminal is set to a potential lower than a threshold voltage of the oxide thin film transistor constituting the shift circuit. A plurality of stages of shift registers composed of a plurality of shift circuits connected in cascade,
Wherein each of the plurality of shift circuits comprises a shift circuit according to any one of claims 1 to 5. A plurality of pixel circuits having light emitting elements arranged in a matrix form,
A shift register comprising the shift register of claim 5,
And a row selection driver for supplying the output signals of the shift circuits included in the shift register on a row-by-row basis as a row selection signal for selecting rows and selecting the plurality of pixel circuits in a row unit.

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