KR20130025797A - Photo multiplier and manufacturing method for the same - Google Patents

Abstract

PURPOSE: A photo multiplier and a method for manufacturing the same are provided to maximize productivity by simplifying a process for manufacturing a silicon micro cell diode. CONSTITUTION: A mask film is formed on an active area(102) of a first conductive substrate. A first doping area(120) is formed by implanting a second conductive impurity to a substrate. An element isolation film is formed on an inactive area(104). A mask film is removed. A second doping area is formed by implanting the second conductive impurity in the first doping area.

Description

Photo multiplier and manufacturing method for the same

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a photomultiplier and a method for manufacturing the same.

The semiconductor optical sensor may include an avalanche photodiode that detects weak light. Avalanche photodiodes can detect high sensitivity light detection with avalanche multiplication that accelerates electron-holes. Based on such avalanche photodiodes, research and development of semiconductor photomultipliers, which operate in the voltage range exceeding the breakdown voltage and can detect even the weakest incident light, are being actively conducted.

The photo multiplier may include cell diodes and dissipation resistors connected in series with the cell diodes. The decay resistors cause an ohmic voltage drop when an instantaneous current due to electrical breakdown flows in the microcell, thereby reducing the breakdown state by lowering the voltage applied to each cell diode below the breakdown voltage. .

In general, a cell diode made of silicon may include a low concentration of epitaxial silicon thin film on a bulk silicon layer of a high concentration doped layer. For example, the microcell diodes may have a doping structure such as p + / p− / n +, p + / n− / n +, n + / n− / p +, n + / p− / p +.

The microcell diodes of such a simple structure do not work properly due to the edge edge (premature edge breakdown). A general photo multiplier may include a guard ring formed at the edge of the microcell diodes to prevent edge phenomenon.

However, the conventional method of manufacturing a photomultiplier requires a lithography process for forming a guard ring, which can lower productivity. For example, a silicon microcell diode may be formed through about three lithography processes including a mask alignment pattern, an upper doped layer pattern, and a guard pattern.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a photo multiplier capable of maximizing productivity by simplifying a manufacturing process of a silicon microcell diode and a method of manufacturing the same.

In order to achieve the above technical problem, a method of manufacturing a photo multiplier according to an embodiment of the present invention, forming a mask film on the active region of the substrate doped with a first conductivity type; Ion implanting a second conductivity type impurity opposite to the first conductivity type into the substrate to form a first doped region in the active region under the mask layer and in an inactive region exposed from the mask layer; Forming an isolation layer on the inactive region; Removing the mask layer; And ion implanting the second conductivity type impurity at a higher concentration than the first doped region over the first doped region in the active region to form a second doped region that is shallower than the first doped region.

According to one embodiment of the present invention, the first doped region may be formed by a counter ion implantation process. The counter ion implantation process may include a multiple ion implantation method.

According to another embodiment of the present invention, the second doped region may be formed by a self-aligned ion implantation process or a self-aligned diffusion process of the device isolation film.

According to an embodiment of the present invention, the device isolation layer may include a silicon oxide film formed by a locus method.

According to another embodiment of the present invention, the mask film may include a silicon nitride film. The silicon nitride film may be removed by phosphoric acid, hydrofluoric acid, or bromic acid.

According to an embodiment of the present invention, forming a first interlayer insulating film on the second doped region and the device isolation layer; Forming a dissipation resistor on the first interlayer insulating film of the inactive region; Forming a second interlayer insulating film on the first interlayer insulating film and the dissipation resistor; Forming contact holes by removing a portion of the second interlayer insulating layer on the dissipation resistor and a portion of each of the first and second interlayer insulating layers on the second doped region; Forming a first wiring on the second interlayer insulating layer of the inactive region and a second wiring connecting the second doped region and the extinction resistors through the contact holes; And forming a lower electrode on the bottom of the substrate.

According to another embodiment of the present invention, a photo multiplier includes: a substrate defined as an active region and an inactive region; A cell diode comprising a lower portion of the substrate in the active region and a first doped region and a second doped region formed on the active region; An isolation layer formed on the inactive region; A first interlayer insulating layer formed on the device isolation layer and the second doped region; And a dissipation resistor formed on the first interlayer insulating film in the inactive region. Here, the first doped region may extend to the inactive region.

According to an embodiment of the present invention, the first doped region may be disposed deeper than the active region in the non-active region.

According to another embodiment of the present invention, the second doped region may be disposed from the upper surface of the substrate of the active region to an upper portion of the substrate that is shallower than the first doped region.

In example embodiments, the device isolation layer and the first interlayer insulating layer may include a silicon oxide layer.

As described above, according to the exemplary configuration of the present invention, a mask film is formed by a photolithography process on the active region of the substrate doped with the first conductivity type. Next, a second dopant is implanted into the substrate to form a first doped region in the active region under the mask layer and in an inactive region. An element isolation film is formed on the inactive region exposed from the mask film, and the mask film is removed. A second doped region shallower than the first doped region is formed in the active region by a self-aligned ion implantation process from the device isolation layer. The cell diode including the substrate under the active region, the first doped region, and the second doped region may be formed in one photolithography process. Therefore, the manufacturing method of the photo multiplier of this invention can maximize productivity.

In addition, the first doped region may suppress generation of a depletion region in an inactive region. Accordingly, the photomultiplier of the present invention can prevent the edge phenomenon of the cell diodes by the first doped region extending from the active region to the inactive region.

1 is a plan view of a photo multiplier according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line II 'in Fig.
3 to 13 are cross-sectional views sequentially illustrating a method of manufacturing the photomultiplier of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in different forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. In addition, since they are in accordance with the preferred embodiment, the reference numerals presented in the order of description are not necessarily limited to the order.

1 is a plan view of a photo multiplier according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, the photomultiplier of the present invention includes cell diodes 101 connected in series between the first wirings 106 and the lower electrode 180, quench resistors, 108). The first wires 106 may extend in directions parallel to each other on the non-active region 104 of the substrate 100. The lower electrode 180 may be disposed on the bottom of the substrate 100. The cell diodes 101 may have a planar diode structure in which electrical breakdown occurs due to a carrier charge generated from optical excitation therein.

For example, the cell diodes 101 may include a lower portion of the substrate 100 of the active region 102, a first doped region 120, and a second doped region 140. The lower portion of the substrate 100 of the active region 102 may be doped with a high concentration of first conductivity type impurities. The first doped region 120 may be doped with a low concentration of first conductivity type impurities or second conductivity type impurities. The first doped region 120 may extend from the active region 102 to the inactive region 104. That is, the first doped region 120 may be disposed on the entire substrate 100. The first doped region 120 may be disposed deeper than the active region 102 in the non-active region 104. The first doped region 120 in the inactive region 104 may prevent edge breakdown of the cell diodes 101.

The second doped region 140 may be doped with a high concentration of second conductivity type impurities. The first conductivity type impurity and the second conductivity type impurity may have opposite conductivity types. The second doped region 140 may be disposed from an upper surface of the substrate 100 of the active region 102 to an upper portion of the substrate 100 that is shallower than the first doped region 120. The second doped region 140 may be doped with a higher concentration of the second conductivity type impurity than the first doped region 120. The substrate 100 may include a silicon substrate. In addition, the first conductivity type impurity may include p-type boron or gallium. The second conductivity type impurity may comprise n-type arsenic or phosphorus.

The quenching resistors 108 may be disposed on the device isolation layer 130 and the first interlayer insulating layer 150. The quench resistors 108 may buffer a sudden voltage drop due to the breakdown voltage generated in the cell diodes 101. The dissipation resistors 108 may include polysilicon doped with conductive impurities. The first and second interlayer insulating layers 150 and 160 may cover the second doped region 140 and the device isolation layer 130 of the active region 102. The second interlayer insulating layer 160 may cover the dissipation resistors 108. The second wires 109 may electrically connect the cell diodes 101 and the decay resistors 108 through the contact holes (170 of FIG. 11) of the first and second interlayer insulating layers 150 and 160. have.

When a bias voltage is applied to the first wirings 106 and the lower electrode 180, a depletion region (not shown) may be induced in the first doped region 120 of the cell diodes 101 in the active region 102. Can be. The first doped region 120 may suppress generation of a depletion region in the non-active region 104 at the edge of the active region 102.

Accordingly, the photo multiplier according to the embodiment of the present invention can prevent the edge phenomenon of the cell diodes 101 by the first doped region 120 extending from the active region 102 to the inactive region 104. have.

Referring to the manufacturing method of the photo multiplier according to the embodiment of the present invention configured as described above are as follows.

3 to 13 are cross-sectional views sequentially illustrating a method of manufacturing the photomultiplier of the present invention.

Referring to FIG. 3, a mask film 110 is formed on the active region 102 of the substrate 100. The mask film 110 may include a silicon nitride film. The mask film 110 may be patterned on the active region 102 by a photolithography process. The substrate 100 may be heavily doped with the first conductivity type impurity before the mask film 110 is formed. For example, the substrate 100 may include a p-type substrate doped with a high concentration of boron (B).

Referring to FIG. 4, a first doped region 120 is formed in the active region 102 and the non-active region 104. The first doped region 120 may have a first conductivity type or a second conductivity type having a lower concentration than the substrate 100 by ion implantation of the second conductivity type impurities. The net doping concentration of the first doped region 120 may be determined by the amounts of the first conductivity type impurities and the second conductivity type impurities. If the first conductivity type impurity is greater than the second impurity, the first doped region 120 may have the first conductivity type. On the other hand, if the second conductivity type impurity is greater than the first conductivity type impurity, the first doped region 120 may have the second conductivity type. For example, the first doped region 120 may be formed of a low concentration p type or n type. Therefore, the net doping concentration of the first doped region 120 may be determined by the counter ion implantation process of the second conductivity type impurity. The counter ion implantation process may include multiple implantation of different energies.

The first doped region 120 may be formed deeper in the substrate 100 of the non-active region 104 than the active region 102. The mask layer 110 may serve as a screen for controlling the amount and depth of the second conductivity type impurities in the active region 102 during ion implantation. The first doped region 120 of the active region 102 may be formed to an increased depth in inverse proportion to the thickness of the mask layer 110. Therefore, the depth and doping concentration of the first doped region 120 may be controlled by the mask layer 102.

In addition, the first doped region 120 in the inactive region 104 may suppress the edge breakdown of the device. This is because the electric field strength of the first doped region 120 formed deeper in the inactive region 104 than in the active region 102 is weakened.

Referring to FIG. 5, the device isolation layer 130 is formed on the inactive region 104. The device isolation layer 130 may include a silicon oxide layer formed by a local oxide of silicon (LOCOS) method. The device isolation layer 130 may be formed on the inactive region 104 exposed from the mask layer 110.

Referring to FIG. 6, the mask film 110 on the active region 102 is removed. The mask film 110 may be removed by an acidic solution or gas such as phosphoric acid, hydrofluoric acid, or bromic acid.

1 and 7, a second doped region 140 is formed on the first doped region 120 of the active region 102. The device isolation layer 130 may be used as an ion implantation mask when the two doped regions 140 are formed. The second doped region 140 may be formed by a self-aligned ion implantation process or a self-aligned diffusion process of the device isolation layer 130.

The substrate 100, the first doped region 120, and the second doped region 140 of the active region 102 may be cell diodes 101. For example, the cell diodes 101 may have a p + / p / n + or p + / n / n + structure in the active region 102. The inactive region 104 and the device isolation layer 130 may be cell separators that deplete during operation of the device to electrically separate the cell diodes 101. The cell diodes 101 may be formed by one photolithography process.

Therefore, the manufacturing method of the photo multiplier according to the embodiment of the present invention can maximize productivity compared to the prior art.

Referring to FIG. 8, a first interlayer insulating layer 150 is formed on the substrate 100. The first interlayer insulating layer 150 may include a silicon oxide film formed by a chemical vapor deposition method. The silicon oxide film may be a transparent film through which external light (not shown) passes. Although not shown, the first interlayer insulating layer 150 may be removed on the active region 102 by a wet etching method or a dry etching method.

Referring to FIG. 9, an extinction resistor 108 is formed on a portion of the first interlayer insulating layer 150 of the inactive region 104. The dissipation resistor 108 may include a dielectric such as polysilicon or a metal oxide film.

Referring to FIG. 10, a second interlayer insulating layer 160 is formed on the entire surface of the substrate 100. The second interlayer insulating layer 160 may include a silicon oxide film formed by a chemical vapor deposition method. The second interlayer insulating layer 160 may be a protective film.

Referring to FIG. 11, a portion of the first and second interlayer insulating layers 150 and 160 of the active region 102 and a portion of the second interlayer insulating layer 160 on the dissipation resistor 108 may be removed to form contact holes 170. ). The contact holes 170 may expose the second doped region 140 and a portion of the extinction resistor 108, respectively.

Referring to FIG. 12, the first wiring 106 and the second wiring 109 are formed. The first wiring 106 can be formed on the second interlayer insulating film of the inactive region 104. The second wiring 109 may electrically connect the second doped region 140 and the extinction resistor 108 through the contact holes 170.

1 and 13, the lower electrode 180 is formed on the bottom of the substrate 100. The lower electrode 180 may include a conductive metal having high conductivity and reflection efficiency, such as aluminum or tungsten.

As a result, the method of manufacturing the photomultiplier according to the embodiment of the present invention can maximize the productivity because the cell diodes 101 can be performed in one photolithography process.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

100 substrate 101 cell diodes
102: active area 104: inactive area
106: first wirings 108: second wirings
109: second wirings 110: mask film
120: first doped region 130: device isolation film
140: second doped region 150: first interlayer insulating film
160: second interlayer insulating film 170: contact holes
180; Bottom electrode

Claims (12)

Forming a mask film on the active region of the substrate doped with the first conductivity type;
Ion implanting a second conductivity type impurity opposite to the first conductivity type into the substrate to form a first doped region in the active region under the mask layer and in an inactive region exposed from the mask layer;
Forming an isolation layer on the inactive region;
Removing the mask layer; And
And implanting the second conductivity type impurity at a higher concentration than the first doped region over the first doped region in the active region to form a second doped region that is shallower than the first doped region. Method of manufacturing the pliers. The method of claim 1,
And the first doped region is formed by a counter ion implantation process. The method of claim 2,
The counter ion implantation process is a method for manufacturing a photo multiplier comprising a multiple ion implantation method. The method of claim 1,
And the second doped region is formed by a self-aligned ion implantation process or a self-aligned diffusion process of the device isolation layer. The method of claim 1,
The device isolation film is a method of manufacturing a photomultiplier comprising a silicon oxide film formed by a Locus method. The method of claim 1,
The mask film is a method of manufacturing a photomultiplier comprising a silicon nitride film. The method according to claim 6,
Wherein the silicon nitride film is removed by phosphoric acid, hydrofluoric acid, or bromic acid. The method of claim 1,
Forming a first interlayer insulating layer on the second doped region and the device isolation layer;
Forming a dissipation resistor on the first interlayer insulating film of the inactive region;
Forming a second interlayer insulating film on the first interlayer insulating film and the dissipation resistor;
Forming contact holes by removing a portion of the second interlayer insulating layer on the dissipation resistor and a portion of each of the first and second interlayer insulating layers on the second doped region;
Forming a first wiring on the second interlayer insulating layer of the inactive region and a second wiring connecting the second doped region and the extinction resistors through the contact holes; And
Forming a lower electrode on the bottom of the substrate manufacturing method of a photo multiplier further comprising. A substrate defined by active and non-active regions;
A cell diode comprising a lower portion of the substrate in the active region and a first doped region and a second doped region formed on the active region;
An isolation layer formed on the inactive region;
A first interlayer insulating layer formed on the device isolation layer and the second doped region; And
A decay resistor formed on said first interlayer insulating film in said non-active region,
And the first doped region extends to the inactive region. The method of claim 9,
And the first doped region is deeper in the non-active region than the active region. The method of claim 9,
And the second doped region is disposed from an upper surface of the substrate of the active region to an upper portion of the substrate that is shallower than the first doped region. The method of claim 9,
The device isolation film and the first interlayer insulating film may include a silicon oxide film.

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