KR20100042468A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
- Publication number
- KR20100042468A KR20100042468A KR1020080101624A KR20080101624A KR20100042468A KR 20100042468 A KR20100042468 A KR 20100042468A KR 1020080101624 A KR1020080101624 A KR 1020080101624A KR 20080101624 A KR20080101624 A KR 20080101624A KR 20100042468 A KR20100042468 A KR 20100042468A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- exposure
- mask
- forming
- photosensitive film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000671 immersion lithography Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 4
- 238000007654 immersion Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2041—Exposure; Apparatus therefor in the presence of a fluid, e.g. immersion; using fluid cooling means
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70216—Mask projection systems
- G03F7/70341—Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
In the method of forming a semiconductor device of the present invention, a photosensitive film is coated on an upper surface of a semiconductor substrate on which an etched layer is formed, and the first photosensitive film is first exposed using a first exposure mask in the form of a line-and-space pattern having a first direction. After the second exposure of the photoresist film using a second mask in which a line-and-space pattern in a second direction crossing the first direction is formed, the non-exposed portion of the photoresist film is removed to form a photoresist pattern, thereby forming a high density contact hole size. Provides the effect of forming uniformly.
Description
The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a fine contact hole.
Due to the integration of semiconductor devices, the size of the pattern becomes smaller and the spacing between neighboring patterns decreases as the number of patterns to be formed in the limited region increases.
In general, such a semiconductor device is implemented through an exposure process. In brief, the photoresist is coated on the etched layer to be patterned to expose the upper surface of the photoresist through an exposure process, and the properties of the photoresist film are used in a subsequent development process. By forming a photoresist pattern, and etching the layer to be etched by using the photoresist pattern as an etch mask to form an etched layer pattern to realize the pattern to be patterned.
In such an exposure process, resolution and depth of focus (DOF) are known as two important issues.
The dual resolution R may be represented by Equation 1 below. In Equation 1 below, k1 is a constant determined by the type, thickness, etc. of the photoresist film, λ is a wavelength of a light source to be used, and NA (Numerical Aperture) is a numerical aperture of the exposure apparatus.
As can be seen from Equation 1, the shorter the wavelength λ of the light source to be used and the larger the numerical aperture NA of the exposure apparatus, the smaller the pattern can be implemented on the semiconductor substrate.
Therefore, in the exposure process in which KrF (248 nm), ArF (103 nm), and F2 (157 nm) are generally applied, a pattern realization method using an immersion lithography process or an exposure process using short-ultraviolet ultraviolet rays such as EUV Is being developed.
Among them, immersion lithography does not use air having a refractive index of 1.0 as a medium of an exposure beam intermediate a semiconductor substrate on which an exposure lens and a resist film are formed, but water having a refractive index of 1.0 or more as an intermediate medium. Or by using fluids, such as an organic solvent, even if it uses the light source of the same exposure wavelength, it is the exposure method which acquires the same effect as using a light source of a short wavelength or using the lens of a high numerical aperture, and does not reduce a depth of focus.
In the case of 1: 1 pitch line-and-space pattern using immersion exposure equipment, the limit of resolution is about 40nm based on half pitch.
However, in the case of forming a 1: 1 pitch high-density contact hole pattern, patterning is difficult, and thus it is difficult to secure a resolution for realizing 50 nm based on half pitch.
As such, the wavelength λ of the light source used and the numerical aperture NA of the exposure apparatus are limited due to the high integration of the semiconductor device. As shown in FIG. 1, patterning is possible on the semiconductor substrate. There is a problem that the size is not formed uniformly.
In the present invention, when the high-density contact hole pattern is implemented due to high integration, the size of each contact hole is not uniformly formed due to the limitation of resolution.
The method of forming a semiconductor device of the present invention comprises the steps of applying a photoresist film on the semiconductor substrate on which the etched layer is formed, and firstly exposing the photoresist film by using a first exposure mask in the form of a line and space pattern having a first direction; Secondly exposing the photoresist film by using a second mask on which a line-and-space pattern in a second direction intersecting the first direction is formed, and removing a non-exposed portion of the photoresist film to form a photoresist pattern. Characterized in that.
At this time, the first direction is characterized in that orthogonal to the second direction.
The first direction and the second direction are symmetrically positioned with respect to the y axis.
In addition, the photoresist pattern is characterized in that formed by the immersion lithography process.
In addition, the photosensitive film is characterized in that the positive type (positive type).
And the photoresist pattern is formed using a negative developer.
In addition, the pitch of the line and space pattern is characterized in that 1: 1 to 10.
In the present invention, it is possible to implement the ArF immersion exposure apparatus using a high-density contact hole pattern having a 1: 1 pitch, which can reduce the investment cost of equipment for applying a short wavelength exposure source and for each high-density contact hole. There is an advantage that the size is formed uniformly.
Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
The present invention provides a method for forming a high-density contact hole even by using an immersion exposure apparatus by performing an exposure process on a positive photoresist film and a development process using a negative developer.
Accordingly, the present invention describes an aligned contact hole and a staggered contact hole by way of example, and are not necessarily limited thereto. Those skilled in the art will be aware of the present invention based on the spirit and scope of the present invention. It can be easily changed.
In order to implement the semiconductor device according to the present invention, two exposure masks are required. In this case, the two masks have a pattern of line and space having a pitch of 1: 1 to 10, and the shape of the contact hole pattern to be finally implemented. Accordingly, it is divided as follows, and a method of forming a semiconductor device using the same can be represented as follows.
First, a method of forming a semiconductor device for implementing an aligned contact hole will be described.
FIG. 2A illustrates a layout of an exposure mask used to implement an aligned contact hole according to the present invention, and FIGS. 2B to 2D illustrate a method of forming a semiconductor device using the exposure mask of FIG. 2A.
For convenience, FIGS. 2A to 2D show portions of the mask and the semiconductor substrate, not the entire portion.
As shown in FIG. 2A, the first and second masks are provided with
In this case, it is preferable that the
Next, as illustrated in FIG. 2B, the
In this case, the
Next, as shown in FIG. 2C, the second exposure is performed using the second mask on the
The light source transmitted through the
At this time, the non-exposed areas 75 which are not exposed from the first and second exposures are generated. In the present invention, the non-exposed areas 75 are formed because the development process performed by a subsequent process is performed using a negative developer. Removed.
Therefore, as illustrated in FIG. 2D, when the developing process is performed on the
Thereafter, when the
Next, a method of forming a semiconductor device using an exposure mask for implementing a staggered contact hole will be described.
3A illustrates a layout of an exposure mask for implementing a staggered contact hole, and FIGS. 3B to 3D illustrate a method of forming a semiconductor device using the mask of FIG. 3A.
For convenience, FIGS. 3A to 3D show a part of the mask and the semiconductor substrate, and not the whole part.
As shown in FIG. 3A, the first and second masks are preferably provided with
In this case, the
Next, after the
At this time, as shown in FIG. 3B, the light source passing through the
Next, secondary exposure is performed using the second mask on the
As shown in FIG. 3C, the light source transmitted through the
In this case, the
Accordingly, as shown in FIG. 3D, when the developing process is performed on the
Thereafter, by etching the etched
When the high density contact hole is implemented through the above method, it is possible to prevent the contact hole size from being formed uniformly.
1 is an electron scanning microscope image showing a semiconductor device formed according to the prior art.
2A is a layout of an exposure mask used to implement an aligned contact hole in accordance with the present invention.
2b to 2d illustrate a method of forming a semiconductor device according to the present invention.
3A is a layout of an exposure mask used to implement a staggered contact hole in accordance with the present invention.
3B to 3D illustrate a method of forming a semiconductor device in accordance with the present invention.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080101624A KR20100042468A (en) | 2008-10-16 | 2008-10-16 | Method for forming semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080101624A KR20100042468A (en) | 2008-10-16 | 2008-10-16 | Method for forming semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR20100042468A true KR20100042468A (en) | 2010-04-26 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020080101624A KR20100042468A (en) | 2008-10-16 | 2008-10-16 | Method for forming semiconductor device |
Country Status (1)
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KR (1) | KR20100042468A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107656426A (en) * | 2017-11-02 | 2018-02-02 | 睿力集成电路有限公司 | The forming method of hole pattern and the semiconductor structure with hole pattern |
-
2008
- 2008-10-16 KR KR1020080101624A patent/KR20100042468A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107656426A (en) * | 2017-11-02 | 2018-02-02 | 睿力集成电路有限公司 | The forming method of hole pattern and the semiconductor structure with hole pattern |
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