KR20050068389A - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a capacitor of a semiconductor device in which a cleaning chemical is used to increase the surface area of a capacitor to improve device characteristics. The method includes forming a first polysilicon layer to be connected to a storage node contact. Stacking a first material layer affected by the cleaning liquid and a second material layer unaffected on the first polysilicon layer, and selectively patterning the stacked first and second material layers using a storage node mask Performing a cleaning process to partially etch the side surface of the first material layer; forming a second polysilicon layer on the entire surface including the first material layer partially etched in the side surface; Etching the 2 polysilicon layer to form a storage node having curvature by the first and second material layers, and removing the first and second material layers. Include.

Description

Method for fabricating capacitor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of forming a capacitor of a semiconductor device in which the surface area of the capacitor is increased by using a cleaning chemical to improve the characteristics of the device.

The biggest aspect of DRAM development is that in addition to the development of process technology such as photo and etch necessary to form fine patterns, it is important to efficiently reduce the memory device to store the information charge.

However, as the size of the memory device decreases, the area occupied by the capacitor is reduced, which places serious limitations on securing sufficient storage capacity for maintaining the stored information.

In the prior art, the following method is used as a method of increasing the capacitor capacity.

First, the capacitance of the dielectric film formed between the capacitor upper and lower electrodes is increased by using a high dielectric constant thin film ε.

Although this method can increase the capacitance of the capacitor, the energy band gap becomes smaller as the dielectric constant becomes thinner, which causes a problem of poor leakage current characteristics.

The thickness d of the dielectric thin film formed between the capacitor upper and lower electrodes is reduced. However, this method is also undesirable because it is a direction in which leakage current increases.

In addition, there is a method of increasing capacitance by increasing the surface area of the upper and lower electrodes of the capacitor.

This method is widely used because it can increase the capacitance of the capacitor while keeping the same thickness as the existing dielectric material.

Among them, the method of increasing the capacitor area is to secure the area and the spacing of the device by cell designing the capacitor in three dimensions to form a stacked structure or a trench structure.

A method of depositing a metastable polysilicon (MPS) grain on the surface of an electrode as a method of securing capacitance by giving an uneven surface to the surface of the charge storage to increase the effective area.

MPS is a hemispherical shaped grains (HSG) that is deposited on a hemispherical polysilicon surface when silicon is deposited near 580 ° C in a low pressure chemical vapor deposition (LPCVD) system.

The temperature of 580 ° C corresponds to a transition zone in which the structure of the deposited silicon changes from amorphous to polycrystalline, which is a function of deposition parameters such as temperature and pressure, and the flow rate of SiH ₄ used as a seed material.

However, this method of increasing capacitance using the MPS has a very small process margin during the MPS growth process as the device is highly integrated.

In addition, it is difficult to deposit uniformly on the entire surface of the wafer, local non-growth regions occur, electrical bridges between storage nodes (SNs), and holes between SN oxides are generated. There is a limit to the capacitance increase.

The present invention has been proposed to solve such a problem of the conventional capacitor manufacturing process of the semiconductor device, a method of forming a capacitor of the semiconductor device to improve the characteristics of the device by increasing the surface area of the capacitor using a cleaning chemical The purpose is to provide.

According to an aspect of the present invention, there is provided a method of forming a capacitor of a semiconductor device, the method comprising: forming a first polysilicon layer to be connected to a storage node contact, and a first material affected by a cleaning liquid on the first polysilicon layer Stacking the second material layer with an unaffected layer, selectively patterning the stacked first and second material layers using a storage node mask, and performing a cleaning process to form a side surface of the first material layer Forming a part of the second polysilicon layer on the front surface including the first material layer partially etched from the side surface, and etching the first and second polysilicon layers to the first and second material layers. Forming a storage node having a curvature, and removing the first and second material layers.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1A is a TEM photograph after an etching process for forming a bit line.

1B is a TEM photograph after solvent cleaning performed after an etching process for forming a bit line, and FIG. 1C is a block diagram showing a cross-sectional structure of FIG. 1B.

The present invention is a method of increasing the capacitor surface area in order to increase the capacity of the capacitor, by using a wet-type etching in which Ti is attacked by Amine-based solvent cleaning chemical, for example, ACT solvent treatment. This is to increase the capacitor surface area.

The patterning of Ti by the solvent cleaning chemical used for this invention is demonstrated.

FIG. 1A shows a TEM photograph before amine-based solvent cleaning chemical after bit line etching, and FIG. 1B is a TEM photograph after 10 minutes of ACT solvent treatment after bit line etching.

From the picture, it can be seen that Ti is wet-etched by about 20 nm per side of TiN / Ti used as a bit line barrier metal.

FIG. 1C shows the cross-sectional configuration of FIG. 1B, which is an oxide film 1, Ti / TiN (2) (3) used as a bit line barrier layer, and W (4) used as a bit line, a bit line hard mask The nitride layer 5 used as a layer is laminated | stacked.

Here, it can be seen that Ti (2) on the oxide film 1 is attacked by an amine-based solvent cleaning chemical.

The present invention uses this principle, and is applied to increase the capacitor area by using only the Ti portion attacked during the ACT solvent treatment.

The capacitor forming process according to the present invention is as follows.

2A to 2F are cross-sectional views illustrating a process of forming a capacitor of a semiconductor device in accordance with a first embodiment of the present invention.

First, as shown in FIG. 2A, an interlayer insulating layer 21 is formed on a front surface of a cell transistor (not shown) and a storage node contact 20 is formed.

After depositing the first polysilicon 22 for forming the storage node, one selected from TiN, W, or an oxide layer is formed of a material that is not attacked by the Ti 23 and the ACT solvent, for example, to form an electrode pattern. It is formed of a sacrificial material layer 24 for.

Next, a storage node mask 25 is formed on the sacrificial material layer 24.

As shown in FIG. 2B, the sacrificial material layer pattern for forming a storage node is formed by sequentially etching the sacrificial material layer 24 and Ti 23 which are not attacked by the ACT solvent using the storage node mask 25. 24a) and Ti layer 23a are formed.

Subsequently, as shown in FIG. 2C, the ACT solvent treatment is performed for a predetermined time to form the Ti pattern layer 23b.

Here, it can be seen that the Ti pattern layer 23b is hit by a portion to the side by receiving the attack of the ACT solvent. In this case, the Ti attack degree is increased by increasing the ACT solvent deep time, thereby increasing the surface area.

Then, as shown in Figure 2d, a predetermined thickness of the second polysilicon 22a is deposited on the front.

Here, polysilicon has a property of being uniformly deposited, and is deposited on the sidewalls of the Ti pattern layer 23b having a shape hit into the side surface by the ACT solvent attack.

Subsequently, as shown in FIG. 2E, the first and second polysilicon layers 22 and 22a are plasma-etched with a blanket using a predetermined target. At this time, sufficient over-etching is performed to expose a material that is not attacked by the ACT solvent, that is, the sacrificial material layer 24a and the lower interlayer insulating layer 21.

As shown in FIG. 2F, the patterns 23a and 24a and the Ti pattern layer 23b for forming a storage node made of a material that is not attacked by the ACT solvent are removed by wet chemicals to form a first polysilicon pattern layer. The storage node 22b having an increased surface area formed of the second polysilicon pattern layer is formed.

In this case, when the material that is not attacked by the ACT solvent is W or TiN, all of the lower Ti may be removed using SPM (Sulfuric acid Hydrogen Peroxide Mixture) or APM (Ammonia Hydrogen Peroxide Mixture).

If the material is not attacked by the ACT solvent, the oxide film is first removed using a wet chemical (BOE) containing HF, and the bottom Ti can be removed using SPM or APM chemical.

There is no damage to polysilicon by SPM, APM and BOE at this stage.

And the capacitor forming process according to the second embodiment of the present invention will be described.

3A and 3B are cross-sectional views illustrating a capacitor for forming a semiconductor device in accordance with a second embodiment of the present invention.

When capacitor capacity is needed to be further increased, additional materials not attacked by Ti and ACT solvents are deposited to form a multi-layered structure, followed by subsequent processes.

As shown in FIG. 3A, after forming the storage node contact 30 in the contact hole of the interlayer insulating layer 31 and depositing the first polysilicon 32a for the electrode, the material is not attacked by Ti and ACT solvent. Repeatedly deposited.

After the plasma etching is performed by the SNC mask operation, an ACT solvent treatment is performed, and a second polysilicon layer 32b is deposited.

The first and second polysilicon layers 32a and 32b are blanket-etched to pattern the storage nodes.

As shown in FIG. 3B, the first and second Ti layers 33a and 33b and the first and second material layers 34a and 34b which are not subjected to the ACT solvent treatment are removed to form the storage node 35. do.

The present invention is to increase the surface area by increasing the curvature of the storage node by ACT solvent treatment after alternately depositing and patterning a material layer having a selectivity in the attack of the ACT solvent to increase the capacitor capacity.

In this way, the capacitor capacity can be increased by increasing the capacitor surface area.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above may increase the surface area by increasing the bending of the storage node by ACT solvent treatment after alternately depositing and patterning a material layer having a selectivity in the attack of the ACT solvent to increase the capacitor capacity.

This has the effect of effectively increasing the capacitor capacity by increasing the capacitor surface area in a simple process to ensure the operation reliability of the device and the ease of the device manufacturing process.

1A is a SEM photograph after an etching process for forming a bit line;

1B is a SEM photograph after solvent cleaning performed after an etching process for forming a bit line;

Figure 1c is a block diagram showing a cross-sectional structure of Figure 1b,

2A to 2F are cross-sectional views of a process for forming a capacitor of a semiconductor device according to a first embodiment of the present invention;

3A and 3B are cross-sectional views illustrating a process of forming a capacitor of a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: storage node contact 21: interlayer insulating layer

22: first polysilicon layer 22a: second polysilicon layer

23: Ti layer 24: sacrificial material layer

25: Storage Node Mask

Claims (6)

Forming a first polysilicon layer to be connected to the storage node contacts; Stacking a first material layer affected by the cleaning liquid and a second material layer unaffected on the first polysilicon layer; Selectively patterning the stacked first and second material layers using a storage node mask; Performing a cleaning process to partially etch the side surface of the first material layer; Forming a second polysilicon layer on the entire surface including the first material layer partially etched from the side surface; Etching the first and second polysilicon layers to form a storage node having curvature by the first and second material layers; And Removing the first and second material layers Capacitor formation method of a semiconductor device comprising a. The method of claim 1, And the first material layer is formed of Ti, and the second material layer is formed of any one of TiN, W, and an oxide film. The method of claim 1, ACT solvent is used in the cleaning process. The method of claim 1, And etching the first and second polysilicon layers to form the storage node by blanket etching the upper surface of the second material layer. The method of claim 2, When the second material layer is W or TiN, and the first material layer is Ti, And removing all of the first material layer Ti using SPM or APM. The method of claim 2, When the second material layer is an oxide film and the first material layer is Ti, The method of claim 1, wherein the oxide film is first removed using a wet chemical (BOE) containing HF, and the Ti is removed using SPM or APM chemical.