KR20050027384A - Chip size package having rerouting pad and stack thereof - Google Patents

Chip size package having rerouting pad and stack thereof Download PDF

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Publication number
KR20050027384A
KR20050027384A KR1020030063632A KR20030063632A KR20050027384A KR 20050027384 A KR20050027384 A KR 20050027384A KR 1020030063632 A KR1020030063632 A KR 1020030063632A KR 20030063632 A KR20030063632 A KR 20030063632A KR 20050027384 A KR20050027384 A KR 20050027384A
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South Korea
Prior art keywords
chip
circuit board
package
integrated circuit
pad
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KR1020030063632A
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Korean (ko)
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이영민
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삼성전자주식회사
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Priority to KR1020030063632A priority Critical patent/KR20050027384A/en
Publication of KR20050027384A publication Critical patent/KR20050027384A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A CSP(Chip Size Package) with a rerouting pad and a stack structure thereof are provided to reduce occupied surface area by forming ball terminals under a PCB(Printed Circuit Board) within a chip region. An IC(Integrated Circuit) chip(23) with rerouting pads(23b) is attached on a PCB(21). A second PCB(24) with contact pads(24a) for contacting electrically the rerouting pads is located over the IC chip. Bonding wires(26) connect electrically the PCB with the IC chip. An encapsulating part(27) is used for sealing the IC chip and the bonding wires. A plurality of ball terminals(28) are formed under the PCB. At this time, the ball terminals are within the IC chip region.

Description

재배선 패드를 갖는 칩 사이즈 패키지 및 그 적층체 {Chip Size Package Having Rerouting Pad And Stack Thereof}Chip Size Package Having Rerouting Pad And Stack Thereof}

본 발명은 반도체 패키지 적층 기술에 관한 것으로서, 보다 구체적으로는 재배선 패드를 갖는 칩 사이즈 패키지(chip size package; CSP) 및 그 적층체(stack) 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor package stacking technology, and more particularly, to a chip size package (CSP) having a redistribution pad and a stack structure thereof.

반도체 소자의 집적도를 향상시키기 위한 방법의 일환으로 적층 기술이 이용되고 있다. 적층 기술에는 여러 개의 집적회로 칩을 적층하는 칩 적층 방식과 여러 개의 패키지를 적층하는 패키지 적층 방식이 있다. 일반적으로 패키지 적층 방식은 칩 적층 방식에 비하여 칩의 전기적 특성과 동작 상태를 테스트하기에 용이하고 수율이 높다는 장점이 있다. 패키지 적층 방식에 의하여 제조된 패키지 적층체의 종래 구조가 도 1에 도시되어 있다.As a method of improving the degree of integration of semiconductor devices, a lamination technique is used. Stacking technologies include a chip stacking method for stacking multiple integrated circuit chips and a package stacking method for stacking multiple packages. In general, the package stacking method is easier to test the electrical characteristics and operating state of the chip than the chip stacking method and has a high yield. A conventional structure of a package laminate manufactured by the package lamination method is shown in FIG. 1.

도 1을 참조하면, 패키지 적층체(10)는 상부 패키지(11a)의 하부에 형성된 볼 단자(12)와 하부 패키지(11b)의 상부에 형성된 접속 패드(13a) 사이의 접합에 의하여 상하 패키지(11a, 11b) 사이의 연결을 구현한다. 볼 단자(12)는 회로 기판(13)의 밑면에 만들어진 볼 랜드(13b, ball land)에 형성되며, 접속 패드(13a)는 회로 기판(13)의 윗면에 만들어지고 비아(13c, via)를 통해 볼 랜드(13b)와 연결된다.Referring to FIG. 1, the package stack 10 may include an upper and lower packages (10) by bonding between a ball terminal 12 formed at a lower portion of the upper package 11a and a connection pad 13a formed at an upper portion of the lower package 11b. Implement the connection between 11a and 11b). The ball terminal 12 is formed on a ball land 13b made on the bottom surface of the circuit board 13, and the connection pad 13a is made on the top surface of the circuit board 13, and the vias 13c, vias are formed. It is connected with the ball land 13b.

집적회로 칩(14)은 회로 기판(13)의 중앙에 위치하며 본딩 와이어(15, bonding wire)를 통하여 회로 기판(13)의 윗면에 만들어진 본드 핑거(13d, bond finger)와 전기적으로 연결된다. 집적회로 칩(14)과 본딩 와이어(15)는 봉지제(16)로 밀봉되어 외부 환경으로부터 보호된다. 상부 패키지와 하부 패키지 사이에는 접착제(17)를 사용하기도 한다.The integrated circuit chip 14 is positioned at the center of the circuit board 13 and electrically connected to the bond fingers 13d (bond fingers) made on the upper surface of the circuit board 13 through bonding wires 15. The integrated circuit chip 14 and bonding wire 15 are sealed with an encapsulant 16 to protect it from the external environment. An adhesive 17 may be used between the upper package and the lower package.

그런데, 종래의 패키지 적층체(10)는 상하 패키지(11a, 11b)의 적층을 구현하기 위하여 볼 단자(12)와 접속 패드(13a) 등을 집적회로 칩(14)의 영역 바깥에 배치하고 있는 구조이다. 따라서, 패키지 적층체(10)의 크기가 커질 수밖에 없고 외부 기판에 실장할 때 실장 면적을 많이 차지하게 된다. 이는 반도체 제품의 소형화에 큰 제약으로 작용하고 있다.However, in the conventional package stack 10, the ball terminals 12, the connection pads 13a, and the like are disposed outside the region of the integrated circuit chip 14 in order to stack the upper and lower packages 11a and 11b. Structure. Therefore, the size of the package stack 10 is inevitably large and occupies a large amount of mounting area when mounted on an external substrate. This is a big constraint on the miniaturization of semiconductor products.

따라서, 본 발명의 목적은 패키지의 크기를 집적회로 칩의 수준으로 감소시킨 칩 사이즈 패키지 및 그 적층체를 구현하여 적층체의 실장 면적을 최소화하기 위한 것이다.Accordingly, an object of the present invention is to minimize the mounting area of a laminate by implementing a chip size package and a laminate thereof in which the size of the package is reduced to the level of an integrated circuit chip.

이러한 목적을 달성하기 위하여, 본 발명은 집적회로 칩 위에 재배선 패드를 만들고 그 위에 제2 회로 기판을 연결하여 다른 패키지가 적층될 수 있도록 한 칩 사이즈 패키지 및 그 적층체를 제공한다.To achieve this object, the present invention provides a chip size package and a stack thereof in which a redistribution pad is made on an integrated circuit chip and a second circuit board is connected thereon so that another package can be stacked.

본 발명에 따른 칩 사이즈 패키지는 회로 기판과, 회로 기판의 윗면에 부착되며 재배선 패드가 형성된 집적회로 칩과, 집적회로 칩의 위쪽에 위치하며 재배선 패드와 전기적으로 연결되는 접속 패드가 형성된 제2 회로 기판과, 회로 기판과 집적회로 칩을 전기적으로 연결하는 본딩 와이어와, 집적회로 칩과 본딩 와이어를 밀봉하는 봉지제, 및 회로 기판의 밑면에 형성된 볼 단자를 포함한다. 특히, 재배선 패드는 집적회로 칩의 윗면 전체에 걸쳐 형성되며, 볼 단자는 집적회로 칩의 영역을 벗어나지 않고 회로 기판의 밑면에 형성되는 것이 특징이다.The chip size package according to the present invention comprises a circuit board, an integrated circuit chip attached to an upper surface of the circuit board and having a redistribution pad formed thereon, and a connection pad positioned above the integrated circuit chip and electrically connected to the redistribution pad. And a circuit board, a bonding wire for electrically connecting the circuit board and the integrated circuit chip, an encapsulant for sealing the integrated circuit chip and the bonding wire, and a ball terminal formed on the bottom surface of the circuit board. In particular, the redistribution pad is formed over the entire upper surface of the integrated circuit chip, and the ball terminal is formed on the bottom surface of the circuit board without leaving the area of the integrated circuit chip.

본 발명에 따른 칩 사이즈 패키지에 있어서, 집적회로 칩과 제2 회로 기판 사이의 연결 수단은 접속 범프 또는 이방성 전도막이 사용될 수 있다.In the chip size package according to the present invention, a connection bump or an anisotropic conductive film may be used as the connection means between the integrated circuit chip and the second circuit board.

본 발명에 따른 칩 사이즈 패키지 적층체는 이와 같은 칩 사이즈 패키지를 두 개 이상 사용하여 아래쪽 패키지의 제2 회로 기판 위에 위쪽 패키지의 볼 단자를 접합함으로써 적층을 구현한다.The chip size package laminate according to the present invention uses two or more such chip size packages to achieve lamination by bonding the ball terminals of the upper package onto the second circuit board of the lower package.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. 첨부 도면에 있어서 일부 구성요소는 도면의 명확한 이해를 돕기 위해 다소 과장되거나 개략적으로 도시되거나 또는 생략되었으며, 동일한 구성요소 또는 대응하는 구성요소는 동일한 참조 번호를 사용하였다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, some of the components are somewhat exaggerated, schematically illustrated or omitted in order to facilitate a clear understanding of the drawings, and the same components or corresponding components have the same reference numerals.

실시예Example

먼저, 본 발명에 따른 칩 사이즈 패키지의 적층체를 설명하기에 앞서, 적층체에 사용되는 개별 패키지를 설명하기로 한다. 본 발명에 따른 개별 패키지는 재배선 패드를 이용한 칩 사이즈 패키지로서, 도 2에 도시되어 있다.First, prior to describing the stack of chip size packages according to the invention, the individual packages used in the stack will be described. The individual package according to the invention is shown in FIG. 2 as a chip size package using a redistribution pad.

도 2를 참조하면, 칩 사이즈 패키지(20)는 회로 기판(21)의 윗면에 접착제(22)를 이용하여 집적회로 칩(23)을 부착하고, 본딩 와이어(26)를 이용하여 집적회로 칩(23)과 회로 기판(21)을 전기적으로 연결한 구조를 갖는다. 집적회로 칩(23)과 본딩 와이어(26)는 봉지제(27)로 밀봉되어 외부 환경으로부터 보호되며, 회로 기판(21)의 밑면에는 솔더 볼과 같은 볼 단자(28)가 규칙적으로 배치되어 형성된다.Referring to FIG. 2, the chip size package 20 attaches the integrated circuit chip 23 to the top surface of the circuit board 21 using the adhesive 22, and uses the bonding wire 26 to form the integrated circuit chip ( 23 and the circuit board 21 are electrically connected. The integrated circuit chip 23 and the bonding wire 26 are sealed with an encapsulant 27 to be protected from the external environment, and the bottom surface of the circuit board 21 is formed by regularly arranging ball terminals 28 such as solder balls. do.

접착제(22)로는 통상적인 에폭시 접착제 등을 사용할 수 있다. 본딩 와이어(26)를 이용한 전기적 연결 방식으로는 잘 알려진 범프 리버스 와이어 본딩(bump reverse wire bonding) 방식을 채택할 수 있다. 봉지제(27)는 노즐을 이용한 디스펜싱(dispensing) 방식, 스크린 프린팅(screen printing) 방식 등으로 형성할 수 있으며, 볼 단자(28)는 볼 배치(ball placement), 도금(plating), 스텐실 프린팅(stencil printing), 메탈 젯(metal jet)과 같은 방식으로 형성할 수 있다.As the adhesive 22, a conventional epoxy adhesive or the like can be used. As the electrical connection method using the bonding wire 26, a well-known bump reverse wire bonding method may be adopted. The encapsulant 27 may be formed by a dispensing method using a nozzle, a screen printing method, or the like, and the ball terminal 28 may be ball placement, plating, and stencil printing. (stencil printing), metal jet (metal jet) can be formed in the same manner.

회로 기판(21)에는 본드 핑거(21a)와 볼 랜드(21b)가 형성되어 있다. 본드 핑거(21a)는 본딩 와이어(26)가 접속되는 부위이며, 볼 랜드(21b)는 볼 단자(28)가 형성되는 부위이다. 볼 단자(28)는 모두 집적회로 칩(23)의 아래쪽에 위치한다. 따라서, 칩(23) 수준의 크기로 패키지(20)의 크기를 감소시킨 칩 사이즈 패키지를 구현할 수 있다.The bond finger 21a and the ball land 21b are formed in the circuit board 21. The bond finger 21a is a portion where the bonding wire 26 is connected, and the ball land 21b is a portion where the ball terminal 28 is formed. The ball terminals 28 are all located below the integrated circuit chip 23. Therefore, the chip size package having the size of the package 20 reduced to the size of the chip 23 may be implemented.

본 발명의 칩 사이즈 패키지(20)에 사용되는 집적회로 칩(23)은 윗면에 재배선 패드(23b)가 만들어져 있는 것이 특징이다. 재배선 패드(23b)가 형성된 집적회로 칩(23)의 평면 구조가 도 3에 도시되어 있다. 도 3에 도시된 바와 같이, 집적회로 칩(23)의 윗면에는 통상적인 칩 패드(23a)들이 윗면 가장자리를 따라 배열된다. 칩 패드(23a)는 본딩 와이어(도 2의 26)를 통하여 회로 기판(도 2의 21)과 전기적으로 연결되는 부위이다. 한편, 재배선 패드(23b)는 집적회로 칩(23) 윗면의 가장자리를 제외하고 윗면 전 영역에 걸쳐 형성된다. 재배선 패드(23b)의 형성 방법은 POC(pad on circuit) 공정으로 잘 알려져 있으므로 자세한 설명은 생략한다. 재배선 패드(23b)는 내부 배선(도시되지 않음)을 통하여 칩 패드(23a)와 전기적으로 연결되어 있으며, 패키지 적층을 위하여 제2 회로 기판(도 2의 24)과 연결되는 부위이다.The integrated circuit chip 23 used in the chip size package 20 of the present invention is characterized in that a redistribution pad 23b is formed on an upper surface thereof. A planar structure of the integrated circuit chip 23 on which the redistribution pad 23b is formed is shown in FIG. As shown in Fig. 3, on the top surface of the integrated circuit chip 23, conventional chip pads 23a are arranged along the top edge. The chip pad 23a is a portion that is electrically connected to the circuit board 21 of FIG. 2 through the bonding wire 26 of FIG. 2. Meanwhile, the redistribution pad 23b is formed over the entire area of the upper surface except for the edge of the upper surface of the integrated circuit chip 23. Since the method of forming the redistribution pad 23b is well known as a pad on circuit (POC) process, a detailed description thereof will be omitted. The redistribution pad 23b is electrically connected to the chip pad 23a through an internal wiring (not shown), and is a portion connected to the second circuit board 24 of FIG. 2 for package stacking.

다시 도 2를 참조하면, 집적회로 칩(23)의 재배선 패드(23b)에는 제2 회로 기판(24)이 연결된다. 제2 회로 기판(24)의 윗면과 밑면에는 집적회로 칩(23)의 재배선 패드(23b)와 대응하여 각각 접속 패드(24a, 24b)가 형성되어 있다. 밑면 접속 패드(24a)는 재배선 패드(23b)와 대응하는 위치에 형성되며, 윗면 접속 패드(24b)는 적층될 다른 패키지의 볼 단자(28)와 대응하는 위치에 형성된다. 윗면과 밑면 접속 패드(24a, 24b)는 비아(via, 도시되지 않음)를 통하여 서로 연결된다.Referring back to FIG. 2, a second circuit board 24 is connected to the redistribution pad 23b of the integrated circuit chip 23. Connection pads 24a and 24b are formed on the top and bottom surfaces of the second circuit board 24 to correspond to the redistribution pad 23b of the integrated circuit chip 23, respectively. The bottom connection pad 24a is formed at a position corresponding to the redistribution pad 23b, and the top connection pad 24b is formed at a position corresponding to the ball terminal 28 of another package to be stacked. Top and bottom connection pads 24a and 24b are connected to each other through vias (not shown).

제2 회로 기판(24)의 밑면 접속 패드(24a)와 집적회로 칩(23)의 재배선 패드(23b)는 여러 가지 방식을 이용하여 전기적으로 연결될 수 있다. 도 4a 및 도 4b는 두 가지 예를 보여주고 있다. 도 4a에 도시된 예는 솔더 볼과 같은 접속 범프(25a)를 이용하는 방식이고, 도 4b에 도시된 예는 이방성 전도막(25b, ACF; anisotropic conductive film)을 이용하는 방식이다. 도 4a의 방식은 제2 회로 기판(24)의 밑면 접속 패드(24a)에 미리 접속 범프(25a)를 형성한 다음, 접속 범프(25a)를 집적회로 칩(23)의 재배선 패드(23b)에 접합하는 방식이다. 도 4b의 방식은 절연 필름 내부에 미세한 전도성 볼들이 분포된 이방성 전도막(25b)을 이용하여 밑면 접속 패드(24a)와 재배선 패드(23b)를 연결하는 방식이다. 본 발명을 설명하는 도면들은 도 4a의 방식을 예시하고 있으나, 도 4b의 방식도 가능함은 물론이다.The bottom connection pad 24a of the second circuit board 24 and the redistribution pad 23b of the integrated circuit chip 23 may be electrically connected using various methods. 4A and 4B show two examples. The example shown in FIG. 4A uses a connection bump 25a such as a solder ball, and the example shown in FIG. 4B uses an anisotropic conductive film 25B (ACF). In the method of FIG. 4A, the connection bumps 25a are formed in advance on the bottom connection pads 24a of the second circuit board 24, and then the connection bumps 25a are connected to the redistribution pads 23b of the integrated circuit chip 23. It is a way to join. 4B is a method of connecting the bottom connection pad 24a and the redistribution pad 23b by using the anisotropic conductive film 25b in which fine conductive balls are distributed inside the insulating film. The drawings illustrating the present invention illustrate the scheme of FIG. 4A, but of course the scheme of FIG. 4B is also possible.

이상 설명한 바와 같은 구조를 갖는 칩 사이즈 패키지(20)는 적층체를 구현하기에 적합하다. 본 발명에 따른 칩 사이즈 패키지(20)의 적층체(30) 구조가 도 5에 도시되어 있다. 도 5는 모두 4개의 칩 사이즈 패키지(20a, 20b, 20c, 20d)를 사용하여 적층체(30)를 구성한 예이다.The chip size package 20 having the structure as described above is suitable for implementing a laminate. The structure of the stack 30 of the chip size package 20 according to the invention is shown in FIG. FIG. 5 shows an example in which the laminate 30 is configured by using four chip size packages 20a, 20b, 20c, and 20d.

도 5에 도시된 바와 같이, 아래쪽 패키지(20a)의 제2 회로 기판(24)에 위쪽 패키지(20b)의 볼 단자(28)를 접합하여 패키지를 적층시킨다. 즉, 윗쪽 패키지(20b)의 볼 단자(28)는 아래쪽 제2 회로 기판(24)의 윗면 접속 패드(24b)에 접합된다. 전술한 바와 같이, 집적회로 칩(23)에는 재배선 패드(23b)가 만들어져 있고, 제2 회로 기판(24)은 재배선 패드(23b)와 연결되어 있으므로, 볼 단자(28)와 제2 회로 기판(24)의 접합을 통하여 칩 사이즈 패키지(20a, 20b, 20c, 20d)의 적층이 가능하다.As shown in FIG. 5, the ball terminals 28 of the upper package 20b are bonded to the second circuit board 24 of the lower package 20a to stack the packages. That is, the ball terminal 28 of the upper package 20b is bonded to the upper surface connection pad 24b of the lower second circuit board 24. As described above, since the redistribution pad 23b is made in the integrated circuit chip 23, and the second circuit board 24 is connected to the redistribution pad 23b, the ball terminal 28 and the second circuit are provided. Stacking of the chip size packages 20a, 20b, 20c, and 20d is possible through the bonding of the substrate 24.

도 6a 내지 도 6d는 도 5에 도시된 칩 사이즈 패키지 적층체(30)의 제조 공정을 보여주고 있다. 먼저, 도 6a에 도시된 바와 같이, 회로 기판(21)의 윗면에 접착제(22)를 이용하여 집적회로 칩(23)을 부착한다. 그리고 나서, 도 6b에 도시된 바와 같이, 집적회로 칩(23)의 윗면에 제2 회로 기판(24)을 접합한다. 이 때의 접합 매개체는 접속 범프(25a) 또는 이방성 전도막 등이 사용된다.6A through 6D show the manufacturing process of the chip size package stack 30 shown in FIG. First, as shown in FIG. 6A, the integrated circuit chip 23 is attached to the upper surface of the circuit board 21 using the adhesive 22. Then, as shown in FIG. 6B, the second circuit board 24 is bonded to the upper surface of the integrated circuit chip 23. At this time, as the bonding medium, a connection bump 25a, an anisotropic conductive film, or the like is used.

계속해서, 도 6c에 도시된 바와 같이, 본딩 와이어(26)를 이용하여 집적회로 칩(23)과 회로 기판(21)을 전기적으로 연결한 뒤, 집적회로 칩(23)과 본딩 와이어(26)를 보호하기 위하여 봉지제(27)를 형성한다. 집적회로 칩(23)과 제2 회로 기판(24) 사이의 접합 매개체로서 접속 범프(25a)가 사용되는 경우, 봉지제(27)는 집적회로 칩(23)과 제2 회로 기판(24) 사이의 틈에도 스며들어 접속 범프(25a)를 고정하게 된다. 봉지제(27)를 형성한 후, 회로 기판(21)의 밑면에 볼 단자(28)를 형성한다.Subsequently, as shown in FIG. 6C, the integrated circuit chip 23 and the circuit board 21 are electrically connected using the bonding wire 26, and then the integrated circuit chip 23 and the bonding wire 26 are used. In order to protect the encapsulant 27 is formed. When the connection bump 25a is used as a junction medium between the integrated circuit chip 23 and the second circuit board 24, the encapsulant 27 is formed between the integrated circuit chip 23 and the second circuit board 24. The connection bumps 25a are fixed to the gaps of the holes. After the sealing agent 27 is formed, the ball terminal 28 is formed in the lower surface of the circuit board 21.

이러한 과정을 거쳐 개별 칩 사이즈 패키지(20)를 완성한 다음, 도 6d에 도시된 바와 같이, 칩 사이즈 패키지 적층체(30)를 만든다. 즉, 아래쪽 패키지(20a)의 제2 회로 기판(24) 윗면 접속 패드(24b)에 위쪽 패키지(20b)의 볼 단자(28)를 접합하여 패키지를 적층시킨다. 이러한 방식으로 원하는 개수만큼의 패키지 적층을 구현할 수 있다.After the individual chip size package 20 is completed through this process, as shown in FIG. 6D, the chip size package stack 30 is formed. That is, the ball terminals 28 of the upper package 20b are bonded to the upper connection pads 24b of the second circuit board 24 of the lower package 20a to stack the packages. In this way, the desired number of package stacks can be implemented.

이상 설명한 바와 같이, 본 발명은 집적회로 칩 위에 재배선 패드를 만들고 그 위에 제2 회로 기판을 연결한 후, 제2 회로 기판 위에 다른 패키지의 볼 단자를 접합하여 패키지 적층을 구현한다. 따라서, 상하 패키지의 적층을 매개하는 볼 단자가 집적회로 칩의 영역을 벗어나지 않고 회로 기판의 하부에 형성될 수 있으므로, 칩 사이즈의 패키지 및 그 적층체를 구현할 수 있다.As described above, the present invention implements package stacking by making a redistribution pad on an integrated circuit chip, connecting a second circuit board thereon, and bonding ball terminals of another package on the second circuit board. Therefore, the ball terminal for stacking the upper and lower packages can be formed in the lower portion of the circuit board without departing from the area of the integrated circuit chip, so that a chip size package and a stack thereof can be implemented.

본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

도 1은 종래기술에 따른 패키지 적층체의 한 예를 나타내는 단면도이다.1 is a cross-sectional view showing an example of a package laminate according to the prior art.

도 2는 본 발명의 실시예에 따른 재배선 패드를 갖는 칩 사이즈 패키지를 나타내는 단면도이다.2 is a cross-sectional view illustrating a chip size package having a redistribution pad according to an embodiment of the present invention.

도 3은 도 2에 도시된 칩 사이즈 패키지에서 재배선 패드가 형성된 집적회로 칩을 나타내는 평면도이다.3 is a plan view illustrating an integrated circuit chip in which redistribution pads are formed in the chip size package illustrated in FIG. 2.

도 4a 및 도 4b는 도 2에 도시된 칩 사이즈 패키지에서 제2 회로 기판과 재배선 패드를 연결하는 두 가지 예를 보여주는 단면도이다.4A and 4B are cross-sectional views illustrating two examples of connecting the second circuit board and the redistribution pad in the chip size package shown in FIG. 2.

도 5는 도 2에 도시된 칩 사이즈 패키지를 여러 개 적층한 구조로서 본 발명의 실시예에 따른 칩 사이즈 패키지 적층체를 나타내는 단면도이다.5 is a cross-sectional view illustrating a chip size package stack according to an exemplary embodiment of the present invention as a structure in which a plurality of chip size packages illustrated in FIG. 2 are stacked.

도 6a 내지 도 6d는 도 5에 도시된 칩 사이즈 패키지 적층체의 제조 공정을 보여주는 단면도이다.6A through 6D are cross-sectional views illustrating a manufacturing process of the chip size package laminate shown in FIG. 5.

<도면에 사용된 참조 번호의 설명><Description of Reference Number Used in Drawing>

10: 패키지 적층체(package stack) 11a, 11b: 개별 패키지10: package stack 11a, 11b: individual package

12: 볼 단자(ball terminal) 13: 회로 기판(circuit substrate)12: ball terminal 13: circuit substrate

13a: 접속 패드(connection pad) 13b: 볼 랜드(ball land)13a: connection pad 13b: ball land

13c: 비아(via) 13d: 본드 핑거(bond finger)13c: via 13d: bond fingers

14: 집적회로 칩(IC chip) 15: 본딩 와이어(bonding wire)14: IC chip 15: bonding wire

16: 봉지제(encapsulant) 17: 접착제(adhesive)16: encapsulant 17: adhesive

20, 20a, 20b, 20c, 20d: 칩 사이즈 패키지(chip size package)20, 20a, 20b, 20c, 20d: chip size package

21: 제1 회로 기판(first circuit substrate)21: first circuit substrate

21a: 본드 핑거(bond finger) 21b: 볼 랜드(ball land)21a: bond finger 21b: ball land

22: 접착제(adhesive) 23: 집적회로 칩(IC chip)22: adhesive 23: integrated circuit chip (IC chip)

23a: 칩 패드(chip pad) 23b: 재배선 패드(rerouting pad)23a: chip pad 23b: rerouting pad

24: 제2 회로 기판(second circuit substrate)24: second circuit substrate

24a, 24b: 접속 패드(connection pad)24a, 24b: connection pad

25a: 접속 범프(connection bump) 25b: 이방성 전도막(ACF)25a: connection bump 25b: anisotropic conductive film (ACF)

26: 본딩 와이어(bonding wire) 27: 봉지제(encapsulant)26: bonding wire 27: encapsulant

28: 볼 단자(ball terminal) 30: 칩 사이즈 패키지 적층체28: ball terminal 30: chip size package stack

Claims (5)

회로 기판;A circuit board; 상기 회로 기판의 윗면에 부착되며, 재배선 패드가 형성된 집적회로 칩;An integrated circuit chip attached to an upper surface of the circuit board and having a redistribution pad formed therein; 상기 집적회로 칩의 위쪽에 위치하며, 상기 재배선 패드와 전기적으로 연결되는 접속 패드가 형성된 제2 회로 기판;A second circuit board positioned above the integrated circuit chip and having a connection pad electrically connected to the redistribution pad; 상기 회로 기판과 상기 집적회로 칩을 전기적으로 연결하는 본딩 와이어;Bonding wires electrically connecting the circuit board and the integrated circuit chip; 상기 집적회로 칩과 상기 본딩 와이어를 밀봉하는 봉지제; 및An encapsulant sealing the integrated circuit chip and the bonding wire; And 상기 회로 기판의 밑면에 형성된 볼 단자를 포함하며,It includes a ball terminal formed on the bottom surface of the circuit board, 상기 재배선 패드는 상기 집적회로 칩의 윗면 전체에 걸쳐 형성되며, 상기 볼 단자는 상기 집적회로 칩의 영역을 벗어나지 않고 상기 회로 기판의 밑면에 형성되는 것을 특징으로 하는 칩 사이즈 패키지.The redistribution pad is formed over the entire upper surface of the integrated circuit chip, wherein the ball terminal is formed on the bottom surface of the circuit board without leaving the area of the integrated circuit chip. 제1 항에 있어서, 상기 집적회로 칩과 상기 제2 회로 기판 사이의 연결 수단은 접속 범프인 것을 특징으로 하는 칩 사이즈 패키지.The chip size package of claim 1, wherein the connecting means between the integrated circuit chip and the second circuit board is a connection bump. 제1 항에 있어서, 상기 집적회로 칩과 상기 제2 회로 기판 사이의 연결 수단은 이방성 전도막인 것을 특징으로 하는 칩 사이즈 패키지.The chip size package according to claim 1, wherein the connecting means between the integrated circuit chip and the second circuit board is an anisotropic conductive film. 제1 항 내지 제3 항 중의 어느 하나에 기재된 칩 사이즈 패키지를 두 개 이상 적층한 칩 사이즈 패키지 적층체로서, 아래쪽 패키지의 제2 회로 기판 위에 위쪽 패키지의 볼 단자를 접합하여 적층을 구현하는 것을 특징으로 하는 칩 사이즈 패키지 적층체.A chip size package laminate in which two or more chip size packages according to any one of claims 1 to 3 are laminated, and the ball terminals of the upper package are bonded to the second circuit board of the lower package to implement lamination. A chip size package laminated body made of. 제4 항에 있어서, 위쪽 패키지의 볼 단자는 아래쪽 패키지의 제2 회로 기판의 접속 패드에 접합되는 것을 특징으로 하는 칩 사이즈 패키지 적층체.The chip size package laminate according to claim 4, wherein the ball terminal of the upper package is bonded to the connection pad of the second circuit board of the lower package.
KR1020030063632A 2003-09-15 2003-09-15 Chip size package having rerouting pad and stack thereof KR20050027384A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100800473B1 (en) * 2006-06-30 2008-02-04 삼성전자주식회사 Stack chip having redistributed chip pad and stack chip package using the same
US7649248B2 (en) 2005-08-08 2010-01-19 Samsung Electronics Co., Ltd. Stack package implementing conductive support
US8053881B2 (en) 2008-09-24 2011-11-08 Samsung Electronics Co., Ltd. Semiconductor package and method for manufacturing the same
US8253232B2 (en) 2009-05-08 2012-08-28 Samsung Electronics Co., Ltd. Package on package having a conductive post with height lower than an upper surface of an encapsulation layer to prevent circuit pattern lift defect and method of fabricating the same
US8759959B2 (en) 2010-03-02 2014-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor packages

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7649248B2 (en) 2005-08-08 2010-01-19 Samsung Electronics Co., Ltd. Stack package implementing conductive support
KR100800473B1 (en) * 2006-06-30 2008-02-04 삼성전자주식회사 Stack chip having redistributed chip pad and stack chip package using the same
US8053881B2 (en) 2008-09-24 2011-11-08 Samsung Electronics Co., Ltd. Semiconductor package and method for manufacturing the same
US8253232B2 (en) 2009-05-08 2012-08-28 Samsung Electronics Co., Ltd. Package on package having a conductive post with height lower than an upper surface of an encapsulation layer to prevent circuit pattern lift defect and method of fabricating the same
US8759959B2 (en) 2010-03-02 2014-06-24 Samsung Electronics Co., Ltd. Stacked semiconductor packages
US9190401B2 (en) 2010-03-02 2015-11-17 Samsung Electronics Co., Ltd. Stacked semiconductor packages

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