KR19990001440A - Wiring Formation Method of Semiconductor Device - Google Patents

Wiring Formation Method of Semiconductor Device Download PDF

Info

Publication number
KR19990001440A
KR19990001440A KR1019970024757A KR19970024757A KR19990001440A KR 19990001440 A KR19990001440 A KR 19990001440A KR 1019970024757 A KR1019970024757 A KR 1019970024757A KR 19970024757 A KR19970024757 A KR 19970024757A KR 19990001440 A KR19990001440 A KR 19990001440A
Authority
KR
South Korea
Prior art keywords
wiring
forming
sacrificial layer
cell region
layer
Prior art date
Application number
KR1019970024757A
Other languages
Korean (ko)
Other versions
KR100231134B1 (en
Inventor
윤탁현
양원석
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019970024757A priority Critical patent/KR100231134B1/en
Publication of KR19990001440A publication Critical patent/KR19990001440A/en
Application granted granted Critical
Publication of KR100231134B1 publication Critical patent/KR100231134B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 배선 형성 방법에 관한 것으로서 셀영역과 주변영역을 포함하는 기판 상에 절연막, 배선층 및 희생층을 순차적으로 형성하는 공정과, 상기 희생층을 상기 셀영역의 소정 부분에만 남도록 패터닝하고 상기 패터닝된 희생층의 측면에 측벽을 형성하는 공정과, 상기 패터닝된 희생층을 제거하고 셀영역 내의 상기 측벽의 일측 또는 타측 끝의 소정 부분과 상기 주변영역 내의 소정 부분을 덮는 패터닝된 감광막을 형성하는 공정과, 상기 측벽 및 상기 감광막을 마스크로 사용하여 배선층을 패터닝하여 상기 셀영역 내에 제 1 배선 및 접촉부와 상기 주변 영역 내에 제 2 배선을 형성하는 공정을 구비한다. 따라서, 셀영역 내의 제 1 배선의 선폭을 좁게 하여 집적도를 향상시키면서 접촉부와 주변영역 내의 배선의 선폭을 크게 형성하여 소자 특성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring in a semiconductor device, the method comprising sequentially forming an insulating film, a wiring layer, and a sacrificial layer on a substrate including a cell region and a peripheral region, and patterning the sacrificial layer to remain only in a predetermined portion of the cell region. And forming a sidewall on a side of the patterned sacrificial layer, and removing the patterned sacrificial layer, and patterning a photosensitive film covering a predetermined portion of one side or the other end of the sidewall in the cell region and a predetermined portion in the peripheral region. And forming a wiring layer using the sidewalls and the photosensitive film as a mask to form a first wiring and a contact portion in the cell region and a second wiring in the peripheral region. Therefore, the line width of the first wiring in the cell region can be narrowed to improve the degree of integration, and the line width of the wiring in the contact portion and the peripheral region can be made large to improve the device characteristics.

Description

반도체장치의 배선 형성 방법Wiring Formation Method of Semiconductor Device

본 발명은 반도체장치의 배선 형성 방법에 관한 것으로서, 특히, 셀영역 내의 배선의 폭을 좁게 하면서 배선의 접촉부와 주변영역 내의 배선의 선폭을 넓게 형성하는 반도체장치의 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring in a semiconductor device, and more particularly, to a method of forming a wiring in a semiconductor device in which the line width of the wiring in the contact portion of the wiring and the wiring in the peripheral region is made wide.

반도체소자의 집적도가 증가함에 따라 단위 셀의 크기가 작아진다. 단위 셀의 크기의 축소에 따라 셀영역 내의 배선의 선폭도 감소하게 된다. 그러므로, 측벽(side wall)을 이용하여 배선을 노광 장비 한계 이하로 형성하는 방법이 개발되었다. 상기에서 배선을 노광 장비 한계 이하로 좁게 형성하면 단위 셀의 크기를 감소시킬 수 있어 집적도를 향상시킬 수 있다.As the degree of integration of semiconductor devices increases, the unit cell size decreases. As the size of the unit cell is reduced, the line width of the wiring in the cell region is also reduced. Therefore, a method has been developed that uses side walls to form wiring below the exposure equipment limit. If the wiring is formed to be narrower than the exposure equipment limit, the size of the unit cell can be reduced, thereby improving the degree of integration.

이에 반하여, 셀영역 내에 형성된 배선의 일측 끝단에 전기적으로 연결되게 형성되어 이 후에 형성되는 배선과 접촉되는 접촉부는 배선의 선폭 보다 크게 형성되어야 한다. 이는 접촉부 상에 형성되는 접촉구가 노광 공정의 한계에 의해 최소 크기가 배선의 선폭 보다 크게 때문에 중첩 마진을 고려하여야 한다. 또한, 주변영역에 형성되는 구동 트랜지스터는 집적도의 향상 보다는 소자의 특성이 중요하므로 배선의 선폭을 셀영역 내의 배선의 선폭 보다 크게 형성하여야 한다.On the contrary, the contact portion formed to be electrically connected to one end of the wiring formed in the cell region and in contact with the wiring formed thereafter should be formed larger than the line width of the wiring. This should consider the overlap margin because the contact hole formed on the contact portion has a minimum size larger than the line width of the wiring due to the limitation of the exposure process. In addition, the driving transistor formed in the peripheral region is important to the characteristics of the device rather than to improve the degree of integration, so the line width of the wiring should be larger than the line width of the wiring in the cell region.

그러나, 상술한 종래의 측벽을 이용한 반도체장치의 배선 형성 방법은 셀영역 내의 배선의 선폭 뿐만 아니라 접촉부와 주변영역 내의 배선의 선폭도 좁게 형성하는 문제점이 있었다.However, the above-described conventional wiring forming method of a semiconductor device using sidewalls has a problem in that not only the line width of the wiring in the cell region but also the line width of the wiring in the contact portion and the peripheral region is narrow.

따라서, 본 발명의 목적은 셀영역 내의 배선의 선폭을 좁게 하면서 접촉부와 주변영역 내의 배선의 선폭을 크게 형성할 수 있는 반도체장치의 배선 형성 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for forming a wiring in a semiconductor device which can increase the line width of the wiring in the contact portion and the peripheral region while narrowing the line width of the wiring in the cell region.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 배선 형성 방법은 셀 영역과 주변영역을 포함하는 기판 상에 절연막, 배선층 및 희생층을 순차적으로 형성하는 공정과, 상기 희생층을 상기 셀영역의 소정 부분에만 남도롤 패터닝하고 상기 패터닝된 희생층의 측면에 측벽을 형성하는 공정과, 상기 패터닝된 희생층을 제거하고 셀영역 내의 상기 측벽의 일측 또는 타측 끝의 소정 부분과 상기 주변영역 내의 소정 부분을 덮는 패터닝된 감광막을 형성하는 공정과, 상기 측벽 및 상기 감광막을 마스크로 사용하여 배선층을 패터닝하여 상기 셀영역 내에 제 1 배선 및 접촉부와 상기 주변영역 내에 제 2 배선을 형성하는 공정을 구비한다.According to an aspect of the present invention, there is provided a method of forming a wiring in a semiconductor device, the method including sequentially forming an insulating film, a wiring layer, and a sacrificial layer on a substrate including a cell region and a peripheral region, and forming the sacrificial layer in the cell region. Patterning the south roll only on a predetermined portion and forming a sidewall on the side of the patterned sacrificial layer, removing the patterned sacrificial layer, and a predetermined portion at one or the other end of the sidewall in the cell region and a predetermined portion in the peripheral region. Forming a patterned photoresist film covering the gap; and forming a first wiring and a contact portion in the cell region and a second wiring in the peripheral region by patterning a wiring layer using the sidewall and the photosensitive film as a mask.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따라 형성된 반도체장치의 평면도1 is a plan view of a semiconductor device formed in accordance with the present invention.

도 2A 내지 도 2D는 도 1을 X-X선을 따라 본 발명에 따른 반도체장치의 배선 형성 방법을 도시하는 공정도2A to 2D are process drawings showing the wiring forming method of the semiconductor device according to the present invention along the X-X line of FIG.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11 : 기판13 : 절연막11 substrate 13 insulating film

15 : 배선층17 : 희생층15: wiring layer 17: sacrificial layer

19 : 측벽21 : 감광막19 side wall 21 photosensitive film

23 : 제 1 배선25 : 접촉부23: first wiring 25: contact portion

27 : 제 2 배선CA : 셀영역27: second wiring CA: cell area

PA : 주변영역PA: surrounding area

도 1은 본 발명에 따라 형성된 반도체장치의 평면도이다.1 is a plan view of a semiconductor device formed in accordance with the present invention.

반도체장치는 셀영역(CA)과 주변영역(PA)을 갖는 기판(11) 상에 절연막(13)이 형성된다. 상기에서 기판(11)은 불순물이 도핑된 확산영역(도시되지 않음)이 형성된 반도체기판이거나, 또는, 하부의 다른 배선일 수도 있다. 절연막(13) 상의 셀영역(CA)에 제 1 배선(23)과 접촉부(25)가 형성되고 주변영역(PA)에 제 2 배선(27)이 형성된다.In the semiconductor device, an insulating layer 13 is formed on the substrate 11 having the cell region CA and the peripheral region PA. The substrate 11 may be a semiconductor substrate on which a diffusion region (not shown) doped with impurities is formed, or may be another wiring below. The first wiring 23 and the contact portion 25 are formed in the cell area CA on the insulating layer 13, and the second wiring 27 is formed in the peripheral area PA.

제 1 배선(23)은 절연막(13) 상의 셀영역(CA)에 다수 개가 형성된다. 접촉부(25)는 절연막(13) 상의 셀영역(CA)에 제 1 배선(23)의 일측 또는 타측에 연결되게 형성된다. 즉, 접촉부(25)는 제 1 배선(23)의 홀수 번째의 일측과 연결되게 형성되고, 짝수 번째의 타측과 연결되게 형성된다. 접촉부(25)는 제 1 배선(23)의 선폭과 무관하게 큰 선폭을 갖도록 형성된다.A plurality of first wirings 23 are formed in the cell region CA on the insulating film 13. The contact portion 25 is formed to be connected to one side or the other side of the first wiring 23 in the cell region CA on the insulating layer 13. That is, the contact portion 25 is formed to be connected to one side of the odd-numbered side of the first wiring 23, and is formed to be connected to the other side of the even-numbered side. The contact portion 25 is formed to have a large line width irrespective of the line width of the first wiring 23.

제 2 배선(27)은 절연막(13) 상의 주변영역(PA)에 형성된다. 제 2 배선(27)도 제 1 배선(23)의 선폭과 무관하게 큰 선폭을 갖도록 형성된다.The second wiring 27 is formed in the peripheral area PA on the insulating film 13. The second wiring 27 is also formed to have a large line width irrespective of the line width of the first wiring 23.

도 2A 내지 도 2D는 도 1을 X-X선을 따라 본 발명에 따른 반도체장치의 배선 형성 방법을 도시하는 공정도이다.2A to 2D are process drawings showing the wiring forming method of the semiconductor device according to the present invention along the X-X line of FIG.

도 2A를 참조하면, 셀영역(CA)과 주변영역(PA)을 갖는 기판(11) 상에 절연막(13)을 형성한다. 상기에서, 기판(11)은 불순물이 도핑된 확산영역(도시되지 않음)이 형성된 반도체기판이거나, 또는, 하부의 다른 배선일 수도 있다. 그리고, 절연막(13)을 산화실리콘, 질화실리콘, BPSG(Boro Phorpho Silicate Glass), USG(Undoped Silicate Glass), 또는, SOG(Spin On Glass) 등으로 형성한다.Referring to FIG. 2A, an insulating layer 13 is formed on the substrate 11 having the cell region CA and the peripheral region PA. In the above, the substrate 11 may be a semiconductor substrate on which a diffusion region (not shown) doped with impurities is formed, or may be another wiring below. The insulating film 13 is formed of silicon oxide, silicon nitride, Boro Phorpho Silicate Glass (BPSG), Undoped Silicate Glass (USG), or Spin On Glass (SOG).

절연막(13) 상에 다결정실리콘 또는 알루미늄 등의 도전성금속을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하거나, 또는, 실리사이드로 배선층(15)을 형성한다. 그리고, 배선층(15) 상에 산화실리콘 또는 질화실리콘 등을 CVD 방법으로 증착하여 희생층(17)을 형성한다.A conductive metal such as polycrystalline silicon or aluminum is deposited on the insulating film 13 by chemical vapor deposition (hereinafter, referred to as CVD), or the wiring layer 15 is formed of silicide. Then, silicon oxide, silicon nitride, or the like is deposited on the wiring layer 15 by CVD to form the sacrificial layer 17.

도 2B를 참조하면, 희생층(17)을 셀영역(CA)의 소정 부분에만 남도록 포토리쏘 그래피 방법으로 패터닝한다. 그리고, 배선층(15) 상에 희생층(17)을 덮도록 절연막(13) 및 희생층(17)을 형성하는 물질과 식각선택비가 다른 물질을 증착한 후 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 등의 방법으로 에치백하여 희생층(17)의 측면에 측벽(19)을 형성한다. 즉, 절연막(13) 및 희생층(17)을 산화실리콘으로 형성하면 측벽(19)을 질화실리콘으로 형성하고, 질화실리콘으로 형성하면 산화실리콘으로 형성한다. 도시되지 않았지만 측벽(19)은 희생층(17)의 4개의 측면 모두에 연결되게 형성되어 4각형을 이룬다.Referring to FIG. 2B, the sacrificial layer 17 is patterned by a photolithography method so that only a portion of the cell region CA remains. In addition, after the material forming the insulating layer 13 and the sacrificial layer 17 and the material having a different etching selectivity are deposited on the wiring layer 15, reactive ion etching (hereinafter, referred to as “reactive ion etching”) is described below. The sidewall 19 is formed on the side surface of the sacrificial layer 17 by etching back by a method such as RIE). That is, when the insulating film 13 and the sacrificial layer 17 are formed of silicon oxide, the sidewall 19 is formed of silicon nitride, and if of the silicon nitride is formed of silicon oxide. Although not shown, the side wall 19 is formed to be connected to all four sides of the sacrificial layer 17 to form a quadrangular shape.

도 2C를 참조하면, 패터닝된 희생층(17)을 습식식각 방법으로 제거한다. 이 때, 측벽(19)은 희생층(17)과 식각선택비가 다르므로 측벽(19)은 손상되지 않고 희생층(17)만 제거된다. 그리고, 4각형을 이루는 측벽(19)을 일측 및 타측의 소정 부분을 포토리쏘그래피 방법으로 제거하여 2개의 띠 형태로 분리한다.Referring to FIG. 2C, the patterned sacrificial layer 17 is removed by a wet etching method. At this time, since the sidewall 19 has an etching selectivity different from that of the sacrificial layer 17, the sidewall 19 is not damaged and only the sacrificial layer 17 is removed. Then, the side wall 19 forming the quadrangular shape is removed by a photolithography method on one side and the other side to be separated into two strips.

배선층(15) 상에 감광막(21)을 도포한 후 노광 및 현상하여 셀영역(CA) 내의 띠 형태의 측벽(19)의 일측 또는 타측 끝의 소정 부분과 주변영역(PA) 내의 소정 부분을 덮도록 패터닝한다. 이 때, 감광막(21)은 측벽(19)의 일측 또는 타측 끝의 소정 부분에는 측벽(19)의 두께 보다 넓은 폭을 갖는 4각형태를 가지며, 주변영역(PA)내에는 측벽(19)의 두께 보다 넓은 폭을 갖는 띠 형태를 갖도록 패터닝된다.The photosensitive film 21 is coated on the wiring layer 15, and then exposed and developed to cover a predetermined portion of one side or the other end of the strip-shaped sidewall 19 in the cell region CA and a predetermined portion in the peripheral region PA. To be patterned. At this time, the photosensitive film 21 has a quadrangular shape having a width wider than the thickness of the side wall 19 at a predetermined portion of one side or the other end of the side wall 19, and in the peripheral area PA of the side wall 19. It is patterned to have a strip shape with a width wider than the thickness.

도 2D를 참조하면, 측벽(19) 및 감광막(21)을 마스크로 사용하여 배선층(15)을 패터닝하여 셀영역(CA) 내에 제 1 배선(23)과 접촉부(25)를 형성하고 주변영역(PA)내에 제 2 배선(27)을 형성한다. 상기에서, 제 1 배선(23)과 접촉부(25)는 서로 연결되게 형성되는 데, 접촉부(25)의 폭이 제 1 배선(23)의 선폭 보다 크다. 또한, 주변영역(PA) 내에 제 2 배선(27)의 선폭도 제 1 배선(23)의 선폭 보다 크게 형성된다.Referring to FIG. 2D, the wiring layer 15 is patterned by using the sidewall 19 and the photosensitive film 21 as a mask to form the first wiring 23 and the contact portion 25 in the cell region CA, and the peripheral region ( The second wiring 27 is formed in PA). In the above, the first wiring 23 and the contact portion 25 are formed to be connected to each other, the width of the contact portion 25 is larger than the line width of the first wiring (23). In addition, the line width of the second wiring 27 is also formed larger than the line width of the first wiring 23 in the peripheral area PA.

감광막(21)과 측벽(19)을 순차적으로 제거한다. 상기에서 절연막(13)은 측벽(19)과 식각선택비가 서로 다르므로 측벽(19) 제거시 제거 또는 손상되지 않는다.The photosensitive film 21 and the side wall 19 are sequentially removed. Since the insulating layer 13 is different from the sidewall 19 and the etching selectivity, the insulating layer 13 is not removed or damaged when the sidewall 19 is removed.

상술한 바와 같이 본 발명에 따른 반도체장치의 배선 형성 방법은 측벽을 이용하여 배선층을 패터닝하여 셀영역(CA) 내에 제 1 배선을 형성할 때 측벽의 일측 또는 타측 끝의 소정 부분과 주변영역(PA) 내의 소정 부분을 감광막 패턴으로 덮은 상태에서 배선층을 패터닝하여 제 1 배선 보다 넓은 선폭을 갖는 접촉구 및 제 2 배선을 동시에 형성한다.As described above, in the method of forming the wiring of the semiconductor device according to the present invention, when the first wiring is formed in the cell area CA by patterning the wiring layer using the sidewall, the predetermined portion and the peripheral area PA of one side or the other end of the sidewall are formed. The wiring layer is patterned in a state where a predetermined portion within the circuit) is covered with the photosensitive film pattern to simultaneously form a contact hole having a wider line width than the first wiring and the second wiring.

따라서, 본 발명은 셀영역 내의 제 1 배선의 선폭을 좁게 하여 집적도를 향상시키면서 접촉부와 주변영역 내의 배선의 선폭을 크게 형성하여 소자 특성을 향상시킬 수 있는 잇점이 있다.Therefore, the present invention has the advantage that the line width of the first wiring in the cell region can be narrowed to improve the degree of integration while the line width of the wiring in the contact portion and the peripheral region can be made large to improve the device characteristics.

Claims (6)

셀영역과 주변영역을 포함하는 기판 상에 절연막, 배선층 및 희생층을 순차적으로 형성하는 공정과,Sequentially forming an insulating film, a wiring layer, and a sacrificial layer on the substrate including the cell region and the peripheral region; 상기 희생층을 상기 셀영역의 소정 부분에만 남도록 패터닝하고 상기 패터닝된 희생층의 측면에 측벽을 형성하는 공정과,Patterning the sacrificial layer so as to remain only in a predetermined portion of the cell region, and forming sidewalls on side surfaces of the patterned sacrificial layer; 상기 패터닝된 희생층을 제거하고 셀영역 내의 상기 측벽의 일측 또는 타측 끝의 소정 부분과 상기 주변영역 내의 소정 부분을 덮는 패터닝된 감광막을 형성하는 공정과,Removing the patterned sacrificial layer and forming a patterned photoresist film covering a predetermined portion of one side or the other end of the sidewall in the cell region and a predetermined portion in the peripheral region; 상기 측벽 및 상기 감광막을 마스크로 사용하여 배선층을 패터닝하여 상기 셀영역 내에 제 1 배선 및 접촉부와 상기 주변영역 내에 제 2 배선을 형성하는 공정을 구비하는 반도체장치의 배선 형성 방법.And forming a first wiring and a contact portion in the cell region and a second wiring in the peripheral region by patterning a wiring layer using the sidewalls and the photosensitive film as a mask. 청구항 1에 있어서,The method according to claim 1, 상기 절연막을 산화실리콘, 질화실리콘, BPSG(Boro Phorpho Silicate Glass), USG(Undoped Silicate Glass), 또는, SOG(Spin On Glass)로 형성하는 반도체장치의 배선 형성 방법.A method of forming a wiring in a semiconductor device, wherein the insulating film is formed of silicon oxide, silicon nitride, Boro Phorpho Silicate Glass (BPSG), Undoped Silicate Glass (USG), or spin on glass (SOG). 청구항 1에 있어서,The method according to claim 1, 상기 희생층을 산화실리콘 또는 질화실리콘으로 형성하는 반도체장치의 배선 형성 방법.And forming the sacrificial layer from silicon oxide or silicon nitride. 청구항 1에 있어서,The method according to claim 1, 상기 측벽을 상기 절연막 및 상기 희생층을 형성하는 물질과 식각선택비가 다른 물질로 형성하는 반도체장치의 배선 형성 방법.And forming the sidewalls of a material having an etch selectivity different from that of the material forming the insulating layer and the sacrificial layer. 청구항 1에 있어서,The method according to claim 1, 상기 감광막을 상기 측벽 보다 넓은 폭을 갖도록 형성하는 반도체장치의 배선 형성 방법.And the photosensitive film is formed to have a width wider than that of the sidewalls. 청구항 1에 있어서,The method according to claim 1, 상기 셀영역 내에 제 1 배선 및 접촉부와 상기 주변영역 내에 제 2 배선을 형성하는 공정 후에 상기 측벽 및 상기 패터닝된 감광막을 제거하는 공정을 더 구비하는 반도체장치의 배선 형성 방법.And removing the sidewalls and the patterned photoresist after forming the first wiring and the contact portion in the cell region and the second wiring in the peripheral region.
KR1019970024757A 1997-06-14 1997-06-14 Method for forming metal interconnector of semiconductor device KR100231134B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970024757A KR100231134B1 (en) 1997-06-14 1997-06-14 Method for forming metal interconnector of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970024757A KR100231134B1 (en) 1997-06-14 1997-06-14 Method for forming metal interconnector of semiconductor device

Publications (2)

Publication Number Publication Date
KR19990001440A true KR19990001440A (en) 1999-01-15
KR100231134B1 KR100231134B1 (en) 1999-11-15

Family

ID=19509613

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970024757A KR100231134B1 (en) 1997-06-14 1997-06-14 Method for forming metal interconnector of semiconductor device

Country Status (1)

Country Link
KR (1) KR100231134B1 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630780B1 (en) * 2000-09-06 2006-10-04 주식회사 하이닉스반도체 A method for fabricating semiconductor device using inorganic SOG
WO2009075959A1 (en) * 2007-12-06 2009-06-18 Micron Technology, Inc. Method for forming high density patterns
KR100924193B1 (en) * 2007-12-24 2009-10-29 주식회사 하이닉스반도체 Method for manufacturing the semiconductor device
US7651951B2 (en) 2005-03-15 2010-01-26 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US7687408B2 (en) 2004-09-02 2010-03-30 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7732343B2 (en) 2006-04-07 2010-06-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7767573B2 (en) 2005-07-29 2010-08-03 Round Rock Research, Llc Layout for high density conductive interconnects
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US8011090B2 (en) 2005-09-01 2011-09-06 Micron Technology, Inc. Method for forming and planarizing adjacent regions of an integrated circuit
US8030222B2 (en) 2004-08-31 2011-10-04 Round Rock Research, Llc Structures with increased photo-alignment margins
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8123968B2 (en) 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US8207614B2 (en) 2005-05-23 2012-06-26 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8507341B2 (en) 2005-03-28 2013-08-13 Micron Technology, Inc. Integrated circuit fabrication
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US8703616B2 (en) 2005-06-09 2014-04-22 Round Rock Research, Llc Method for adjusting feature size and position
US8928111B2 (en) 2008-07-03 2015-01-06 Micron Technology, Inc. Transistor with high breakdown voltage having separated drain extensions
US9082829B2 (en) 2005-09-01 2015-07-14 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US9099314B2 (en) 2005-09-01 2015-08-04 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US9117766B2 (en) 2005-06-02 2015-08-25 Micron Technology, Inc. Method for positioning spacers in pitch multiplication
US9478497B2 (en) 2006-08-30 2016-10-25 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US9553082B2 (en) 2006-04-25 2017-01-24 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101063727B1 (en) 2009-01-22 2011-09-07 주식회사 하이닉스반도체 Pattern formation method of semiconductor device

Cited By (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630780B1 (en) * 2000-09-06 2006-10-04 주식회사 하이닉스반도체 A method for fabricating semiconductor device using inorganic SOG
US8030222B2 (en) 2004-08-31 2011-10-04 Round Rock Research, Llc Structures with increased photo-alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7687408B2 (en) 2004-09-02 2010-03-30 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US8338085B2 (en) 2004-09-02 2012-12-25 Micron Technology, Inc. Method to align mask patterns
US8207576B2 (en) 2005-03-15 2012-06-26 Round Rock Research, Llc Pitch reduced patterns relative to photolithography features
US7651951B2 (en) 2005-03-15 2010-01-26 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US8048812B2 (en) 2005-03-15 2011-11-01 Round Rock Research, Llc Pitch reduced patterns relative to photolithography features
US8598632B2 (en) 2005-03-15 2013-12-03 Round Rock Research Llc Integrated circuit having pitch reduced patterns relative to photoithography features
US8859362B2 (en) 2005-03-28 2014-10-14 Micron Technology, Inc. Integrated circuit fabrication
US9412594B2 (en) 2005-03-28 2016-08-09 Micron Technology, Inc. Integrated circuit fabrication
US9147608B2 (en) 2005-03-28 2015-09-29 Micron Technology, Inc. Integrated circuit fabrication
US8507341B2 (en) 2005-03-28 2013-08-13 Micron Technology, Inc. Integrated circuit fabrication
US9099402B2 (en) 2005-05-23 2015-08-04 Micron Technology, Inc. Integrated circuit structure having arrays of small, closely spaced features
US8207614B2 (en) 2005-05-23 2012-06-26 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US9117766B2 (en) 2005-06-02 2015-08-25 Micron Technology, Inc. Method for positioning spacers in pitch multiplication
US8703616B2 (en) 2005-06-09 2014-04-22 Round Rock Research, Llc Method for adjusting feature size and position
US7767573B2 (en) 2005-07-29 2010-08-03 Round Rock Research, Llc Layout for high density conductive interconnects
US8123968B2 (en) 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US8877639B2 (en) 2005-08-30 2014-11-04 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US9099314B2 (en) 2005-09-01 2015-08-04 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US10396281B2 (en) 2005-09-01 2019-08-27 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8011090B2 (en) 2005-09-01 2011-09-06 Micron Technology, Inc. Method for forming and planarizing adjacent regions of an integrated circuit
US9679781B2 (en) 2005-09-01 2017-06-13 Micron Technology, Inc. Methods for integrated circuit fabrication with protective coating for planarization
US9082829B2 (en) 2005-09-01 2015-07-14 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7732343B2 (en) 2006-04-07 2010-06-08 Micron Technology, Inc. Simplified pitch doubling process flow
US9184159B2 (en) 2006-04-07 2015-11-10 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US9553082B2 (en) 2006-04-25 2017-01-24 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8663532B2 (en) 2006-06-01 2014-03-04 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8449805B2 (en) 2006-06-01 2013-05-28 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US9478497B2 (en) 2006-08-30 2016-10-25 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US9412591B2 (en) 2007-07-31 2016-08-09 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
WO2009075959A1 (en) * 2007-12-06 2009-06-18 Micron Technology, Inc. Method for forming high density patterns
CN101889326B (en) * 2007-12-06 2012-07-11 美光科技公司 Method for forming high density patterns
US8871648B2 (en) 2007-12-06 2014-10-28 Micron Technology, Inc. Method for forming high density patterns
US9941155B2 (en) 2007-12-18 2018-04-10 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US9666695B2 (en) 2007-12-18 2017-05-30 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US10497611B2 (en) 2007-12-18 2019-12-03 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
KR100924193B1 (en) * 2007-12-24 2009-10-29 주식회사 하이닉스반도체 Method for manufacturing the semiconductor device
US8242021B2 (en) 2007-12-24 2012-08-14 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8507384B2 (en) 2008-03-21 2013-08-13 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US9048194B2 (en) 2008-03-21 2015-06-02 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8928111B2 (en) 2008-07-03 2015-01-06 Micron Technology, Inc. Transistor with high breakdown voltage having separated drain extensions
US8871646B2 (en) 2008-11-24 2014-10-28 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits

Also Published As

Publication number Publication date
KR100231134B1 (en) 1999-11-15

Similar Documents

Publication Publication Date Title
KR100231134B1 (en) Method for forming metal interconnector of semiconductor device
KR100278273B1 (en) A method for forming contact holes in semiconductor device
US7235442B2 (en) Method for fabricating conductive line
KR100324935B1 (en) Method of forming wiring for semiconductor device
KR100248626B1 (en) Method of fabricating semiconductor device
KR100430688B1 (en) Method of forming contact hole of semiconductor device
KR100240613B1 (en) Interconnecting method of semiconductor device
KR100235960B1 (en) Method of forming conducting line in semiconductor device
KR100306905B1 (en) Contact hole formation method
KR100328557B1 (en) Method for forming a metal line of semiconductor device
KR100396685B1 (en) Interconnection of semiconductor device and manufacturing method thereof
KR100237758B1 (en) Manufacture of semiconductor device
KR100204910B1 (en) Interconnecting method of semiconductor device
KR100267773B1 (en) Method for fabricating semiconductor device
KR100244261B1 (en) Plug forming method in semiconductor device
KR100277883B1 (en) Manufacturing Method of Semiconductor Device
KR100221606B1 (en) Method for wiring contact of semiconductor device
KR100249018B1 (en) Method of fabricating contact hole
KR100413043B1 (en) Gate electrode formation method of semiconductor device
KR100219055B1 (en) Forming method for contact hole of semiconductor device
KR19980058381A (en) Semiconductor device and other manufacturing method
KR19980015773A (en) Method of forming a contact hole in a semiconductor device
KR20010059464A (en) Method for manufacturing semiconductor device
KR19980015743A (en) Polycide gate formation method
KR19990024656A (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee