KR102490626B1 - Organic Light Emitting Display Device and Method of Manufacturing the same - Google Patents

Abstract

An object of the present invention is to provide an organic light emitting display device capable of implementing a narrow bezel while avoiding a problem of low potential power rise, as well as designing a power supply suitable for a target specification or a flexible design in a method requiring low power consumption. To this end, the present invention electrically connects the low potential power line and the upper electrode layer with a compensation metal layer positioned on the upper electrode layer.

Description

Organic light emitting display device and method of manufacturing the same {Organic Light Emitting Display Device and Method of Manufacturing the same}

The present invention relates to an organic light emitting display device and a manufacturing method thereof.

An organic light emitting device used in an organic light emitting display device is a self light emitting device in which a light emitting layer is formed between two electrodes. In the organic light emitting device, electrons and holes are injected into the light emitting layer from an electron injection electrode (cathode) and a hole injection electrode (anode), respectively, and excitons, in which the injected electrons and holes are combined, enter an excited state. It is an element that emits light when it falls from the ground state.

An organic light emitting display device forms a display panel using an organic light emitting device. The display panel may be implemented in a top-emission type, a bottom-emission type, and a dual-emission type according to the direction in which light is emitted, and a passive matrix type ( It can be implemented in passive matrix) and active matrix type. Organic light emitting display devices are implemented in various forms, such as having a curved surface by imparting ductility or being bent artificially or mechanically.

Conventionally proposed organic light emitting display devices cannot directly connect the upper electrode (top electrode) of the organic light emitting diode and the low potential power line (lowest electrode). Connect the lines electrically.

However, the configuration and connection method of the low potential power line proposed in the prior art has difficulty in reducing the bezel area because the low potential power line must be configured with a source-drain metal layer or a gate metal layer existing in the non-display area (or bezel area).

In order to solve the problems of the background art described above, the present invention forms a compensation metal layer on the low potential power line to prevent the low potential power rise problem caused by the method of connecting the electrode and the low potential power line using a connection electrode. do. The method of forming the compensating metal layer according to the present invention can design a power supply to meet target specifications when manufacturing an organic light emitting display device, and can provide advantages of low power consumption and narrow bezel design.

As a means to solve the above-described problems, the present invention prevents the problem of low potential power rise and implements a narrow bezel, as well as an organic light emitting display capable of flexible design by designing power to meet target specifications or requiring low power consumption. to provide the device. To this end, the organic light emitting display device according to the present invention includes a display area defined on a first substrate, a gate-in-panel area positioned outside the display area, and a low-potential power line positioned outside the gate-in-panel area. A non-display area including a region, a low potential power line positioned in the low potential power line area on the first substrate, and an insulating layer positioned on the low potential power line and extending from the low potential power line area to the gate a lower electrode layer positioned up to the in-panel area and connected to the low potential power line; an upper electrode layer insulated by an insulating layer positioned on the lower electrode layer and positioned from the display area to the gate-in-panel area and connected to the lower electrode layer; and A compensation metal layer located on the upper electrode layer and electrically connecting the low potential power line and the upper electrode layer is included.

A compensation metal layer located on the upper electrode layer electrically connects the low potential power line and the upper electrode layer,

The compensation metal layer may contact the low potential power line, the lower electrode layer and the upper electrode layer.

The compensation metal layer may be located from a low potential power line region to a gate-in-panel region;

It may be located from the low potential power line area to the display area.

In another aspect, the present invention provides a method for manufacturing an organic light emitting display device. A manufacturing method of an organic light emitting display device defines a display area on a first substrate and defines a non-display area including a gate-in-panel area outside the display area and a low potential power line area outside the gate-in-panel area. Step, forming a gate metal layer in the gate-in-panel region on the first substrate, forming a first insulating layer on the gate metal layer, source drain serving as a low potential power line in a low potential power line region on the first insulating layer Forming a metal layer, forming a second insulating layer on the source-drain metal layer, forming a planarization layer on the second insulating layer, a gate from a low potential power line region on the planarization layer to be connected to a low potential power line Forming a lower electrode layer up to the in-panel area, forming a bank layer on the lower electrode layer, forming an organic light emitting layer in a display area on the bank layer, from the display area on the organic light emitting layer to the gate in-panel area to be connected to the lower electrode layer forming an upper electrode layer, and forming a compensation metal layer on the upper electrode layer so that the low potential power line and the upper electrode layer are electrically connected to each other.

The present invention has an effect of providing an organic light emitting display device capable of implementing a narrow bezel while preventing a low potential power supply problem by further forming a compensation metal layer. In addition, the present invention has an effect of configuring a compensation metal layer using various metal materials (Cu, Ag, NiCr, NiCu, etc.). In addition, since the present invention configures the compensation metal layer based on a material having low sheet resistance, the deposited area, thickness, and shape can be changed according to a target specification, there is an effect of increasing the degree of freedom in design. In addition, the present invention can implement a narrow bezel while maintaining the same low-potential power-up level, and can relatively reduce the low-potential power-up level when implementing a display panel with the same size of the bezel, thereby maximizing the performance of the display panel. It works. In addition, the present invention has an effect of implementing a narrow bezel while preventing a problem of low potential power rise, and designing a power supply according to a target specification or enabling a flexible design by requiring low power consumption.

1 is a schematic block diagram of an organic light emitting display device;
2 is a first exemplary diagram showing a circuit configuration of a sub-pixel;
3 is a second exemplary diagram showing a circuit configuration of a sub-pixel;
4 is a cross-sectional view of a display panel;
5 is an exemplary view showing mechanical characteristics of the display panel shown in FIG. 4;
6 is a cross-sectional view showing a non-display area of a power design unit according to a conventional structure;
7 is a hierarchical diagram schematically illustrating a connection structure between an upper electrode and a low potential power line shown in FIG. 6;
8 is a cross-sectional view showing a non-display area of a power design unit according to a first embodiment of the present invention.
9 is a hierarchical diagram schematically illustrating a connection structure between an upper electrode and a low potential power line shown in FIG. 8;
10 is a view for explaining a manufacturing method related to forming an upper electrode layer;
11 is a view for explaining a manufacturing method related to forming a compensation metal layer;
12 is a cross-sectional view showing a non-display area of a power design unit according to a second embodiment of the present invention.
FIG. 13 is a first hierarchical diagram schematically illustrating a connection structure between an upper electrode and a low potential power line shown in FIG. 12;
FIG. 14 is a second hierarchical view schematically illustrating a connection structure between an upper electrode and a low potential power line shown in FIG. 12;
15 is a view for explaining a manufacturing method related to forming an upper electrode layer;
16 is a view for explaining a manufacturing method related to forming a compensation metal layer;
17 is a plan view showing a display area and a non-display area of a power design unit according to a third embodiment of the present invention;
18 is a simulation result graph of a conventionally proposed power source structure and a power source structure according to the first embodiment of the present invention.

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a first exemplary diagram showing a circuit configuration of a subpixel, and FIG. 3 is a second exemplary diagram illustrating a circuit configuration of a subpixel.

As shown in FIG. 1 , the organic light emitting display device includes an image processor 110 , a timing controller 120 , a data driver 130 , a gate driver 140 and a display panel 150 .

The image processor 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processor 110 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description. The image processing unit 110 is formed in the form of an integrated circuit (IC) on a system circuit board.

The timing controller 120 receives a data signal DATA along with a data enable signal DE or driving signals including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing unit 110 .

The timing controller 120 generates a gate timing control signal (GDC) for controlling the operation timing of the gate driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs The timing controller 120 is formed in the form of an IC on a control circuit board.

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120, converts it into a gamma reference voltage, and outputs the result. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 is formed in the form of an IC on a data circuit board.

The gate driver 140 outputs a gate signal while shifting the level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120 . The gate driver 140 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 140 is formed in the form of an IC on a gate circuit board or formed in a gate-in-panel method on the display panel 150 . A part formed in the gate-in-panel method in the gate driver 140 is a shift register or the like.

The display panel 150 displays an image in response to the data signal DATA and the gate signal supplied from the data driver 130 and the gate driver 140 . The display panel 150 includes subpixels SP that display an image.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different light emitting areas according to light emitting characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The switching transistor SW performs a switching operation to store the data signal supplied through the first data line DL1 as a data voltage in the capacitor Cst in response to the gate signal supplied through the first gate line GL1. The driving transistor DR operates to allow a driving current to flow between the high potential power line EVDD and the low potential power line EVSS according to the data voltage stored in the capacitor Cst. The compensation circuit CC is a circuit for compensating for the threshold voltage of the driving transistor DR.

The compensation circuit (CC) is composed of one or more thin film transistors and capacitors. Since the configuration of the compensation circuit (CC) varies greatly depending on the compensation method, specific examples and descriptions thereof will be omitted. Thin film transistors are implemented based on low-temperature polysilicon (LTPS), amorphous silicon (a-Si), oxide or organic semiconductor layers.

As shown in FIG. 3 , when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for supplying a specific signal or power as well as driving the compensation thin film transistor.

The added signal line may be defined as first and second gate lines GL1b for driving the compensation thin film transistor included in the subpixel. Also, the added power line may be defined as a third power line INIT for initializing a specific node of a subpixel to a specific voltage. However, this is only one example and is not limited thereto.

On the other hand, in FIGS. 2 and 3, it is taken as an example that a compensation circuit (CC) is included in one sub-pixel. However, when the subject of compensation is located outside the sub-pixel, such as the data driver 130, the compensation circuit (CC) may be omitted. That is, one sub-pixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor (Cst), and an organic light emitting diode (OLED), but a compensation circuit When (CC) is added, it may be configured in various ways such as 3T1C, 4T2C, 5T2C, and 6T1C.

4 is a cross-sectional view of a display panel, and FIG. 5 is an example view showing mechanical characteristics of the display panel shown in FIG. 4 .

As shown in FIG. 4 , the display panel 150 includes a first substrate 150a, a display area AA, an adhesive member 165, and a second substrate 150b. The first substrate 150a and the second substrate 150b are made of polyimide (PI), polyethersulfone (PES), polyethylene terephthalate (PET), polycarbonates (PC), polyethylene It is selected from plastic, glass, or thin metal materials such as polyethylene naphthalate (PEN) and acrylonitrile butadiene styrene (ABS).

The display area AA is formed between the first substrate 150a and the second substrate 150b. Sub-pixels, various signal lines, and power lines are formed in the display area AA. A multilayer encapsulation structure may be formed on the power lines to block moisture that may be introduced from the outside.

The first substrate 150a and the second substrate 150b are bonded and sealed by an adhesive member 165 positioned between them. The adhesive member 165 may be selected from pressure sensitive adhesive film (PSA), optical clear adhesive film (OCA), frit, multilayer passivation, and the like.

Structures such as sub-pixels and various signal lines and power lines formed in the display area AA are vulnerable to moisture (moisture) or oxygen. For this reason, the display area AA is sealed by the adhesive member 165 positioned between the first substrate 150a and the second substrate 150b. However, depending on the characteristics and configuration of the adhesive member 165, the second substrate 150b may be omitted.

As shown in FIG. 5 , since the display panel 150 has ductility, an organic light emitting display device manufactured thereon is implemented in various forms such as being artificially or mechanically bent or having a curved surface.

An organic light emitting display device manufactured based on the above display panel may be implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The display panel 150 to be described below can be implemented to be bent depending on the substrate material even if it is not plastic, and can also be implemented in a narrow bezel form in which the area occupied by the non-display area is reduced.

In addition, in the following description, the top-emission method is taken as an example, and the problems of the conventionally proposed structure are considered and the present invention capable of solving them will be described.

6 is a cross-sectional view showing a non-display area of a power design unit according to a conventional structure, and FIG. 7 is a hierarchical diagram briefly showing a connection structure between an upper electrode and a low potential power line shown in FIG. 6 .

As shown in FIG. 6 , the non-display area NA of the display panel includes a margin area EMP, a low potential power line area EVSSP, and a gate in-panel area GIP. The gate-in-panel area GIP is positioned outside the display area AA. The low potential power line region EVSSP is positioned outside the gate-in-panel region GIP. The margin area EMP is positioned outside the low potential power line area EVSSP.

The margin area EMP is defined as an area for preparing an extra space when the first substrate 150a and the second substrate (not shown) are bonded and sealed using an adhesive member or the like. The low potential power line area EVSSP is defined as an area that can be used when forming a low potential power line on the first substrate 150a. The gate-in-panel region GIP is defined as a region that can be used when forming a shift register or the like, which is a part formed by a gate-in-panel method in a gate driver (not shown).

The first substrate 150a includes a first layer BP and a second layer PI. The first layer (BP) serves as a back plate for maintaining the ductility and reinforcing the rigidity of the second layer (PI).

On the first substrate 150a, starting from the buffer layer BUF to the upper electrode layer 159, which is the uppermost layer, is formed. In the non-display area NA, there are low potential power lines, etc., and in the display area AA, transistor arrays (transistors, capacitors, etc.), organic light emitting diodes, etc. are present. Hereinafter, the interlayer structure formed on the first substrate 150a without distinction between the display area AA and the non-display area NA will be described.

A buffer layer BUF is formed on the first substrate 150a. A gate metal layer 151 is formed on the buffer layer BUF. A first insulating layer 152 is formed on the gate metal layer 151 . A source-drain metal layer 153 is formed on the first insulating layer 152 . A second insulating layer 154 is formed on the source-drain metal layer 153 . A planarization layer 155 is formed on the second insulating layer 154 . A lower electrode layer 156 is formed on the planarization layer 155 . A bank layer BNK is formed on the lower electrode layer 156 . A reflective electrode layer 157 is formed on the bank layer BNK. An organic light emitting layer 158 is formed on the reflective electrode layer 157 . An upper electrode layer 159 is formed on the organic light emitting layer 158 .

As shown in FIGS. 6 and 7 , the source-drain metal layer 153 existing on the upper layer of the low potential power line region EVSSP becomes the low potential power line EVSS. That is, the low potential power line EVSS is made of the same material as the source and drain electrodes in the display area AA. Since the upper electrode layer 159 existing on the uppermost layer of the gate-in-panel region GIP is selected as the cathode electrode of the organic light emitting diode, low potential power is supplied through the low potential power line EVSS.

Due to structural characteristics, the organic light emitting display device cannot directly connect the upper electrode layer 159 and the low potential power supply line (EVSS) (electrodes and lines are spaced apart from each other). In addition, in the case of a top emission organic light emitting display device, due to structural characteristics, the sheet resistance of the upper electrode layer 159 is high, and ΔVSS of the low potential power supply line EVSS increases when a power source is configured only with the upper electrode layer 159.

Therefore, in the related art, a parallel resistor electrically connecting the upper electrode layer 159 and the low potential power line EVSS using the lower electrode layer 156 positioned between the upper electrode layer 159 and the low potential power line EVSS ( R) and a power supply design method that lowers ΔVSS has been used universally.

Calculating the total resistance value (R_Total) of the low potential power line (EVSSP, power design unit) according to the conventionally proposed method is as follows.

R_Total = R1 * R2 * R3 / (R1*R2 + R1*R3 + R2*R3)

R1 is the resistance value of the upper electrode layer, R2 is the resistance value of the lower electrode layer serving as a connection electrode, and R3 is the resistance value of the source-drain metal layer serving as a low potential power line.

However, in the configuration and connection method of the low potential power line (EVSS) proposed in the related art, the low potential power line is connected to the source drain metal layer 153 or the gate metal layer 151 existing in the non-display area NA (or bezel area). It is difficult to reduce the bezel area because it must be configured.

Meanwhile, in order to reduce the bezel area in the structure of FIG. 6, as a result of an experiment to reduce the area of the source-drain metal layer serving as a low-potential power line, it was found that ΔVSS significantly increased. Therefore, since the bezel area cannot be reduced only with the conventionally proposed structure, another method for reducing the bezel area while preventing the increase of ΔVSS is required.

<First Embodiment>

8 is a cross-sectional view showing a non-display area of a power design unit according to a first embodiment of the present invention, and FIG. 9 is a hierarchical diagram briefly showing a connection structure between an upper electrode and a low potential power line shown in FIG. 8 .

As shown in FIG. 8 , the non-display area NA of the display panel includes a margin area EMP, a low potential power line area EVSSP, and . The gate-in-panel area GIP is positioned outside the display area AA. The low potential power line region EVSSP is positioned outside the gate-in-panel region GIP. The margin area EMP is positioned outside the low potential power line area EVSSP.

The margin area EMP is defined as an area for preparing an extra space when the first substrate 150a and the second substrate (not shown) are bonded and sealed using an adhesive member or the like. The low potential power line area EVSSP is defined as an area that can be used when forming a low potential power line on the first substrate 150a. The gate-in-panel region GIP is defined as a region that can be used when forming a shift register or the like, which is a part formed by a gate-in-panel method in a gate driver (not shown).

The first substrate 150a includes a first layer BP and a second layer PI. The first layer (BP) serves as a back plate for maintaining the ductility and reinforcing the rigidity of the second layer (PI). For example, the first layer BP may be selected from polyethylene terephthalate (PET), and the second layer PI may be selected from polyimide (PI), but is not limited thereto.

On the first substrate 150a, starting from the buffer layer BUF to the upper electrode layer 159, which is the uppermost layer, is formed. In the non-display area NA, there are low potential power lines, etc., and in the display area AA, transistor arrays (transistors, capacitors, etc.), organic light emitting diodes, etc. are present. Hereinafter, the interlayer structure formed on the first substrate 150a without distinction between the display area AA and the non-display area NA will be described.

A buffer layer BUF is formed on the first substrate 150a. The buffer layer BUF may have a structure including a single-layer buffer layer, a multi-layer buffer layer, or a single-layer buffer layer and a multi-layer buffer layer. The buffer layer BUF may be selected from among silicon (Si)-based SiOx, SiNx, and SiON.

A gate metal layer 151 is formed on the buffer layer BUF. The gate metal layer 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof. It may be, and it may be made of a single layer or multiple layers. The gate metal layer 151 is divided into a gate electrode of a transistor, gate lines connected to the gate electrode, and gate pads connected to the gate lines by a patterning process.

A first insulating layer 152 is formed on the gate metal layer 151 . The first insulating layer 152 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). The first insulating layer 152 may be defined as a gate insulating layer.

A source-drain metal layer 153 is formed on the first insulating layer 152 . The source-drain metal layer 153 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or a mixture thereof. It may be an alloy, and may consist of a single layer or multiple layers. The source-drain metal layer 153 is divided into source and drain electrodes of the transistor, data lines connected to the source or drain electrodes, and data pads connected to the data lines by a patterning process.

A second insulating layer 154 is formed on the source-drain metal layer 153 . The second insulating layer 154 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). The second insulating layer 154 may be cut with a protective layer.

A planarization layer 155 is formed on the second insulating layer 154 . The planarization layer 155 is a layer covering the transistor array portion and is selected from an organic material such as photoacrylic (PAC) or a coating layer that can serve to planarize the upper surface.

A lower electrode layer 156 is formed on the planarization layer 155 . The lower electrode layer 156 is made of a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum-doped zinc oxide (AZO). The lower electrode layer 156 is divided into a lower electrode (eg, an anode electrode) of an organic light emitting diode, a connection electrode of a low potential power line, and the like by a patterning process.

A bank layer BNK is formed on the lower electrode layer 156 . The bank layer BNK may be an organic insulating layer or an inorganic insulating layer. The bank layer BNK may be defined as a pixel defining layer defining an opening area of an organic light emitting diode.

A reflective electrode layer 157 is formed on the bank layer BNK. The reflective electrode layer 157 is selected from a material having high reflectivity, such as aluminum (Al) or silver (Ag), to transmit light generated from the organic light emitting layer 158 in the direction of the upper electrode layer 159 .

An organic light emitting layer 158 is formed on the reflective electrode layer 157 . The organic light emitting layer 158 is selected from a light emitting material that emits red, green, blue or white light. The organic emission layer 158 has a hierarchical structure such as a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer, or a structure in which other functional layers are added.

An upper electrode layer 159 is formed on the organic light emitting layer 158 . The upper electrode layer 159 is formed in the form of a front electrode to be positioned in portions of the display area AA and the non-display area NA, and is formed of a light-transmitting material or thin enough to transmit light. The upper electrode layer 159 becomes an upper electrode (eg, a cathode electrode) of an organic light emitting diode and has a region connected to a low potential power line.

The compensation metal layer 160 (New Metal) is formed on the upper electrode layer 159 (Cathode) and the source-drain metal layer 153 (SD). The compensation metal layer 160 may be formed as a single layer or multiple layers. The compensation metal layer 160 serves to lower resistance when electrically connecting the upper electrode layer 159 and the low potential power supply line (EVSS), and a description thereof is as follows.

As shown in FIGS. 8 and 9 , the source-drain metal layer 153 existing on the upper layer of the low potential power line region EVSSP becomes the low potential power line EVSS. Since the upper electrode layer 159 existing on the upper layer of the gate-in-panel region GIP is selected as the cathode electrode of the organic light emitting diode, low potential power is supplied through the low potential power line EVSS.

Due to structural characteristics, the organic light emitting display device cannot directly connect the upper electrode layer 159 and the low potential power supply line (EVSS) (electrodes and lines are spaced apart from each other). Also, due to structural characteristics of the organic light emitting display device, the sheet resistance of the upper electrode layer 159 is high, and ΔVSS of the low potential power supply line EVSS increases when a power source is configured only with the upper electrode layer 159 .

Therefore, in the first embodiment, the compensation metal layer 160 is further formed on the lower electrode layer 156 (anode) serving as a connection electrode between the upper electrode layer 159 and the low potential power line (EVSS). The compensation metal layer 160 may be selected from a material having low sheet resistance, such as a single metal material such as copper (Cu) or silver (Ag) or an alloy material such as nickel chrome (NiCr) or nickel copper (NiCu), but is limited thereto It doesn't work.

The compensation metal layer 160 is formed from the gate-in-panel region GIP to the low potential power line region EVSSP. The second insulating layer 154 positioned in the low potential power line region EVSSP has a contact hole exposing a portion of the source-drain metal layer 153 . Accordingly, the compensation metal layer 160 contacts the upper electrode layer 159 on the uppermost layer of the gate-in-panel region GIP and the source-drain metal layer 153 on the upper layer of the low potential power line region EVSSP.

As another example, the bank layer BNK positioned in the low potential power line region EVSSP may have a contact hole exposing a side surface (or side wall) of the lower electrode layer 156 as shown. To this end, the lower electrode layer 156 is formed to cover the side surface of the planarization layer 155 . The bank layer BNK exposes part (or all) of the lower electrode layer 156 formed to cover the side surface of the planarization layer 155 .

In this case, the compensation metal layer 160 includes the upper electrode layer 159 on the uppermost layer of the gate-in-panel region GIP, the source-drain metal layer 153 on the upper layer of the low potential power line region EVSSP, and the low potential. It contacts the side surface of the lower electrode layer 156 in the power line area EVSSP.

That is, the compensation metal layer 160 is formed in a structure in contact with two or more layers of the upper electrode layer 159 and the source-drain metal layer 153, or the upper electrode layer 159, the lower electrode layer 156, and the source-drain metal layer 153 or more. It can be formed into a structure in contact with three layers.

In the first embodiment of the present invention, in order to implement a narrow bezel by minimizing the power design area that occupies the bezel area, a reinforcing material with low sheet resistance is applied from the gate-in-panel area (GIP) to the low potential power line area. (EVSSP).

As a result of the experiment, it was found that the structure of the first embodiment can further narrow the bezel area as can be seen through a comparison between the EVSSP area of FIG. 7 shown in FIG. 9 and the EVSSP area of the embodiment.

As a result of the experiment, it was found that the structure of the first embodiment further reduced the total resistance of the low potential power line compared to the conventional structure (total resistance decreased due to the addition of a low sheet resistance resistor to the parallel resistance structure) compared to the conventional structure. Also, the total resistance of the low-potential power line was found to be more reduced when a structure in which the compensating metal layer 160 contacts three layers than a structure in which the compensating metal layer 160 contacts two layers.

It is expected that the conditions for implementing a display device with a high resolution and a narrow bezel can be satisfied by using the power supply structure as described above in the first embodiment. However, even if the target of the display device is not a narrow bezel but requires low power consumption, since ΔVSS can be lowered than before, it is possible to change the structure to use a lower electric potential power supply (EVDD) than before.

Hereinafter, a manufacturing method for power design according to a first embodiment of the present invention will be described. However, in the following, only the upper electrode layer and the compensation metal layer formation part directly related to the characteristics of the present invention will be described.

10 is a view for explaining a manufacturing method related to forming an upper electrode layer, and FIG. 11 is a view for explaining a manufacturing method related to forming a compensation metal layer.

During the transistor array process, a low potential power line corresponding to the power supply unit is formed in the non-display area NA by using a metal layer, and an upper electrode layer 159 is formed on the entire surface of the display area AA in a subsequent process. The upper electrode layer 159 is selected from a material capable of using thermal evaporation or sputtering.

As shown in FIG. 10 , the upper electrode layer 159 is formed by a first mask CMSK having an open portion OPN (NOPN is a blocking portion) exposing a portion of the display area AA and the non-display area NA. do. As shown in FIG. 11 , the compensation metal layer 160 is formed by a second mask NMSK having an open portion OPN exposing only a part of the non-display area NA adjacent to the display area AA. As a result, the compensation metal layer 160 is formed from the gate-in-panel region GIP to the low potential power line region EVSSP.

As described above, when the compensating metal layer 160 is formed only on the non-display area NA, it is independent of the light transmittance in the display area AA direction, so it can be formed as a single layer or multiple layers, and it can be formed with restrictions on thickness. can be avoided

<Second Embodiment>

12 is a cross-sectional view showing a non-display area of a power design unit according to a second embodiment of the present invention, and FIG. 13 is a first hierarchical diagram briefly showing a connection structure between an upper electrode and a low potential power line shown in FIG. 12, FIG. 14 is a second hierarchical view schematically illustrating a connection structure between an upper electrode and a low potential power line shown in FIG. 12 .

As shown in FIG. 12 , the non-display area NA of the display panel includes a margin area EMP, a low potential power line area EVSSP, and a gate in-panel area GIP. The gate-in-panel area GIP is positioned outside the display area AA. The low potential power line region EVSSP is positioned outside the gate-in-panel region GIP. The margin area EMP is positioned outside the low potential power line area EVSSP.

The margin area EMP is defined as an area for preparing an extra space when the first substrate 150a and the second substrate (not shown) are bonded and sealed using an adhesive member or the like. The low potential power line area EVSSP is defined as an area that can be used when forming a low potential power line on the first substrate 150a. The gate-in-panel region GIP is defined as a region that can be used when forming a shift register or the like, which is a part formed by a gate-in-panel method in a gate driver (not shown).

The first substrate 150a includes a first layer BP and a second layer PI. The first layer (BP) serves as a back plate for maintaining the ductility and reinforcing the rigidity of the second layer (PI). For example, the first layer BP may be selected from polyethylene terephthalate (PET), and the second layer PI may be selected from polyimide (PI), but is not limited thereto.

On the first substrate 150a, starting from the buffer layer BUF to the upper electrode layer 159, which is the uppermost layer, is formed. In the non-display area NA, there are low potential power lines, etc., and in the display area AA, transistor arrays (transistors, capacitors, etc.), organic light emitting diodes, etc. are present. Hereinafter, the interlayer structure formed on the first substrate 150a without distinction between the display area AA and the non-display area NA will be described.

A buffer layer BUF is formed on the first substrate 150a. The buffer layer BUF may have a structure including a single-layer buffer layer, a multi-layer buffer layer, or a single-layer buffer layer and a multi-layer buffer layer. The buffer layer BUF may be selected from among silicon (Si)-based SiOx, SiNx, and SiON.

A gate metal layer 151 is formed on the buffer layer BUF. The gate metal layer 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof. It may be, and it may be made of a single layer or multiple layers. The gate metal layer 151 is divided into a gate electrode of a transistor, gate lines connected to the gate electrode, and gate pads connected to the gate lines by a patterning process.

A first insulating layer 152 is formed on the gate metal layer 151 . The first insulating layer 152 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). The first insulating layer 152 may be defined as a gate insulating layer.

A source-drain metal layer 153 is formed on the first insulating layer 152 . The source-drain metal layer 153 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or a mixture thereof. It may be an alloy, and may consist of a single layer or multiple layers. The source-drain metal layer 153 is divided into source and drain electrodes of the transistor, data lines connected to the source or drain electrodes, and data pads connected to the data lines by a patterning process.

A second insulating layer 154 is formed on the source-drain metal layer 153 . The second insulating layer 154 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). The second insulating layer 154 may be cut with a protective layer.

A planarization layer 155 is formed on the second insulating layer 154 . The planarization layer 155 is a layer covering the transistor array portion and is selected from an organic material such as photoacrylic (PAC) or a coating layer that can serve to planarize the upper surface.

A lower electrode layer 156 is formed on the planarization layer 155 . The lower electrode layer 156 is made of a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum-doped zinc oxide (AZO). The lower electrode layer 156 is divided into a lower electrode (eg, an anode electrode) of an organic light emitting diode, a connection electrode of a low potential power line, and the like by a patterning process.

A bank layer BNK is formed on the lower electrode layer 156 . The bank layer BNK may be an organic insulating layer or an inorganic insulating layer. The bank layer BNK may be defined as a pixel defining layer defining an opening area of an organic light emitting diode.

A reflective electrode layer 157 is formed on the bank layer BNK. The reflective electrode layer 157 is selected from a material having high reflectivity, such as aluminum (Al) or silver (Ag), to transmit light generated from the organic light emitting layer 158 in the direction of the upper electrode layer 159 .

An organic light emitting layer 158 is formed on the reflective electrode layer 157 . The organic light emitting layer 158 is selected from a light emitting material that emits red, green, blue or white light. The organic emission layer 158 has a hierarchical structure such as a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer, or a structure in which other functional layers are added.

An upper electrode layer 159 is formed on the organic light emitting layer 158 . The upper electrode layer 159 is formed in the form of a front electrode to be positioned in portions of the display area AA and the non-display area NA, and is formed of a light-transmitting material or thin enough to transmit light. The upper electrode layer 159 becomes an upper electrode (eg, a cathode electrode) of an organic light emitting diode and has a region connected to a low potential power line.

The compensation metal layer 160 is formed on the upper electrode layer 159 and the source-drain metal layer 153 . The compensation metal layer 160 may be formed as a single layer. The compensation metal layer 160 serves to lower resistance when electrically connecting the upper electrode layer 159 and the low potential power supply line (EVSS), and a description thereof is as follows.

As shown in FIGS. 12 and 13 , the source-drain metal layer 153 existing on the upper layer of the low potential power line region EVSSP becomes the low potential power line EVSS. Since the upper electrode layer 159 existing on the uppermost layer of the gate-in-panel region GIP is selected as the cathode electrode of the organic light emitting diode, low potential power is supplied through the low potential power line EVSS.

Due to structural characteristics, the organic light emitting display device cannot directly connect the upper electrode layer 159 and the low potential power supply line (EVSS) (electrodes and lines are spaced apart from each other). In addition, in the case of a top emission organic light emitting display device, due to structural characteristics, the sheet resistance of the upper electrode layer 159 is high, and ΔVSS of the low potential power supply line EVSS increases when a power source is configured only with the upper electrode layer 159.

Therefore, in the second embodiment, the compensation metal layer 160 is further formed on the lower electrode layer 156 serving as a connection electrode between the upper electrode layer 159 and the low potential power line EVSS. The compensation metal layer 160 may be selected from a material having low sheet resistance, such as a single metal material such as copper (Cu) or silver (Ag) or an alloy material such as nickel chrome (NiCr) or nickel copper (NiCu), but is limited thereto It doesn't work.

The compensation metal layer 160 is formed from the display area AA to the low potential power line area EVSSP. The second insulating layer 154 positioned in the low potential power line region EVSSP has a contact hole exposing a portion of the source-drain metal layer 153 . Accordingly, the compensation metal layer 160 contacts the upper electrode layer 159 on the uppermost layer of the gate-in-panel region GIP and the source-drain metal layer 153 on the upper layer of the low potential power line region EVSSP.

As another example, the bank layer BNK positioned in the low potential power line region EVSSP may have a contact hole exposing a side surface (or side wall) of the lower electrode layer 156 as shown. To this end, the lower electrode layer 156 is formed to cover the side surface of the planarization layer 155 . The bank layer BNK exposes part (or all) of the lower electrode layer 156 formed to cover the side surface of the planarization layer 155 .

In this case, the compensation metal layer 160 includes the upper electrode layer 159 on the uppermost layer of the gate-in-panel region GIP, the source-drain metal layer 153 on the upper layer of the low potential power line region EVSSP, and the low potential. It contacts the side surface of the lower electrode layer 156 in the power line area EVSSP.

That is, the compensation metal layer 160 is formed in a structure in contact with two or more layers of the upper electrode layer 159 and the source-drain metal layer 153, or the upper electrode layer 159, the lower electrode layer 156, and the source-drain metal layer 153 or more. It can be formed into a structure in contact with three layers.

As shown in FIGS. 12 and 14 , when the compensating metal layer 160 is formed on the display area AA and the non-display area NA, light transmittance in the direction of the display area AA may be inhibited. Therefore, in the second embodiment, the compensation metal layer 160 is formed in multiple layers, but the thickness of the display area AA is thin while the thickness of the non-display area NA is thick. When the compensation metal layer 160 is formed, if the non-display area NA is made thicker than the display area AA, the transmittance deterioration problem can be solved and the total resistance of the low-potential power line can be further reduced.

In the second embodiment of the present invention, in order to implement a narrow bezel by minimizing the power design area occupying the bezel area, a reinforcing material having low sheet resistance is applied from the display area AA to the low potential power line area EVSSP. ) is used to form a structure.

As a result of the experiment, it was found that the structure of the second embodiment can further narrow the bezel area as can be seen through comparison between the EVSSP area of FIG. 7 shown in FIGS. 13 and 14 and the EVSSP area of the embodiment.

As a result of the experiment, it was found that the structure of the second embodiment further reduced the total resistance of the low-potential power line compared to the conventional structure (total resistance decreased due to the addition of a resistor with a low sheet resistance to the parallel resistance structure) compared to the conventional structure. Also, the total resistance of the low-potential power line was found to be more reduced when a structure in which the compensating metal layer 160 contacts three layers than a structure in which the compensating metal layer 160 contacts two layers.

It is predicted that the conditions for implementing a display device with a high resolution and a narrow bezel can be satisfied by using the power supply structure as described above in the second embodiment. However, even if the target of the display device is not a narrow bezel but requires low power consumption, since ΔVSS can be lowered than before, it is possible to change the structure to use a lower electric potential power supply (EVDD) than before.

Hereinafter, a manufacturing method for power design according to a second embodiment of the present invention will be described. However, in the following, only the upper electrode layer and the compensation metal layer formation part directly related to the characteristics of the present invention will be described.

15 is a view for explaining a manufacturing method related to forming an upper electrode layer, and FIG. 16 is a view for explaining a manufacturing method related to forming a compensation metal layer.

During the transistor array process, a low potential power line corresponding to the power supply unit is formed in the non-display area NA by using a metal layer, and the upper electrode layer 159 is formed in the display area AA by using thermal evaporation as a subsequent process. form on the front

As shown in FIG. 15 , the upper electrode layer 159 is formed by a first mask CMSK having an open portion OPN (NOPN is a blocking portion) exposing a portion of the display area AA and the non-display area NA. do. As shown in FIG. 16 , the compensation metal layer 160 is formed by a second mask NMSK having an open portion OPN exposing a portion of the display area AA to the non-display area NA. As a result, the compensation metal layer 160 is formed from the display area AA to the low potential power line area EVSSP.

As described above, when the compensating metal layer 160 is formed on the display area AA and the non-display area NA, light transmittance in the direction of the display area AA may be inhibited. Therefore, in the second embodiment, the compensation metal layer 160 is formed in multiple layers, but the thickness of the display area AA is thin while the thickness of the non-display area NA is thick.

To this end, the first layer of the compensation metal layer 160 is designed to be exposed from the display area AA to the non-display area NA, and the second layer is designed to cover the gate-in-panel area GIP to the non-display area NA. It is desirable to design it to expose up to.

On the other hand, according to the first and second embodiments of the present invention, the compensation metal layer 160 takes a form surrounding all four sides of the non-display area NA. However, as in the third embodiment below, the compensation metal layer 160 may be formed only on one side and the other side of the non-display area NA.

<Third Embodiment>

17 is a plan view illustrating a display area and a non-display area of a power design unit according to a third embodiment of the present invention.

As shown in FIG. 17 , the compensating metal layer 160 is formed in a stick or bar shape on the left and right sides of the non-display area NA ( FIG. 16 a ), or the non-display area NA ) It may be formed in the form of a stick or bar on the upper and lower sides. If the compensation metal layer 160 is formed in the structure shown in FIG. 17 , ΔVSS of the low potential power line EVSS can be lowered and process tact time can be advanced.

In addition, referring to the third embodiment of FIG. 17 , when the compensation metal layer of the second layer added in the second embodiment is formed in the form of (a) or (b) of FIG. 17, the direction of the display area (AA) It can be seen that there is an advantage in that the compensation metal layer can be formed without considering the light transmittance or thickness limitation of .

18 is a simulation result graph of a conventionally proposed power source structure and a power source structure according to the first embodiment of the present invention.

As shown in FIG. 18, the conventionally proposed power source structure (a in FIG. 18) can lower the EVSS rising problem to about 0.24V. On the other hand, the power supply structure according to the first embodiment of the present invention (FIG. 18B) can lower the EVSS Rising problem to about 0.19V compared to the conventional structure. Meanwhile, the simulation result of FIG. 18 is based on a small (3.64 inch) display panel.

As described above, the present invention has an effect of providing an organic light emitting display device capable of implementing a narrow bezel while preventing a low potential power supply problem by further forming a compensation metal layer. In addition, the present invention has an effect of configuring a compensation metal layer using various metal materials (Cu, Ag, NiCr, NiCu, etc.). In addition, since the present invention configures the compensation metal layer based on a material having low sheet resistance, the deposited area, thickness, and shape can be changed according to a target specification, there is an effect of increasing the degree of freedom in design. In addition, the present invention can implement a narrow bezel while maintaining the same low-potential power-up level, and can relatively reduce the low-potential power-up level when implementing a display panel with the same size of the bezel, thereby maximizing the performance of the display panel. It works. In addition, the present invention has the effect of realizing a device requiring low power consumption by using the compensating metal layer. The present invention has an effect of implementing a narrow bezel while preventing a problem of low potential power rise, and designing a power supply according to a target specification or enabling a flexible design by requiring low power consumption.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driver 140: gate driver
150: display panel 150a: first substrate
AA: display area NA: non-display area
EMP: margin area EVSSP: low potential power line area
GIP: gate-in-panel region 160: compensation metal layer
159: upper electrode layer 153: source drain metal layer
156: lower electrode layer

Claims (11)

a non-display area including a display area defined on the first substrate, a gate-in-panel area positioned outside the display area, and a low potential power line area positioned outside the gate-in-panel area;
a low potential power line located in a low potential power line area on the first substrate;
a lower electrode layer insulated by an insulating layer positioned on the low potential power line, positioned from the low potential power line area to the gate-in-panel area, and connected to the low potential power line;
an upper electrode layer insulated by an insulating layer positioned on the lower electrode layer, positioned from the display area to the gate-in-panel area, and connected to the lower electrode layer; and
and a compensation metal layer disposed on the upper electrode layer and electrically connecting the low potential power line and the upper electrode layer. According to claim 1,
The compensating metal layer is
An organic light emitting display device in contact with the low potential power line, the lower electrode layer, and the upper electrode layer. According to claim 1,
The compensating metal layer is
The organic light emitting display device of claim 1 , wherein the gate-in-panel area contacts the upper electrode layer, and the low potential power line area contacts side surfaces of the lower electrode layer and the low potential power line. According to claim 1,
The low potential power line is made of the same material as the source and drain electrodes in the display area. According to claim 1,
a gate metal layer positioned in the gate-in-panel region on the first substrate;
A first insulating layer positioned on the gate metal layer;
a source-drain metal layer positioned in the low potential power line region on the first insulating layer;
a second insulating layer positioned on the source-drain metal layer;
A planarization layer positioned on the second insulating layer;
the lower electrode layer positioned from the low potential power line region to the gate-in-panel region on the planarization layer;
a bank layer positioned on the lower electrode layer;
an organic light emitting layer positioned in the display area on the bank layer;
an upper electrode layer positioned from the display area on the organic light emitting layer to the gate-in-panel area;
The source-drain metal layer is the low potential power line. According to claim 5,
The compensating metal layer is
An organic light emitting display device positioned from the low potential power line region to the gate-in-panel region. According to claim 5,
The compensating metal layer is
An organic light emitting display device positioned from the low potential power line area to the display area. According to claim 7,
The compensating metal layer is
An organic light emitting display device comprising multiple layers, wherein a thickness of the compensation metal layer in the non-display area is greater than a thickness of the compensation metal layer in the display area. defining a display area on a first substrate, and defining a non-display area including a gate-in-panel area outside the display area and a low potential power line area outside the gate-in-panel area;
forming a gate metal layer in the gate-in-panel region on the first substrate;
forming a first insulating layer on the gate metal layer;
forming a source-drain metal layer serving as a low-potential power line in the low-potential power line region on the first insulating layer;
forming a second insulating layer on the source-drain metal layer;
forming a planarization layer on the second insulating layer;
forming a lower electrode layer from the low potential power line region on the planarization layer to the gate-in-panel region to be connected to the low potential power line;
forming a bank layer on the lower electrode layer;
forming an organic light emitting layer in the display area on the bank layer;
forming an upper electrode layer from the display area on the organic light emitting layer to the gate-in-panel area so as to be connected to the lower electrode layer; and
and forming a compensation metal layer on the upper electrode layer so that the low potential power line and the upper electrode layer are electrically connected. According to claim 9,
patterning the second insulating layer to expose a portion of the source-drain metal layer in the low potential power line region;
and patterning the bank layer so that a side surface of the lower electrode layer is exposed in the low potential power line region. According to claim 9,
Forming the compensation metal layer
Manufacture of an organic light emitting display device in which the compensation metal layer is formed of a single layer made of a single metal material of copper (Cu) or silver (Ag) or a multi-layer made of an alloy material of nickel chromium (NiCr) or nickel copper (NiCu) Way.

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