KR101114261B1 - Method for forming inter layer dielectric in semiconductor device - Google Patents

Method for forming inter layer dielectric in semiconductor device Download PDF

Info

Publication number
KR101114261B1
KR101114261B1 KR1020050058567A KR20050058567A KR101114261B1 KR 101114261 B1 KR101114261 B1 KR 101114261B1 KR 1020050058567 A KR1020050058567 A KR 1020050058567A KR 20050058567 A KR20050058567 A KR 20050058567A KR 101114261 B1 KR101114261 B1 KR 101114261B1
Authority
KR
South Korea
Prior art keywords
forming
interlayer insulating
insulating film
semiconductor device
oxidation process
Prior art date
Application number
KR1020050058567A
Other languages
Korean (ko)
Other versions
KR20070002870A (en
Inventor
조흥재
임관용
성민규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050058567A priority Critical patent/KR101114261B1/en
Publication of KR20070002870A publication Critical patent/KR20070002870A/en
Application granted granted Critical
Publication of KR101114261B1 publication Critical patent/KR101114261B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 게이트 스택과 같은 전도체 스택 사이를 절연시키기 위한 층간절연막 형성시 보이드가 발생하는 것을 방지할 수 있는 반도체소자의 층간절연막 형성 방법을 제공하기 위한 것으로, 본 발명의 반도체소자의 층간절연막 형성 방법은 반도체 기판 상에 전극물질과 하드마스크질화막의 순서로 적층되는 전도체 스택을 형성하는 단계, 상기 전도체 스택의 양측벽에 접하는 스페이서를 형성하는 단계, 상기 스페이서의 표면 일부를 산화시켜 산화막시드층을 형성하는 단계, 및 상기 산화막시드층을 시드로 이용하여 상기 전도체 스택 사이를 갭필하는 층간절연막을 형성하는 단계를 포함하며, 이와 같은 본 발명은 라디칼산화 공정을 통해 하부구조물을 산화시켜 산화막시드층을 미리 형성해주고, 이 산화막 시드층을 시드로 이용하므로 보이드없이 층간절연막을 갭필하여 반도체소자의 전기적 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention is to provide a method for forming an interlayer insulating film of a semiconductor device capable of preventing voids from occurring when forming an interlayer insulating film for insulating between conductor stacks such as a gate stack, and the method for forming an interlayer insulating film of a semiconductor device of the present invention. Forming a conductor stack stacked on the semiconductor substrate in the order of an electrode material and a hard mask nitride film, forming a spacer in contact with both sidewalls of the conductor stack, and oxidizing a portion of a surface of the spacer to form an oxide film seed layer. And forming an interlayer insulating film gap-filling between the conductor stacks using the oxide seed layer as a seed, and the present invention oxidizes a substructure through a radical oxidation process to prepare an oxide film seed layer in advance. And use this oxide seed layer as a seed so that no void Gaeppil by an interlayer insulating film is effective to improve the electrical reliability of the semiconductor device.

층간절연막, 산화막시드층, 라디칼산화, 라디칼산소원자 Interlayer insulating film, oxide film seed layer, radical oxidation, radical oxygen atom

Description

반도체소자의 층간절연막 형성 방법{METHOD FOR FORMING INTER LAYER DIELECTRIC IN SEMICONDUCTOR DEVICE}METHODS FOR FORMING INTER LAYER DIELECTRIC IN SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체소자의 층간절연막 형성 방법을 간략히 도시한 도면,1 is a view schematically illustrating a method for forming an interlayer insulating film of a semiconductor device according to the prior art;

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성 방법을 도시한 공정 단면도.2A to 2C are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

21 : 반도체 기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film

23 : 폴리실리콘 24 : 텅스텐실리사이드23 polysilicon 24 tungsten silicide

25 : 게이트하드마스크질화막 26b : 게이트스페이서25: gate hard mask nitride film 26b: gate spacer

27 : 산화막시드층 28 : 층간절연막27 oxide film seed layer 28 interlayer insulating film

200 : 게이트스택200: gate stack

본 발명은 반도체 제조기술에 관한 것으로, 특히 보이드가 발생하지 않는 층간절연막의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of forming an interlayer insulating film in which voids do not occur.

반도체소자의 집적도가증가함에 따라 트랜지스터 또는 게이트전극 사이를 절연시키는 층간절연기술이 중요하게 된다. 특히, 집적도와 게이트전극의 스택 높이가 높아짐에 따라 절연막이 채워질 종횡비(Aspect ratio)가 커지기 때문에, 절연막을 갭필(Gapfill)시키기 어려워 보이드(Void)가 발생한다.As the degree of integration of semiconductor devices increases, the interlayer insulation technology to insulate between transistors or gate electrodes becomes important. In particular, as the integration ratio and the stack height of the gate electrode are increased, the aspect ratio for filling the insulating layer increases, making voids difficult to gapfill the insulating layer.

이렇게 형성된 보이드는 후속 세정 공정들 중에서 절연막의 식각속도를 증가시켜, 결국에는 게이트전극 사이의 절연막이 모두 제거되어 DC Fail를 발생시켜 수율을 감소시키는 문제를 초래한다.The voids thus formed increase the etching rate of the insulating film during subsequent cleaning processes, and eventually, all the insulating films between the gate electrodes are removed, resulting in a DC fail to reduce the yield.

도 1은 종래기술에 따른 반도체소자의 층간절연막 형성 방법을 간략히 도시한 도면이다.1 is a view briefly illustrating a method for forming an interlayer insulating film of a semiconductor device according to the prior art.

도 1에 도시된 바와 같이, 반도체기판(11) 상에 게이트산화막(12)을 형성한 후, 게이트산화막(12) 상에 폴리실리콘(13), 텅스텐실리사이드(14) 및 게이트하드마스크질화막(15)의 순서로 적층되는 게이트 스택(100)을 형성한다.As shown in FIG. 1, after the gate oxide film 12 is formed on the semiconductor substrate 11, the polysilicon 13, the tungsten silicide 14, and the gate hard mask nitride film 15 are formed on the gate oxide film 12. The gate stacks 100 stacked in the order of FIG.

이어서, 게이트 스택(100)을 포함한 전면에 스페이서질화막을 증착한 후, 스페이서식각을 진행하여 게이트스택(100)의 양측벽에 접하는 게이트스페이서(16)를 형성한다. 이때, 반도체 기판(11) 상부에 스페이서질화막(16a)이 잔류할 수 있다.Subsequently, after the spacer nitride film is deposited on the entire surface including the gate stack 100, spacer etching is performed to form gate spacers 16 that are in contact with both sidewalls of the gate stack 100. In this case, the spacer nitride layer 16a may remain on the semiconductor substrate 11.

이어서, 게이트스페이서(16)를 포함한 전면에 게이트스택(100) 사이를 갭필하는 층간절연막(Inter Layer Dielectric, 17)을 형성한다.Subsequently, an interlayer dielectric 17 is formed on the entire surface including the gate spacer 16 to gap-fill the gate stack 100.

그러나, 종래기술은 층간절연막(17) 형성시 게이트스택(100) 사이에서 층간절연막(17)이 완전히 채워지지 않고 비어있는 보이드(V)가 발생하는 문제가 있다. 이때, 보이드(V)가 발생하는 이유는 게이트스택(100)의 높이가 높아짐에 따라 종횡비가 증가하게 되고, 이러한 높은 종횡비를 갖는 게이트스택(100) 사이의 공간을 모두 채우기 전에 게이트스택(100) 상부에서 층간절연막(17)이 형성되기 때문이다.However, the related art has a problem in that the void V is generated without the interlayer insulating layer 17 being completely filled between the gate stacks 100 when the interlayer insulating layer 17 is formed. At this time, the reason why the void (V) occurs is that the aspect ratio increases as the height of the gate stack 100 increases, the gate stack 100 before filling all the space between the gate stack 100 having such a high aspect ratio This is because the interlayer insulating film 17 is formed thereon.

이러한 보이드 문제를 비단 게이트전극은 물론 반도체소자 제조 공정시 높이가 증가하는 비트라인 등의 전도체 사이를 절연하기 위한 층간절연막 형성시에도 발생한다.This void problem occurs not only in the gate electrode but also in the formation of an interlayer insulating film for insulating between conductors, such as bit lines, of which height increases during a semiconductor device manufacturing process.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 게이트스택과 같은 전도체 사이를 절연시키기 위한 층간절연막 형성시 보이드가 발생하는 것을 방지할 수 있는 반도체소자의 층간절연막 형성 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a method for forming an interlayer insulating film of a semiconductor device capable of preventing voids from occurring when forming an interlayer insulating film for insulating between conductors such as a gate stack. The purpose is.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 층간절연막 형성 방법은 반도체 기판 상에 전극물질과 하드마스크질화막의 순서로 적층되는 전도체 스택을 형성하는 단계, 상기 전도체 스택의 양측벽에 접하는 스페이서를 형성하는 단계, 상기 스페이서의 표면 일부를 산화시켜 산화막시드층을 형성하는 단계, 및 상기 산 화막시드층을 시드로 이용하여 상기 전도체 스택 사이를 갭필하는 층간절연막을 형성하는 단계를 포함하는 것을 특징으로 하며, 상기 산화막시드층을 형성하는 단계는 라디칼산화 공정으로 진행하는 것을 특징으로 하고, 상기 라디칼산화 공정은, 열라디칼산화공정 또는 플라즈마산화공정으로 진행하는 것을 특징으로 하며, 상기 열라디칼산화 공정은 700℃～ 1000℃의 온도와 10mTorr～100Torr의 저압에서 진행하며, 산화분위기는 H2/O2의 혼합가스 또는 D2/O2의 혼합가스를 이용하는 것을 특징으로 하고, 상기 플라즈마산화공정은 25℃～700℃의 저온에서 진행하며, 산화소스는 O2, H2/O2 또는 D2/O2 중에서 선택되고, 플라즈마를 형성하기 위해서 소스플라즈마파워는 10W～5000W로 인가하고, 바이어스플라즈마파워는 0W～1000W로 인가하여 진행하는 것을 특징으로 하며, 상기 플라즈마 산화 공정시, 압력은 10mTorr～100Torr의 고압을 유지하고, 플라즈마처리시간은 5초～500초동안 진행하며, 산화소스의 유량은 5sccm～5000sccm으로 하는 것을 특징으로 한다.In the method for forming an interlayer insulating film of a semiconductor device of the present invention for achieving the above object, forming a conductor stack stacked in the order of an electrode material and a hard mask nitride film on a semiconductor substrate, forming a spacer in contact with both side walls of the conductor stack And forming an oxide film seed layer by oxidizing a portion of the surface of the spacer, and forming an interlayer insulating film gap gap between the conductor stacks using the oxide film seed layer as a seed. The forming of the oxide film seed layer may be performed by a radical oxidation process, wherein the radical oxidation process may be performed by a thermal radical oxidation process or a plasma oxidation process, and the thermal radical oxidation process is 700 It proceeds at a temperature of ℃ ～ 1000 ℃ and low pressure of 10mTorr ~ 100Torr, and the oxidation atmosphere is H 2 / O wherein the second using a mixed gas of the mixed gas or D 2 / O 2 in, and the plasma oxidation process proceeds at a low temperature of 25 ℃ ~ 700 ℃, oxidation source is O 2, H 2 / O 2 Or D 2 / O 2 , wherein source plasma power is applied at 10 W to 5000 W, and bias plasma power is applied at 0 W to 1000 W to form a plasma. Is maintained at a high pressure of 10mTorr ~ 100Torr, the plasma treatment time is 5 seconds to 500 seconds, the flow rate of the oxidation source is characterized in that 5sccm ~ 5000sccm.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21) 상에 게이트산화막(22)을 형성한 후, 게이트산화막(22) 상에 폴리실리콘(23), 텅스텐실리사이드(24) 및 게이트하드마스크질화막(25)의 순서로 적층되는 게이트 스택(200)을 형성한다.As shown in FIG. 2A, after the gate oxide layer 22 is formed on the semiconductor substrate 21, the polysilicon 23, the tungsten silicide 24, and the gate hard mask nitride layer 25 are formed on the gate oxide layer 22. The gate stacks 200 stacked in the order of FIG.

이어서, 게이트 스택(200)을 포함한 전면에 스페이서질화막을 증착한 후, 스페이서식각을 진행하여 게이트스택(200)의 양측벽에 접하는 게이트스페이서(26b)를 형성한다. 이때, 스페이서질화막은 SiN으로 형성한다.Subsequently, a spacer nitride film is deposited on the entire surface including the gate stack 200, and then spacer etching is performed to form gate spacers 26b contacting both sidewalls of the gate stack 200. At this time, the spacer nitride film is formed of SiN.

이러한 스페이서식각후에 게이트 스택(200) 사이의 반도체기판(21) 상부에는 스페이서질화막(26a)이 잔류할 수 있다. 예를 들어, 스페이서식각후에 콘택식각배리어 물질로 질화막을 추가로 증착할 수 있기 때문에, 층간절연막이 증착될 하부구조가 질화막 물질이 형성된 상태라 가정하는 것이다.After the spacer etching, the spacer nitride layer 26a may remain on the semiconductor substrate 21 between the gate stacks 200. For example, since the nitride film may be further deposited with the contact etching barrier material after the spacer etching, it is assumed that the underlying structure on which the interlayer insulating film is to be deposited is formed with the nitride film material.

도 2b에 도시된 바와 같이, 질화막 계열의 물질이 형성된 하부구조물에 대해 라디칼산화(Radical oxidation) 공정을 진행하여 잔류하는 스페이서질화막(26a) 및 게이트스페이서(26b)의 표면 일부를 산화시킨다. 이때, 게이트하드마스크질화막(25)도 표면 일부가 산화된다.As shown in FIG. 2B, a radical oxidation process is performed on the substructure on which the nitride film-based material is formed to oxidize a portion of the surface of the spacer nitride film 26a and the gate spacer 26b that remain. At this time, a part of the surface of the gate hard mask nitride film 25 is also oxidized.

이러한 라디칼산화 공정에 의해 잔류하는 스페이서질화막(26a)이 산화되어 형성된 산화막(27a), 게이트스페이서(26b)가 산화되어 형성된 산화막(27b)과 게이트하드마스크질화막(25)이 산화되어 형성된 산화막(27c)이 형성되고, 이러한 산화막(27a, 27b, 27c)은 5Å～100Å 두께이다.The oxide film 27c formed by oxidizing the spacer nitride film 26a remaining by the radical oxidation process and the oxide film 27b formed by oxidizing the gate spacer 26b and the gate hard mask nitride film 25 are oxidized. ) Is formed, and the oxide films 27a, 27b, and 27c are 5 kPa to 100 kPa thick.

라디칼산화 공정은 통상적인 산화공정과는 다르게, 라디칼산소원자(Radical oxygen atom)를 이용하기 때문에, 스페이서질화막(26a)도 산화시킬 수 있다. 여기서, 라디칼산화공정에 의해 형성된 산화막(27a, 27b, 27c)은 후속 층간절연막 증착 시 시드층으로 작용하기 때문에 보이드가 없는 층간절연막의 갭필이 가능해진다. 이하, 산화막(27a, 27b, 27c)을 '산화막시드층(27)'이라고 약칭한다.Unlike the normal oxidation process, the radical oxidation process uses a radical oxygen atom, so that the spacer nitride film 26a can also be oxidized. Here, the oxide films 27a, 27b, and 27c formed by the radical oxidation process act as seed layers during subsequent interlayer insulating film deposition, thereby enabling gap fill of the void free interlayer insulating film. Hereinafter, the oxide films 27a, 27b, and 27c are abbreviated as "oxide film seed layers 27".

상기 라디칼산화 공정은 열라디칼산화(Thermal radical oxidation) 공정 또는 플라즈마산화(Plasma oxidation) 공정을 이용한다. 여기서, 플라즈마산화 공정은 열라디칼산화공정에 비해 낮은 온도에서 플라즈마를 이용하여 라디칼산소원자를 형성하는 산화 공정이다.The radical oxidation process uses a thermal radical oxidation process or a plasma oxidation process. Here, the plasma oxidation process is an oxidation process for forming radical oxygen atoms using plasma at a lower temperature than the thermal radical oxidation process.

먼저, 열라디칼산화 공정은 700℃～ 1000℃의 온도와 10mTorr～100Torr의 저압에서 진행하며, 산화분위기는 H2/O2의 혼합가스 또는 D2/O2[여기서, D는 중수소(Deuterium)를 일컫는다]의 혼합가스를 이용한다. First, the thermal radical oxidation process is carried out at a temperature of 700 ℃ to 1000 ℃ and a low pressure of 10 mTorr ~ 100 Torr, the oxidation atmosphere is a mixed gas of H 2 / O 2 or D 2 / O 2 [where D is deuterium (Deuterium) ] Is used.

그리고,플라즈마 산화 공정은 25℃～700℃의 저온에서 진행하며, 산화소스는 O2, H2/O2 또는 D2/O2 중에서 선택되고, 플라즈마를 형성하기 위해서 소스플라즈마파워는 10W～5000W로 인가하고, 바이어스플라즈마파워는 0W～1000W(바이어스파워는 플라즈마중의 라디칼산소원자를 끌어당기는 힘의 정도를 조절하는 것이므로 소스파워가 인가된 상태에서는 0W를 인가할 수도 있다)로 인가한다. 그리고, 플라즈마산화공정시, 압력은 10mTorr～100Torr의 고압을 유지하고, 플라즈마처리시간은 5초～500초동안 진행하며, 산화소스의 유량은 5sccm～5000sccm으로 한다. 한편, 산화소스에 필요에 따라 He, Ar, Kr 또는 Xe 중에서 선택되는 비활성가스를 첨가할 수도 있다. 이러한 비활성가스는 라디칼산소원자의 발생을 원활하게 하는 역할을 한다.The plasma oxidation process is performed at a low temperature of 25 ° C. to 700 ° C., and the oxidation source is selected from O 2 , H 2 / O 2, or D 2 / O 2 , and the source plasma power is 10 W to 5000 W to form a plasma. The bias plasma power is applied to 0W to 1000W (Bias power is to control the degree of the force that pulls radical oxygen atoms in the plasma, so 0W may be applied when the source power is applied). In the plasma oxidation process, the pressure is maintained at a high pressure of 10 mTorr to 100 Torr, the plasma treatment time is 5 seconds to 500 seconds, and the flow rate of the oxidation source is 5 sccm to 5000 sccm. In addition, an inert gas selected from He, Ar, Kr or Xe may be added to the oxidation source as needed. This inert gas serves to facilitate the generation of radical oxygen atoms.

전술한 바와 같은 열라디칼산화공정 또는 플라즈마산화공정을 이용하면, 게이트스택의 텅스텐실리사이드(24) 및 폴리실리콘(23)은 산화시키지 않고 선택적으로 질화막 물질인 게이트하드마스크질화막(25), 게이트스페이서(26b)의 표면 일부만 산화시킬 수 있다.By using the thermal radical oxidation process or the plasma oxidation process as described above, the tungsten silicide 24 and the polysilicon 23 of the gate stack are not oxidized, but the gate hard mask nitride film 25 and the gate spacer ( Only part of the surface of 26b) can be oxidized.

도 2c에 도시된 바와 같이, 산화막시드층(27)이 형성된 상태에서 층간절연막(28)을 증착한다. 이때, 층간절연막(28)은 BPSG, HDP 산화막과 같은 산화막 물질로 형성하는데, 산화막시드층(27)이 층간절연막(28) 증착시 시드층 역할을 하여 층간절연막(28)이 보이드없이 게이트스택(200) 사이를 갭필한다.As shown in FIG. 2C, the interlayer insulating film 28 is deposited in the state where the oxide film seed layer 27 is formed. At this time, the interlayer insulating film 28 is formed of an oxide film material such as BPSG and HDP oxide film. The oxide film seed layer 27 serves as a seed layer when the interlayer insulating film 28 is deposited, so that the interlayer insulating film 28 is free of gate stacks without voids. 200).

즉, 산화막시드층(27)이 존재한 상태에서 층간절연막(28)을 증착하면, 게이트스택(200) 사이의 공간에서 층간절연막(28)의 증착속도가 매우 빠르게 되어 보이드없이 층간절연막(28)을 증착할 수 있다. 예컨대, 층간절연막(28)이 형성될 하부구조가 스페이서질화막과 같은 질화막이 잔류한 상태에서는 층간절연막(28) 증착시 보이드가 발생하는 것을 피할 수 없으나, 층간절연막(28)과 동일계열의 물질인 산화막시드층(27)이 형성된 상태에서는 보이드없이 층간절연막(28)을 증착할 수 있다.That is, when the interlayer insulating film 28 is deposited in the state where the oxide film seed layer 27 is present, the deposition rate of the interlayer insulating film 28 becomes very fast in the space between the gate stacks 200, and thus the interlayer insulating film 28 is voided. Can be deposited. For example, voids may not be generated during deposition of the interlayer dielectric layer 28 in a state in which a nitride structure such as a spacer nitride layer remains in the underlying structure on which the interlayer dielectric layer 28 is to be formed, but is formed of the same material as the interlayer dielectric layer 28. In the state in which the oxide film seed layer 27 is formed, the interlayer insulating film 28 may be deposited without voids.

상술한 실시예에서는 게이트스택 사이를 채우는 층간절연막의 형성 방법에 대해 설명하였으나, 본 발명은 비트라인 스택 사이를 채우는 층간절연막의 형성 방법에도 산화막시드층을 적용할 수 있다.In the above-described embodiment, the method of forming the interlayer insulating film filling the gaps between the gate stacks has been described. However, the present invention may also apply the oxide seed layer to the method of forming the interlayer insulating film filling the gaps between the bit line stacks.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여 야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 라디칼산화 공정을 통해 하부구조물을 산화시켜 산화막시드층을 미리 형성해주고, 이 산화막 시드층을 시드로 이용하므로 보이드없이 층간절연막을 갭필하여 반도체소자의 전기적 신뢰성을 향상시킬 수 있는 효과가 있다.According to the present invention, the oxide structure is pre-formed by oxidizing a lower structure through a radical oxidation process, and since the oxide seed layer is used as a seed, an interlayer insulating film can be gap-filled without voids to improve electrical reliability of a semiconductor device. There is.

Claims (11)

반도체 기판 상에 전극물질과 하드마스크질화막의 순서로 적층되는 전도체 스택을 형성하는 단계;Forming a conductor stack stacked on the semiconductor substrate in the order of the electrode material and the hard mask nitride film; 상기 전도체 스택의 양측벽에 접하는 질화막 스페이서를 형성하는 단계;Forming a nitride film spacer in contact with both sidewalls of the conductor stack; 상기 질화막 스페이서의 표면 일부를 산화시켜 산화막시드층을 형성하는 단계; 및Oxidizing a portion of the surface of the nitride film spacer to form an oxide film seed layer; And 상기 산화막시드층을 시드로 이용하여 상기 전도체 스택 사이를 갭필하는 층간절연막을 형성하는 단계Forming an interlayer dielectric layer having a gap fill between the conductor stacks using the oxide seed layer as a seed; 를 포함하는 반도체소자의 층간절연막 형성 방법.Method for forming an interlayer insulating film of a semiconductor device comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제1항에 있어서,The method of claim 1, 상기 산화막시드층을 형성하는 단계는,Forming the oxide seed layer, 라디칼산화 공정으로 진행하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.A method of forming an interlayer insulating film of a semiconductor device, characterized by progressing to a radical oxidation process. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제2항에 있어서,3. The method of claim 2, 상기 라디칼산화 공정은, 열라디칼산화공정으로 진행하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.The radical oxidation process is a thermal radical oxidation process, the method of forming an interlayer insulating film of a semiconductor device. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제3항에 있어서,The method of claim 3, 상기 열라디칼산화 공정은,The thermal radical oxidation process, 700℃～ 1000℃의 온도와 10mTorr～100Torr의 저압에서 진행하며, 산화분위기는 H2/O2의 혼합가스 또는 D2/O2의 혼합가스를 이용하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.Method of forming an interlayer insulating film of a semiconductor device, characterized in that the temperature is carried out at a temperature of 700 ℃ ~ 1000 ℃ and low pressure of 10mTorr ~ 100Torr, the oxidation atmosphere using a mixed gas of H 2 / O 2 or a mixed gas of D 2 / O 2 . 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제2항에 있어서,3. The method of claim 2, 상기 라디칼산화 공정은, 플라즈마 산화공정으로 진행하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.The radical oxidation process is a plasma oxidation process, characterized in that the interlayer insulating film forming method of a semiconductor device. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제5항에 있어서,The method of claim 5, 상기 플라즈마산화 공정은,The plasma oxidation process, 25℃～700℃의 저온에서 진행하며, 산화소스는 O2, H2/O2 또는 D2/O2 중에서 선택되고, 플라즈마를 형성하기 위해서 소스플라즈마파워는 10W～5000W로 인가하고, 바이어스플라즈마파워는 0W～1000W로 인가하여 진행하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.It proceeds at a low temperature of 25 ℃ ~ 700 ℃, the oxidation source is selected from O 2 , H 2 / O 2 or D 2 / O 2 , source plasma power is applied from 10W to 5000W to form a plasma, bias plasma A method for forming an interlayer insulating film of a semiconductor device, characterized in that the power is applied at 0W to 1000W. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제6항에 있어서,The method of claim 6, 상기 플라즈마 산화 공정시, 압력은 10mTorr～100Torr의 고압을 유지하고, 플라즈마처리시간은 5초～500초동안 진행하며, 산화소스의 유량은 5sccm～5000sccm으로 하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.During the plasma oxidation process, the pressure is maintained at a high pressure of 10 mTorr to 100 Torr, the plasma treatment time is 5 to 500 seconds, and the flow rate of the oxidizing source is 5 sccm to 5000 sccm. Way. 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제7항에 있어서,The method of claim 7, wherein 상기 플라즈마 산화 공정시, He, Ar, Kr 또는 Xe 중에서 선택되는 비활성가스를 첨가하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.In the plasma oxidation process, an inert gas selected from He, Ar, Kr or Xe is added. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 was abandoned upon payment of a set-up fee. 제1항에 있어서,The method of claim 1, 상기 산화막시드층은,The oxide film seed layer, 5Å～100Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.A method of forming an interlayer insulating film of a semiconductor device, characterized in that formed to a thickness of 5 ~ 100Å. 청구항 10은(는) 설정등록료 납부시 포기되었습니다.Claim 10 was abandoned upon payment of a setup registration fee. 제1항에 있어서, The method of claim 1, 상기 질화막 스페이서의 표면 일부를 산화시켜 산화막시드층을 형성하는 단계에서 상기 하드마스크질화막의 표면 일부도 산화되어 산화막시드층이 형성되는 반도체소자의 층간절연막 형성 방법.And forming a oxide film seed layer by oxidizing a portion of the surface of the nitride spacer to form an oxide film layer, wherein an oxide film seed layer is formed to oxidize a portion of the surface of the hard mask nitride film. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 was abandoned upon payment of a setup registration fee. 제10항에 있어서,The method of claim 10, 상기 전도체 스택은, The conductor stack, 게이트스택 또는 비트라인 스택인 것을 특징으로 하는 반도체소자의 층간절연막 형성 방법.A method of forming an interlayer insulating film of a semiconductor device, characterized in that it is a gate stack or a bit line stack.
KR1020050058567A 2005-06-30 2005-06-30 Method for forming inter layer dielectric in semiconductor device KR101114261B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050058567A KR101114261B1 (en) 2005-06-30 2005-06-30 Method for forming inter layer dielectric in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050058567A KR101114261B1 (en) 2005-06-30 2005-06-30 Method for forming inter layer dielectric in semiconductor device

Publications (2)

Publication Number Publication Date
KR20070002870A KR20070002870A (en) 2007-01-05
KR101114261B1 true KR101114261B1 (en) 2012-03-09

Family

ID=37869800

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050058567A KR101114261B1 (en) 2005-06-30 2005-06-30 Method for forming inter layer dielectric in semiconductor device

Country Status (1)

Country Link
KR (1) KR101114261B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132397A1 (en) * 2001-03-15 2002-09-19 Weimer Ronald A. Use of atomic oxygen process for improved barrier layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132397A1 (en) * 2001-03-15 2002-09-19 Weimer Ronald A. Use of atomic oxygen process for improved barrier layer

Also Published As

Publication number Publication date
KR20070002870A (en) 2007-01-05

Similar Documents

Publication Publication Date Title
US5877074A (en) Method for improving the electrical property of gate in polycide structure
KR101068574B1 (en) Semiconductor device with buried gate and method for fabricating the same
JP3277855B2 (en) Method for forming wiring of semiconductor device
US7087515B2 (en) Method for forming flowable dielectric layer in semiconductor device
KR100972881B1 (en) Method of forming a flash memory device
KR101162480B1 (en) Method for manufacturing insulation layer and method for manufacturing semiconductor device using the same
KR100808601B1 (en) Method for forming multi layer metal wiring of semiconductor device using damascene process
JP5217272B2 (en) Wiring forming method and semiconductor device manufacturing method
KR101114261B1 (en) Method for forming inter layer dielectric in semiconductor device
KR20090020827A (en) Method of forming a metal layer in semiconductor device
KR100611781B1 (en) An isolationing film of semiconductor device and method for forming the same
KR100314809B1 (en) A method for forming damascene gate of semiconductor device
KR100541369B1 (en) Method of forming interconnection line for semiconductor device
KR101103550B1 (en) A method for forming a metal line in semiconductor device
KR100784094B1 (en) Method of forming a dielectric layer in semiconductor device
KR20020092682A (en) Method of Forming Dielectric layer in Semiconductor Device
KR100695487B1 (en) Semiconductor device and method for fabricating using the same
KR100313785B1 (en) Method for forming interlayer dielectric of semiconductor device
KR101033981B1 (en) Method for fabricating semiconductor device
US20100029072A1 (en) Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact Holes
KR100670686B1 (en) Method for manufacturing contact plug in semiconductor device
KR100545699B1 (en) Method for forming plug for capacitor contact of semiconductor device
KR100459063B1 (en) Method for manufacturing intermetal dielectric layer of semiconductor device
KR20000059285A (en) Method for filling a trench
KR100753104B1 (en) Method for manufacturing isolation in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee